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baytrail: add lpss iosf functions and regs

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The low power subsystem devices have a lot of their
configuration done in the IOSF sideband message space.
Add support for these access methods.

BUG=chrome-os-partner:23790
BRANCH=None
TEST=Built and booted through depthcharge.

Change-Id: I0dd52b952a16ef1280c29301164db041ee87f636
Signed-off-by: Aaron Durbin <adurbin@chromum.org>
Reviewed-on: https://chromium-review.googlesource.com/175440
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Tested-by: Aaron Durbin <adurbin@chromium.org>
Commit-Queue: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/4921
Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Aaron Durbin
2013-10-31 10:46:56 -05:00
committed by Aaron Durbin
parent 92fce495a7
commit bc69ae9823
2 changed files with 51 additions and 0 deletions
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22
src/soc/intel/baytrail/iosf.c
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@@ -165,3 +165,25 @@ void iosf_ushphy_write(int reg, uint32_t val)
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
write_iosf_reg(MCR_REG, cr);
}
uint32_t iosf_lpss_read(int reg)
{
uint32_t cr = IOSF_OPCODE(IOSF_OP_READ_LPSS) |
IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) |
IOSF_BYTE_EN;
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
write_iosf_reg(MCR_REG, cr);
return read_iosf_reg(MDR_REG);
}
void iosf_lpss_write(int reg, uint32_t val)
{
uint32_t cr = IOSF_OPCODE(IOSF_OP_WRITE_LPSS) |
IOSF_PORT(IOSF_PORT_LPSS) | IOSF_REG(reg) |
IOSF_BYTE_EN;
write_iosf_reg(MDR_REG, val);
write_iosf_reg(MCRX_REG, IOSF_REG_UPPER(reg));
write_iosf_reg(MCR_REG, cr);
}