cpu/intel/car/p4-netburst: Remove delay loops
While commented as 10 ms + 250 us, those delay loops actually accounted for a total of 840 ms. And they seem unnecessary as followup code has potentially infinite retries when polling for status changes. Tested on aopen/dxplplusu, dual-socket P4 Xeon HT model_f2x. Change-Id: Ib7d1d66ed29c62d97073872f0b7809d719ac2324 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36595 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
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			| @@ -177,12 +177,6 @@ cores_counted: | |||||||
|  |  | ||||||
| hyper_threading_cpu: | hyper_threading_cpu: | ||||||
|  |  | ||||||
| 	/* delay 10 ms */ |  | ||||||
| 	movl	$10000, %ecx |  | ||||||
| 1:	inb	$0x80, %al |  | ||||||
| 	dec	%ecx |  | ||||||
| 	jnz	1b |  | ||||||
|  |  | ||||||
| 	post_code(0x25) | 	post_code(0x25) | ||||||
|  |  | ||||||
| 	/* Send Start IPI to all excluding ourself. */ | 	/* Send Start IPI to all excluding ourself. */ | ||||||
| @@ -198,12 +192,6 @@ hyper_threading_cpu: | |||||||
| 	andl	$LAPIC_ICR_BUSY, %ecx | 	andl	$LAPIC_ICR_BUSY, %ecx | ||||||
| 	jnz	1b | 	jnz	1b | ||||||
|  |  | ||||||
| 	/* delay 250 us */ |  | ||||||
| 	movl	$250, %ecx |  | ||||||
| 1:	inb	$0x80, %al |  | ||||||
| 	dec	%ecx |  | ||||||
| 	jnz	1b |  | ||||||
|  |  | ||||||
| 	post_code(0x26) | 	post_code(0x26) | ||||||
|  |  | ||||||
| 	/* Wait for sibling CPU to start. */ | 	/* Wait for sibling CPU to start. */ | ||||||
|   | |||||||
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