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I ran into a couple of errors while building a mahogany_fam10 target;

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CONFIG_CAR_FAM10 was renamed some time ago to
CONFIG_NORTHBRIDGE_AMD_AMDFAM10, and l3Cache() is actually defined as
l3_cache().

Signed-off-by: Ed Swierk <eswierk@aristanetworks.com>
Acked-by: Marc Jones <marcj303@gmail.com>


git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5262 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ed Swierk
2010-03-19 21:57:40 +00:00
committed by Ed Swierk
parent 8a0c6498a4
commit bd0381a705
1 changed files with 8 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files

16
src/southbridge/amd/rs780/rs780_early_setup.c
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@@ -101,7 +101,7 @@ static void set_nbcfg_enable_bits(device_t nb_dev, u32 reg_pos, u32 mask,
} }
} }
/* family 10 only, for reg > 0xFF */ /* family 10 only, for reg > 0xFF */
#if CONFIG_CAR_FAM10 == 1 #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1
static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask, static void set_fam10_ext_cfg_enable_bits(device_t fam10_dev, u32 reg_pos, u32 mask,
u32 val) u32 val)
{ {
@@ -270,7 +270,7 @@ static void rs780_htinit()
} else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) { } else if ((cpu_ht_freq > 0x6) && (cpu_ht_freq < 0xf)) {
printk_info("rs780_htinit: HT3 mode\n"); printk_info("rs780_htinit: HT3 mode\n");
#if CONFIG_CAR_FAM10 == 1 /* save some spaces */ #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
/* HT3 mode, RPR 8.4.3 */ /* HT3 mode, RPR 8.4.3 */
set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0); set_nbcfg_enable_bits(rs780_f0, 0x9c, 0x3 << 16, 0);
@@ -306,11 +306,11 @@ static void rs780_htinit()
/* Sets Training 0 Time. See T0Time table for encodings */ /* Sets Training 0 Time. See T0Time table for encodings */
set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20); set_fam10_ext_cfg_enable_bits(cpu_f0, 0x16C, 0x3F, 0x20);
/* TODO: */ /* TODO: */
#endif /* #if CONFIG_CAR_FAM10 == 1 */ #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
} }
} }
#if CONFIG_CAR_FAM10 != 1 /* save some spaces */ #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 /* save some spaces */
/******************************************************* /*******************************************************
* Optimize k8 with UMA. * Optimize k8 with UMA.
* See BKDG_NPT_0F guide for details. * See BKDG_NPT_0F guide for details.
@@ -364,9 +364,9 @@ static void k8_optimization()
} }
#else #else
#define k8_optimization() do{}while(0) #define k8_optimization() do{}while(0)
#endif /* #if CONFIG_CAR_FAM10 != 1 */ #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 != 1 */
#if CONFIG_CAR_FAM10 == 1 /* save some spaces */ #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 /* save some spaces */
void fam10_optimization() void fam10_optimization()
{ {
device_t cpu_f0, cpu_f2, cpu_f3; device_t cpu_f0, cpu_f2, cpu_f3;
@@ -422,7 +422,7 @@ void fam10_optimization()
/* L3 Disabled: L3 Enabled: */ /* L3 Disabled: L3 Enabled: */
/* cores: 2 3 4 2 3 4 */ /* cores: 2 3 4 2 3 4 */
/* bit8:4 28 26 24 24 20 16 */ /* bit8:4 28 26 24 24 20 16 */
if (!l3Cache()) { if (!l3_cache()) {
Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (24 + 2*(4-cpu_core_number())) << 4 | 2); Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (24 + 2*(4-cpu_core_number())) << 4 | 2);
} else { } else {
Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (16 + 4*(4-cpu_core_number())) << 4 | 4); Set_NB32(cpu_f3, 0x1A0, 4 << 12 | (16 + 4*(4-cpu_core_number())) << 4 | 4);
@@ -430,7 +430,7 @@ void fam10_optimization()
} }
#else #else
#define fam10_optimization() do{}while(0) #define fam10_optimization() do{}while(0)
#endif /* #if CONFIG_CAR_FAM10 == 1 */ #endif /* #if CONFIG_NORTHBRIDGE_AMD_AMDFAM10 == 1 */
/***************************************** /*****************************************
* rs780_por_pcicfg_init() * rs780_por_pcicfg_init()