cpu/amd: Correct number of MCA banks cleared
Use the value discovered in the MCG_CAP[Count] for the number of MCA status registers to clear. The generations should have the following number of banks: * Family 10h: 6 banks * Family 12h: 6 * Family 14h: 6 * Family 15h: 7 * Family 16h: 6 Change-Id: I0fc6d127a200b10fd484e051d84353cc61b27a41 Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com> Reviewed-on: https://review.coreboot.org/27923 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Martin Roth <martinroth@google.com>
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committed by
Martin Roth
parent
e13dd172b1
commit
bd4a3f8cd9
@@ -27,6 +27,8 @@
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#include <cpu/amd/multicore.h>
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#include <cpu/amd/amdfam12.h>
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#define MCG_CAP 0x179
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# define MCA_BANKS_MASK 0xff
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#define MC0_STATUS 0x401
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static void model_12_init(struct device *dev)
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@@ -35,6 +37,7 @@ static void model_12_init(struct device *dev)
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u8 i;
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msr_t msr;
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int num_banks;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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@@ -52,9 +55,11 @@ static void model_12_init(struct device *dev)
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disable_cache();
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/* zero the machine check error status registers */
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msr = rdmsr(MCG_CAP);
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num_banks = msr.lo & MCA_BANKS_MASK;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < 5; i++)
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for (i = 0; i < num_banks; i++)
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wrmsr(MC0_STATUS + (i * 4), msr);
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enable_cache();
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@@ -28,12 +28,15 @@
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#include <arch/acpi.h>
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#include <northbridge/amd/agesa/agesa_helper.h>
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#define MCG_CAP 0x179
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# define MCA_BANKS_MASK 0xff
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#define MC0_STATUS 0x401
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static void model_14_init(struct device *dev)
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{
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u8 i;
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msr_t msr;
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int num_banks;
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int msrno;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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@@ -75,9 +78,11 @@ static void model_14_init(struct device *dev)
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x86_enable_cache();
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/* zero the machine check error status registers */
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msr = rdmsr(MCG_CAP);
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num_banks = msr.lo & MCA_BANKS_MASK;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < 6; i++)
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for (i = 0; i < num_banks; i++)
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wrmsr(MC0_STATUS + (i * 4), msr);
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/* Enable the local CPU APICs */
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@@ -35,6 +35,7 @@ static void model_15_init(struct device *dev)
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u8 i;
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msr_t msr;
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int num_banks;
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int msrno;
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unsigned int cpu_idx;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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@@ -72,9 +73,11 @@ static void model_15_init(struct device *dev)
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x86_enable_cache();
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/* zero the machine check error status registers */
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msr = rdmsr(MCG_CAP);
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num_banks = msr.lo & MCA_BANKS_MASK;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < 6; i++)
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for (i = 0; i < num_banks; i++)
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wrmsr(MC0_STATUS + (i * 4), msr);
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/* Enable the local CPU APICs */
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@@ -34,6 +34,7 @@ static void model_16_init(struct device *dev)
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u8 i;
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msr_t msr;
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int num_banks;
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int msrno;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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@@ -70,9 +71,11 @@ static void model_16_init(struct device *dev)
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x86_enable_cache();
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/* zero the machine check error status registers */
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msr = rdmsr(MCG_CAP);
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num_banks = msr.lo & MCA_BANKS_MASK;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < 6; i++)
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for (i = 0; i < num_banks; i++)
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wrmsr(MC0_STATUS + (i * 4), msr);
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/* Enable the local CPU APICs */
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@@ -62,6 +62,7 @@ static void model_10xxx_init(struct device *dev)
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{
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u8 i;
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msr_t msr;
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int num_banks;
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struct node_core_id id;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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@@ -109,9 +110,11 @@ static void model_10xxx_init(struct device *dev)
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disable_cache();
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/* zero the machine check error status registers */
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msr = rdmsr(MCG_CAP);
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num_banks = msr.lo & MCA_BANKS_MASK;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < 5; i++)
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for (i = 0; i < num_banks; i++)
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wrmsr(MC0_STATUS + (i * 4), msr);
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enable_cache();
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@@ -35,6 +35,7 @@ static void model_15_init(struct device *dev)
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u8 i;
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msr_t msr;
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int num_banks;
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int msrno;
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unsigned int cpu_idx;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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@@ -69,9 +70,11 @@ static void model_15_init(struct device *dev)
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x86_enable_cache();
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/* zero the machine check error status registers */
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msr = rdmsr(MCG_CAP);
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num_banks = msr.lo & MCA_BANKS_MASK;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < 6; i++)
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for (i = 0; i < num_banks; i++)
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wrmsr(MC0_STATUS + (i * 4), msr);
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/* Enable the local CPU APICs */
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@@ -51,6 +51,7 @@ static void model_15_init(struct device *dev)
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u8 i;
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msr_t msr;
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int num_banks;
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int msrno;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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@@ -81,9 +82,11 @@ static void model_15_init(struct device *dev)
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x86_enable_cache();
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/* zero the machine check error status registers */
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msr = rdmsr(MCG_CAP);
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num_banks = msr.lo & MCA_BANKS_MASK;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < 6; i++)
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for (i = 0; i < num_banks; i++)
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wrmsr(MC0_STATUS + (i * 4), msr);
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/* Enable the local CPU APICs */
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@@ -34,6 +34,7 @@ static void model_16_init(struct device *dev)
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u8 i;
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msr_t msr;
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int num_banks;
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int msrno;
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#if IS_ENABLED(CONFIG_LOGICAL_CPUS)
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u32 siblings;
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@@ -66,9 +67,11 @@ static void model_16_init(struct device *dev)
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x86_enable_cache();
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/* zero the machine check error status registers */
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msr = rdmsr(MCG_CAP);
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num_banks = msr.lo & MCA_BANKS_MASK;
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msr.lo = 0;
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msr.hi = 0;
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for (i = 0; i < 6; i++)
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for (i = 0; i < num_banks; i++)
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wrmsr(MC0_STATUS + (i * 4), msr);
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/* Enable the local CPU APICs */
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