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mb/google/brya/variants/orisa: Change board strap memory config

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Reorder GPIO pin mapping as per platform documentation:
* GPIO_MEM_CONFIG_0 -> GPP_E2
* GPIO_MEM_CONFIG_1 -> GPP_E1
* GPIO_MEM_CONFIG_2 -> GPP_E12
* GPIO_MEM_CONFIG_3 -> NC

BUG=None
TEST=emerge-nissa coreboot

Change-Id: I4e979686833095a904b114500dc1142def583afa
Signed-off-by: Rishika Raj <rishikaraj@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83549
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Amanda Hwang <amanda_hwang@compal.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
This commit is contained in:
Rishika Raj 2024-07-18 17:59:19 +00:00 committed by Subrata Banik
parent 49bde8ce26
commit bd51c60322
1 changed files with 5 additions and 4 deletions
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9
src/mainboard/google/brya/variants/orisa/memory.c
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@ -78,14 +78,15 @@ int variant_memory_sku(void)
{
/*
* Memory configuration board straps
* GPIO_MEM_CONFIG_0 GPP_E1
* GPIO_MEM_CONFIG_1 GPP_E2
* GPIO_MEM_CONFIG_0 GPP_E2
* GPIO_MEM_CONFIG_1 GPP_E1
* GPIO_MEM_CONFIG_2 GPP_E12
* GPIO_MEM_CONFIG_3 NC
*/
gpio_t spd_gpios[] = {
GPP_E1,
GPP_E2,
GPP_E12,
GPP_E1,
GPP_E12
};
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));