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exynos5420: correct the PMS value for CPLL

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This patch matches the User Manual Table 7-2 about the PMS value for
CPLL. This doesn't change the PLL frequency (before and after both make
666MHz) but this is the suggested PMSK values for obtaining 666.
(Suggested as per user manual).

This is ported from https://gerrit.chromium.org/gerrit/#/c/62438/

Signed-off-by: David Hendricks <dhendrix@chromium.org>

Change-Id: Ia33e1971ab88da761000d443792560476514626b
Reviewed-on: https://gerrit.chromium.org/gerrit/65281
Reviewed-by: Gabe Black <gabeblack@chromium.org>
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-on: http://review.coreboot.org/4460
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>
This commit is contained in:
David Hendricks 2013-08-08 16:04:07 -07:00 committed by Patrick Georgi
parent 136e709015
commit bd56bf0dcf
1 changed files with 1 additions and 1 deletions
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2
src/cpu/samsung/exynos5420/clock_init.c
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@ -113,7 +113,7 @@ void system_clock_init(void)
/* Set CPLL */
writel(CPLL_CON1_VAL, &clk->cpll_con1);
val = set_pll(0x6f, 0x2, 0x1);
val = set_pll(0xde, 0x4, 0x1);
writel(val, &clk->cpll_con0);
while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
;