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soc/intel/tigerlake: Configure TCSS D3Hot and D3Cold

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Update configuration for both of TCSS D3Hot and D3Cold. It is expected
D3Hot is enabled for all platforms. Because there are known limitations
for D3Cold enabling on pre-QS platform, this change reads cpu id and
disables D3Cold for pre-QS platform. For QS platform, D3Cold is
configured to be enabled.

BUG=None
TEST=Verified D3Hot is enabled, D3Cold is disabled for pre-QS (cpu:806c0)
and enabled for QS (cpu:0x806c1).

Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I534ddfefcd182f5b35aa5e8b461f0920d375a66d
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43980
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Reviewed-by: Divya S Sasidharan <divya.s.sasidharan@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
John Zhao
2020-07-27 13:22:11 -07:00
committed by Nick Vaccaro
parent 048d9b5cba
commit bd615d6f93
2 changed files with 10 additions and 4 deletions
Download Patch File Download Diff File Expand all files Collapse all files

10
src/soc/intel/tigerlake/fsp_params.c
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@@ -9,6 +9,7 @@
#include <fsp/util.h>
#include <intelblocks/cse.h>
#include <intelblocks/lpss.h>
#include <intelblocks/mp_init.h>
#include <intelblocks/xdci.h>
#include <intelpch/lockdown.h>
#include <security/vboot/vboot_common.h>
@@ -85,6 +86,7 @@ static const pci_devfn_t serial_io_dev[] = {
void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
{
int i;
uint32_t cpu_id;
FSP_S_CONFIG *params = &supd->FspsConfig;
struct device *dev;
@@ -110,8 +112,12 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
}
/* D3Hot and D3Cold for TCSS */
params->D3HotEnable = config->TcssD3HotEnable;
params->D3ColdEnable = config->TcssD3ColdEnable;
params->D3HotEnable = !config->TcssD3HotDisable;
cpu_id = cpu_get_cpuid();
if (cpu_id == CPUID_TIGERLAKE_A0)
params->D3ColdEnable = 0;
else
params->D3ColdEnable = !config->TcssD3ColdDisable;
params->TcssAuxOri = config->TcssAuxOri;
for (i = 0; i < 8; i++)