From 5b47d77047fbe42c8ab5ce63fbb26aee4899a8e5 Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Fri, 13 Nov 2020 17:21:25 +0800 Subject: [PATCH 001/107] intel/fsp2_0: Add soc_validate_fsp_version for FSP version check Only need to check this once so check it at romstage where the console is usually ready. Also define union fsp_revision to avoid code duplication. Change-Id: I628014e05bd567462f50af2633fbf48f3dc412bc Signed-off-by: Johnny Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/47559 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones Reviewed-by: Jonathan Zhang --- src/drivers/intel/fsp2_0/header_display.c | 10 +--------- src/drivers/intel/fsp2_0/include/fsp/util.h | 11 +++++++++++ src/drivers/intel/fsp2_0/util.c | 18 +++++++++--------- 3 files changed, 21 insertions(+), 18 deletions(-) diff --git a/src/drivers/intel/fsp2_0/header_display.c b/src/drivers/intel/fsp2_0/header_display.c index 57e13b5354..b45b4d8a7c 100644 --- a/src/drivers/intel/fsp2_0/header_display.c +++ b/src/drivers/intel/fsp2_0/header_display.c @@ -5,15 +5,7 @@ void fsp_print_header_info(const struct fsp_header *hdr) { - union { - uint32_t val; - struct { - uint8_t bld_num; - uint8_t revision; - uint8_t minor; - uint8_t major; - } rev; - } revision; + union fsp_revision revision; revision.val = hdr->fsp_revision; diff --git a/src/drivers/intel/fsp2_0/include/fsp/util.h b/src/drivers/intel/fsp2_0/include/fsp/util.h index a57b1bb942..315db056e9 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/util.h +++ b/src/drivers/intel/fsp2_0/include/fsp/util.h @@ -42,6 +42,16 @@ struct hob_resource { uint64_t length; } __packed; +union fsp_revision { + uint32_t val; + struct { + uint8_t bld_num; + uint8_t revision; + uint8_t minor; + uint8_t major; + } rev; +}; + #if CONFIG_UDK_VERSION < CONFIG_UDK_2017_VERSION enum resource_type { EFI_RESOURCE_SYSTEM_MEMORY = 0, @@ -90,6 +100,7 @@ void fsp_find_bootloader_tolum(struct range_entry *re); void fsp_get_version(char *buf); void lb_string_platform_blob_version(struct lb_header *header); void report_fspt_output(void); +void soc_validate_fsp_version(const struct fsp_header *hdr); /* Fill in header and validate sanity of component within region device. */ enum cb_err fsp_validate_component(struct fsp_header *hdr, diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index acc3f4b9b3..490816d343 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -85,6 +85,9 @@ enum cb_err fsp_validate_component(struct fsp_header *hdr, return CB_ERR; } + if (ENV_ROMSTAGE) + soc_validate_fsp_version(hdr); + return CB_SUCCESS; } @@ -213,15 +216,7 @@ enum cb_err fsp_load_component(struct fsp_load_descriptor *fspld, struct fsp_hea void fsp_get_version(char *buf) { struct fsp_header *hdr = &fsps_hdr; - union { - uint32_t val; - struct { - uint8_t bld_num; - uint8_t revision; - uint8_t minor; - uint8_t major; - } rev; - } revision; + union fsp_revision revision; revision.val = hdr->fsp_revision; snprintf(buf, FSP_VER_LEN, "%u.%u-%u.%u.%u.%u", (hdr->spec_version >> 4), @@ -243,3 +238,8 @@ void lb_string_platform_blob_version(struct lb_header *header) rec->size = ALIGN_UP(sizeof(*rec) + len + 1, 8); memcpy(rec->string, fsp_version, len+1); } + +__weak void soc_validate_fsp_version(const struct fsp_header *hdr) +{ + printk(BIOS_DEBUG, "%s not implemented.\n", __func__); +} From cdd7d18120a1a76df4a9f8d78391c7018013d916 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Wed, 18 Nov 2020 09:20:01 -0700 Subject: [PATCH 002/107] mb/google/zork: Remove 50ms WIFI delay As a part of trying to get our boot time as low as possible, any delays in the code should try to be refactored out. This removes the 50ms delay in the WIFI sequence by enabling power and putting the wifi module into reset in bootblock, then bringing it out of reset in ramstage. This is significantly longer than the 50ms requirement. The reset GPIO was already being set high in ramstage, so that code didn't need to be added. BUG=b:171513520 TEST=Boot on boards with different module types, WIFI works on both. BRANCH=Zork Signed-off-by: Martin Roth Change-Id: I211d3da338ad368d1f011f03cf7d05121c057075 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47719 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- .../zork/variants/baseboard/gpio_baseboard_trembyle.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c index 14b85b0da9..818c39bf59 100644 --- a/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c +++ b/src/mainboard/google/zork/variants/baseboard/gpio_baseboard_trembyle.c @@ -199,8 +199,8 @@ static void wifi_power_reset_configure_active_low_power(void) * Configure WiFi GPIOs such that: * - WIFI_AUX_RESET_L is configured first to assert PERST# to WiFi device. * - Enable power to WiFi using EN_PWR_WIFI_L. - * - Wait for 50ms after power to WiFi is enabled. - * - Deassert WIFI_AUX_RESET_L. + * - Wait for >50ms after power to WiFi is enabled. (Time between bootblock & ramstage) + * - WIFI_AUX_RESET_L gets deasserted later in mainboard_configure_gpios in ramstage */ static const struct soc_amd_gpio v3_wifi_table[] = { /* WIFI_AUX_RESET_L */ @@ -210,8 +210,6 @@ static void wifi_power_reset_configure_active_low_power(void) }; program_gpios(v3_wifi_table, ARRAY_SIZE(v3_wifi_table)); - mdelay(50); - gpio_set(GPIO_86, 1); } static void wifi_power_reset_configure_active_high_power(void) From 96a06dd46443754ab2aa07fd3ecacf03d34265e1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 14 Nov 2020 00:33:18 +0100 Subject: [PATCH 003/107] nb/intel/sandybridge: Rename loop variable The `discover_edges_real` function actually tests a range of values for DQS PI and evaluates how the system responds. Rename the loop variable. Change-Id: I67390ba315d618d153f91c0e8a81db04ec8f63e1 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47606 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_common.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b67eb564ca..893d6b27de 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2310,14 +2310,14 @@ int command_training(ramctr_timing *ctrl) static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { - int edge; + int dqs_pi; int stats[NUM_LANES][MAX_EDGE_TIMING + 1]; int lane; - for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { + for (dqs_pi = 0; dqs_pi <= MAX_EDGE_TIMING; dqs_pi++) { FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].rising = edge; - ctrl->timings[channel][slotrank].lanes[lane].falling = edge; + ctrl->timings[channel][slotrank].lanes[lane].rising = dqs_pi; + ctrl->timings[channel][slotrank].lanes[lane].falling = dqs_pi; } program_timings(ctrl, channel); @@ -2337,7 +2337,7 @@ static int find_read_mpr_margin(ramctr_timing *ctrl, int channel, int slotrank, wait_for_iosav(channel); FOR_ALL_LANES { - stats[lane][edge] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); + stats[lane][dqs_pi] = MCHBAR32(IOSAV_By_ERROR_COUNT_ch(channel, lane)); } } From e59f70a4d912c64c4b6fdd30c08fcea868da98bc Mon Sep 17 00:00:00 2001 From: John Su Date: Wed, 18 Nov 2020 13:47:43 +0800 Subject: [PATCH 004/107] mb/google/dedede/variants/madoo: Increase TCC offset from 5 to 10 Increase TCC offset value from 5 to 10 for Thermal Control Circuit (TCC) activation. BUG=b:171531244 TEST=build and verify by thermal team Signed-off-by: John Su Change-Id: Ic2822b059f166779e1f0bcf92e753dad1078783c Reviewed-on: https://review.coreboot.org/c/coreboot/+/47691 Reviewed-by: EricR Lai Reviewed-by: Sumeet R Pawnikar Reviewed-by: Karthik Ramasubramanian Reviewed-by: Ben Kao Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/madoo/overridetree.cb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/dedede/variants/madoo/overridetree.cb b/src/mainboard/google/dedede/variants/madoo/overridetree.cb index 1be1012123..c7f39952c5 100644 --- a/src/mainboard/google/dedede/variants/madoo/overridetree.cb +++ b/src/mainboard/google/dedede/variants/madoo/overridetree.cb @@ -59,7 +59,7 @@ chip soc/intel/jasperlake .tdp_pl2_override = 20, }" - register "tcc_offset" = "5" # TCC of 95C + register "tcc_offset" = "10" # TCC of 95C device domain 0 on device pci 04.0 on From 07c85ad11c763a3179ca88e8c0e6d5ae4168c09f Mon Sep 17 00:00:00 2001 From: Felix Held Date: Tue, 17 Nov 2020 17:01:08 +0100 Subject: [PATCH 005/107] include/device/pci_ids: add PCI IDs for new AMD SoCs Change-Id: I0caea5627045b7855e2c5f3cb01d4fa21332788b Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47703 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/include/device/pci_ids.h | 28 ++++++++++++++++++++++++++++ 1 file changed, 28 insertions(+) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index 5095f1168a..ebf02a8fd1 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -301,11 +301,13 @@ #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT 0x1536 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_HT 0x1566 #define PCI_DEVICE_ID_AMD_17H_MODEL_101F_NB 0x15d0 +#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB 0x1630 #define PCI_DEVICE_ID_AMD_15H_MODEL_101F_NB_IOMMU 0x1419 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU 0x1423 #define PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_IOMMU 0x1577 #define PCI_DEVICE_ID_AMD_16H_MODEL_303F_NB_IOMMU 0x1567 #define PCI_DEVICE_ID_AMD_17H_MODEL_1020_NB_IOMMU 0x15D1 +#define PCI_DEVICE_ID_AMD_17H_MODEL_606F_NB_IOMMU 0x1631 #define PCI_DEVICE_ID_ATI_SB600_LPC 0x438D #define PCI_DEVICE_ID_ATI_SB600_SATA 0x4380 @@ -454,13 +456,17 @@ #define PCI_DEVICE_ID_AMD_CZ_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP 0x15D3 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D1 0x1633 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_D2 0x1634 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSA 0x15DB #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_PCIE_GPP_BUSB 0x15DC +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_PCIE_GPP_BUSABC 0x1635 #define PCI_DEVICE_ID_AMD_FAM17H_ACP 0x15E2 #define PCI_DEVICE_ID_AMD_FAM17H_HDA1 0x15E3 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI0 0x15E0 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_XHCI1 0x15E1 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL20H_XHCI0 0x15E5 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_XHCI 0x1639 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF0 0x15E8 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF1 0x15E9 #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF2 0x15EA @@ -468,6 +474,22 @@ #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF4 0x15EC #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF5 0x15ED #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_DF6 0x15EE +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF0 0x1448 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF1 0x1449 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF2 0x144A +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF3 0x144B +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF4 0x144C +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF5 0x144D +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF6 0x144E +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_DF7 0x144F +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF0 0x166A +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF1 0x166B +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF2 0x166C +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF3 0x166D +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF4 0x166E +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF5 0x166F +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF6 0x1670 +#define PCI_DEVICE_ID_AMD_FAM19H_MODEL51H_DF7 0x1671 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER0 0x7901 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_VER1 0x7904 #define PCI_DEVICE_ID_AMD_FAM17H_SATA_AHCI_RAID_VER0 0x7916 @@ -476,9 +498,15 @@ #define PCI_DEVICE_ID_AMD_FAM17H_SMBUS 0x790B #define PCI_DEVICE_ID_AMD_FAM17H_LPC 0x790E #define PCI_DEVICE_ID_AMD_FAM17H_MODEL18H_GBE 0x1458 +#define PCI_DEVICE_ID_AMD_FAM17H_MODEL60H_GBE 0x1641 +#define PCI_DEVICE_ID_AMD_FAM17H_I2S_AC97 0x1644 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_GPU 0x15D8 +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_GPU 0x1636 +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL68H_GPU 0x164C +#define PCI_DEVICE_ID_ATI_FAM19H_MODEL51H_GPU 0x1638 #define PCI_DEVICE_ID_ATI_FAM17H_MODEL18H_HDA0 0x15DE +#define PCI_DEVICE_ID_ATI_FAM17H_MODEL60H_HDA0 0x1637 #define PCI_VENDOR_ID_VLSI 0x1004 #define PCI_DEVICE_ID_VLSI_82C592 0x0005 From 9d8686610952b636f3888138136d7587d8c4de0f Mon Sep 17 00:00:00 2001 From: Kane Chen Date: Thu, 19 Nov 2020 19:48:35 +0800 Subject: [PATCH 006/107] mb/google/zork: update telemetry settings for Woomax Update Woomax to improve the performance. BUG=b:168073070 BRANCH=zork TEST=emerge-zork coreboot Signed-off-by: Kane Chen Change-Id: I2703d15f1fbe715ab1c684274d9e4e0bb55ef23b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47743 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/zork/variants/woomax/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/zork/variants/woomax/overridetree.cb b/src/mainboard/google/zork/variants/woomax/overridetree.cb index abbdd927c8..5a2bc9922c 100644 --- a/src/mainboard/google/zork/variants/woomax/overridetree.cb +++ b/src/mainboard/google/zork/variants/woomax/overridetree.cb @@ -16,9 +16,9 @@ chip soc/amd/picasso register "stapm_time_constant_s" = "200" register "sustained_power_limit_mW" = "15000" - register "telemetry_vddcr_vdd_slope_mA" = "102586" + register "telemetry_vddcr_vdd_slope_mA" = "101070" register "telemetry_vddcr_vdd_offset" = "0" - register "telemetry_vddcr_soc_slope_mA" = "26967" + register "telemetry_vddcr_soc_slope_mA" = "24560" register "telemetry_vddcr_soc_offset" = "0" # End : OPN Performance Configuration From 324b1ee09e966daf847ff52aa3cab18b7bc95abe Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Wed, 18 Nov 2020 19:24:53 +0800 Subject: [PATCH 007/107] util: Add new DDR4 H5ANAG6NCJR-XNC for zork boards Add DDR4 part H5ANAG6NDMR-XNC. Attributes are derived from data sheets. BUG=None TEST=Compared generated SPD with data sheets and checked in SPD Change-Id: I324aefbce1b138a2f71aad3173d6a138cf7fa510 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/47698 Tested-by: build bot (Jenkins) Reviewed-by: Rob Barnes --- src/mainboard/google/zork/spd/ddr4-spd-9.hex | 32 +++++++++++++++++++ .../zork/spd/ddr4_spd_manifest.generated.txt | 1 + 2 files changed, 33 insertions(+) create mode 100644 src/mainboard/google/zork/spd/ddr4-spd-9.hex diff --git a/src/mainboard/google/zork/spd/ddr4-spd-9.hex b/src/mainboard/google/zork/spd/ddr4-spd-9.hex new file mode 100644 index 0000000000..1ce7c21d4c --- /dev/null +++ b/src/mainboard/google/zork/spd/ddr4-spd-9.hex @@ -0,0 +1,32 @@ +23 11 0C 03 46 29 00 08 00 00 00 00 02 03 00 00 +00 00 05 06 F8 FF 02 00 6E 6E 6E 11 00 6E 30 11 +F0 0A 20 08 00 F0 2B 34 28 00 78 00 14 3C 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 9C B5 00 00 00 00 BC 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 20 20 20 20 20 20 20 +20 20 20 20 20 20 20 20 20 20 20 20 20 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 +00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 diff --git a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt index 202f1734d4..21565c66b6 100644 --- a/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt +++ b/src/mainboard/google/zork/spd/ddr4_spd_manifest.generated.txt @@ -13,3 +13,4 @@ K4AAG165WA-BCWE,ddr4-spd-7.hex H5AN8G6NCJR-XNC,ddr4-spd-1.hex K4AAG165WA-BCTD,ddr4-spd-8.hex H5ANAG6NDMR-XNC,ddr4-spd-2.hex +H5ANAG6NCJR-XNC,ddr4-spd-9.hex From d5ffc75fa0d7a9b72b6a0b8e142c168cde839f34 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Wed, 18 Nov 2020 19:32:42 +0800 Subject: [PATCH 008/107] mb/google/zork: update DRAM table for dirinboz Add Hynix DDR4 DRAM, index was generated by gen_part_id H5ANAG6NCJR-XNC BUG=b:173480390 BRANCH=zork TEST=emerge-zork coreboot Change-Id: Ib6f26a7b8d014493f4a256b328bee7ad3bf3c2b9 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/47700 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth Reviewed-by: Rob Barnes --- src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc | 2 +- .../google/zork/variants/dirinboz/spd/dram_id.generated.txt | 1 + .../google/zork/variants/dirinboz/spd/mem_parts_used.txt | 1 + 3 files changed, 3 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc index 5e0983695e..6d8a906c98 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc +++ b/src/mainboard/google/zork/variants/dirinboz/spd/Makefile.inc @@ -2,7 +2,7 @@ ## This is an auto-generated file. Do not edit!! SPD_SOURCES = -SPD_SOURCES += ddr4-spd-empty.hex # ID = 0(0b0000) +SPD_SOURCES += ddr4-spd-9.hex # ID = 0(0b0000) Parts = H5ANAG6NCJR-XNC SPD_SOURCES += ddr4-spd-empty.hex # ID = 1(0b0001) SPD_SOURCES += ddr4-spd-3.hex # ID = 2(0b0010) Parts = K4A8G165WC-BCTD SPD_SOURCES += ddr4-spd-empty.hex # ID = 3(0b0011) diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt index 8c8ee39dff..d6d5d09194 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt +++ b/src/mainboard/google/zork/variants/dirinboz/spd/dram_id.generated.txt @@ -7,3 +7,4 @@ MT40A512M16TB-062E:J 7 (0111) MT40A1G16KD-062E:E 8 (1000) K4AAG165WA-BCTD 9 (1001) K4AAG165WA-BCWE 10 (1010) +H5ANAG6NCJR-XNC 0 (0000) diff --git a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt index ba70da3ed3..5a6541f8a4 100644 --- a/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt +++ b/src/mainboard/google/zork/variants/dirinboz/spd/mem_parts_used.txt @@ -15,3 +15,4 @@ MT40A512M16TB-062E:J, 7 MT40A1G16KD-062E:E, 8 K4AAG165WA-BCTD, 9 K4AAG165WA-BCWE, 10 +H5ANAG6NCJR-XNC From f73580f6242925487e9a39545ad84da7ec907453 Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Wed, 18 Nov 2020 23:24:13 +0800 Subject: [PATCH 009/107] zork: Create gumboz variant Create the gumboz variant of the dalboz reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.2.0). BUG=b:173536689 BRANCH=zork TEST=util/abuild/abuild -p none -t google/zork -x -a make sure the build includes GOOGLE_GUMBOZ Change-Id: I48db7eba7864c18e7307b45fe9f84073bfca0155 Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/47717 Tested-by: build bot (Jenkins) Reviewed-by: Rob Barnes --- src/mainboard/google/zork/Kconfig | 2 + src/mainboard/google/zork/Kconfig.name | 4 ++ .../google/zork/variants/gumboz/Makefile.inc | 3 ++ .../gumboz/include/variant/acpi/audio.asl | 3 ++ .../gumboz/include/variant/acpi/mainboard.asl | 3 ++ .../gumboz/include/variant/acpi/thermal.asl | 3 ++ .../zork/variants/gumboz/include/variant/ec.h | 3 ++ .../variants/gumboz/include/variant/gpio.h | 3 ++ .../variants/gumboz/include/variant/thermal.h | 3 ++ .../zork/variants/gumboz/overridetree.cb | 42 +++++++++++++++++++ .../zork/variants/gumboz/spd/Makefile.inc | 5 +++ .../variants/gumboz/spd/dram_id.generated.txt | 1 + .../variants/gumboz/spd/mem_parts_used.txt | 9 ++++ 13 files changed, 84 insertions(+) create mode 100644 src/mainboard/google/zork/variants/gumboz/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl create mode 100644 src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl create mode 100644 src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl create mode 100644 src/mainboard/google/zork/variants/gumboz/include/variant/ec.h create mode 100644 src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h create mode 100644 src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h create mode 100644 src/mainboard/google/zork/variants/gumboz/overridetree.cb create mode 100644 src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc create mode 100644 src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt create mode 100644 src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt diff --git a/src/mainboard/google/zork/Kconfig b/src/mainboard/google/zork/Kconfig index a0606cc59a..36824e651d 100644 --- a/src/mainboard/google/zork/Kconfig +++ b/src/mainboard/google/zork/Kconfig @@ -72,6 +72,7 @@ config VARIANT_DIR default "woomax" if BOARD_GOOGLE_WOOMAX default "dirinboz" if BOARD_GOOGLE_DIRINBOZ default "shuboz" if BOARD_GOOGLE_SHUBOZ + default "gumboz" if BOARD_GOOGLE_GUMBOZ config MAINBOARD_PART_NUMBER string @@ -84,6 +85,7 @@ config MAINBOARD_PART_NUMBER default "Woomax" if BOARD_GOOGLE_WOOMAX default "Dirinboz" if BOARD_GOOGLE_DIRINBOZ default "Shuboz" if BOARD_GOOGLE_SHUBOZ + default "Gumboz" if BOARD_GOOGLE_GUMBOZ config DEVICETREE string diff --git a/src/mainboard/google/zork/Kconfig.name b/src/mainboard/google/zork/Kconfig.name index 8ed43f0a8b..6c6657cecd 100644 --- a/src/mainboard/google/zork/Kconfig.name +++ b/src/mainboard/google/zork/Kconfig.name @@ -35,3 +35,7 @@ config BOARD_GOOGLE_DIRINBOZ config BOARD_GOOGLE_SHUBOZ bool "-> Shuboz" select BOARD_GOOGLE_BASEBOARD_DALBOZ + +config BOARD_GOOGLE_GUMBOZ + bool "-> Gumboz" + select BOARD_GOOGLE_BASEBOARD_DALBOZ diff --git a/src/mainboard/google/zork/variants/gumboz/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/Makefile.inc new file mode 100644 index 0000000000..295acd25c9 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/Makefile.inc @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +subdirs-y += ./spd diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl new file mode 100644 index 0000000000..900e36f277 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/audio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl new file mode 100644 index 0000000000..a1161edb5f --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/mainboard.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl new file mode 100644 index 0000000000..7a793d8102 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/acpi/thermal.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/ec.h b/src/mainboard/google/zork/variants/gumboz/include/variant/ec.h new file mode 100644 index 0000000000..9e61a440cf --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/ec.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h b/src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h new file mode 100644 index 0000000000..dfaeec3ae1 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/gpio.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h b/src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h new file mode 100644 index 0000000000..2af647973d --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/include/variant/thermal.h @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/google/zork/variants/gumboz/overridetree.cb b/src/mainboard/google/zork/variants/gumboz/overridetree.cb new file mode 100644 index 0000000000..1cc2364f5e --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/overridetree.cb @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-or-later + +chip soc/amd/picasso + + # Start : OPN Performance Configuration + # See devhub #56670 Chapter 5 for documentation + # For the below fields, 0 indicates use SOC default + + # System config index + register "system_config" = "1" + + # Set STAPM confiuration. All of these fields must be set >0 to take affect + register "slow_ppt_limit_mW" = "6000" + register "fast_ppt_limit_mW" = "9000" + register "slow_ppt_time_constant_s" = "5" + register "stapm_time_constant_s" = "2500" + register "sustained_power_limit_mW" = "4800" + + # End : OPN Performance Configuration + + # I2C2 for touchscreen and trackpad + + register "i2c[2]" = "{ + .speed = I2C_SPEED_FAST, + }" + + # I2C3 for H1 + + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .early_init = true, + }" + + # See AMD 55570-B1 Table 13: PCI Device ID Assignments. + device domain 0 on + subsystemid 0x1022 0x1510 inherit + end # domain + + device mmio 0xfedc4000 on # APU_I2C2_BASE + end # device + +end # chip soc/amd/picasso diff --git a/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc new file mode 100644 index 0000000000..3edeb9606c --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/spd/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = ddr4-spd-empty.hex diff --git a/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/spd/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt new file mode 100644 index 0000000000..106a705a36 --- /dev/null +++ b/src/mainboard/google/zork/variants/gumboz/spd/mem_parts_used.txt @@ -0,0 +1,9 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# One part per line with an optional fixed ID in column 2. +# Only include a fixed ID if it is required for legacy reasons! +# Each part must also be listed in util/spd_tools/ddr4/global_ddr4_mem_parts.json.txt. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/ddr4. +# See util/spd_tools/ddr4/README.md for more details and instructions. + +# Part Name, Fixed ID (optional) From d656d08f5e689e83a520999562f7deb48ef2871a Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Thu, 19 Nov 2020 17:53:53 -0800 Subject: [PATCH 010/107] Update vboot submodule to upstream master Updating from commit id 4c523ed1: vboot2: Add support for modexp acceleration to commit id 9d4053df: Revert "Reland: Clean up implicit fall through." This brings in 32 new commmits. Among the changes are restored support for older GCC/clang versions that do not support __attribute__((fallthrough)). Signed-off-by: Julius Werner Change-Id: I1110664bf71b4376bcdd9ba934a95031ba872c1d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47784 Tested-by: build bot (Jenkins) Reviewed-by: Joel Kitching Reviewed-by: Angel Pons --- 3rdparty/vboot | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/3rdparty/vboot b/3rdparty/vboot index 4c523ed10f..9d4053df76 160000 --- a/3rdparty/vboot +++ b/3rdparty/vboot @@ -1 +1 @@ -Subproject commit 4c523ed10f25de872ac0513ebd6ca53d3970b9de +Subproject commit 9d4053df76c127f625a8571d3ef16e6a063c8de5 From 8360946c8e2b0f57d7e12eeb1df72bf2b9410e63 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Fri, 13 Nov 2020 18:08:31 -0800 Subject: [PATCH 011/107] intel/socket_441: Increase bootblock size MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit One mainboard using this socket has less than 20 bytes of space left in its bootblock, hindering development. Double the bootblock size to solve the problem. Signed-off-by: Julius Werner Change-Id: I620c13eab53c3326a4f4660b63ed1dd0fc81f563 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47585 Reviewed-by: Angel Pons Reviewed-by: Kyösti Mälkki Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/cpu/intel/socket_441/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index af43f72e53..7a303af08c 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -12,7 +12,7 @@ config SOCKET_SPECIFIC_OPTIONS # dummy config C_ENV_BOOTBLOCK_SIZE hex - default 0x4000 + default 0x8000 config DCACHE_RAM_BASE hex From 7d11513ab3281ef3bee83b4b523219b683d3ddc1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 14 Nov 2020 01:44:44 +0100 Subject: [PATCH 012/107] nb/intel/sandybridge: Introduce `disable_refresh_machine` function The same IOSAV sequence is used in both loops, so there's no need to reprogram it again in the second loop. Tested on Asus P8H61-M PRO, still boots. Change-Id: If7ee7917b61e4b752b4fc4700715dc9506520c03 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47612 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../intel/sandybridge/raminit_common.c | 74 ++++++------------- 1 file changed, 23 insertions(+), 51 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 893d6b27de..885689c94f 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1933,21 +1933,33 @@ static void train_write_flyby(ramctr_timing *ctrl) MCHBAR32(GDCRTRAININGMOD) = 0; } -static void write_op(ramctr_timing *ctrl, int channel) +static void disable_refresh_machine(ramctr_timing *ctrl) { - int slotrank; + int channel; - wait_for_iosav(channel); + FOR_ALL_POPULATED_CHANNELS { + /* choose an existing rank */ + const int slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - /* choose an existing rank. */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; + iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); + /* Execute command queue */ + iosav_run_once(channel); - /* Execute command queue */ - iosav_run_once(channel); + wait_for_iosav(channel); - wait_for_iosav(channel); + MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); + } + + /* Refresh disable */ + MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); + + FOR_ALL_POPULATED_CHANNELS { + /* Execute the same command queue */ + iosav_run_once(channel); + + wait_for_iosav(channel); + } } /* @@ -1970,16 +1982,7 @@ int write_training(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); - FOR_ALL_POPULATED_CHANNELS { - write_op(ctrl, channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); - } - - /* Refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); - FOR_ALL_POPULATED_CHANNELS { - write_op(ctrl, channel); - } + disable_refresh_machine(ctrl); /* Enable write leveling on all ranks Disable all DQ outputs @@ -2142,38 +2145,7 @@ static void fill_pattern5(ramctr_timing *ctrl, int channel, int patno) static void reprogram_320c(ramctr_timing *ctrl) { - int channel, slotrank; - - FOR_ALL_POPULATED_CHANNELS { - wait_for_iosav(channel); - - /* Choose an existing rank */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - MCHBAR32_OR(SCHED_CBIT_ch(channel), 1 << 21); - } - - /* refresh disable */ - MCHBAR32_AND(MC_INIT_STATE_G, ~(1 << 3)); - FOR_ALL_POPULATED_CHANNELS { - wait_for_iosav(channel); - - /* choose an existing rank. */ - slotrank = !(ctrl->rankmap[channel] & 1) ? 2 : 0; - - iosav_write_zqcs_sequence(channel, slotrank, 4, 4, 31); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } + disable_refresh_machine(ctrl); /* JEDEC reset */ dram_jedecreset(ctrl); From 1e37c9ca465a14d55adeacb332354771543437b5 Mon Sep 17 00:00:00 2001 From: Julius Werner Date: Wed, 11 Dec 2019 17:09:39 -0800 Subject: [PATCH 013/107] cbfs: Add metadata cache This patch adds a new CBFS "mcache" (metadata cache) -- a memory buffer that stores the headers of all CBFS files. Similar to the existing FMAP cache, this cache should reduce the amount of SPI accesses we need to do every boot: rather than having to re-read all CBFS headers from SPI flash every time we're looking for a file, we can just walk the same list in this in-memory copy and finally use it to directly access the flash at the right position for the file data. This patch adds the code to support the cache but doesn't enable it on any platform. The next one will turn it on by default. Change-Id: I5b1084bfdad1c6ab0ee1b143ed8dd796827f4c65 Signed-off-by: Julius Werner Reviewed-on: https://review.coreboot.org/c/coreboot/+/38423 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin --- src/commonlib/Makefile.inc | 7 + src/commonlib/bsd/cbfs_mcache.c | 143 ++++++++++++++++++ .../bsd/include/commonlib/bsd/cb_err.h | 1 + .../bsd/include/commonlib/bsd/cbfs_private.h | 21 +++ src/commonlib/include/commonlib/cbmem_id.h | 6 +- src/include/cbfs.h | 23 ++- src/include/memlayout.h | 3 + src/include/symbols.h | 1 + src/lib/Kconfig | 21 +++ src/lib/cbfs.c | 112 ++++++++++++-- src/lib/coreboot_table.c | 11 +- src/security/vboot/vboot_common.h | 8 +- src/security/vboot/vboot_loader.c | 40 ++++- 13 files changed, 364 insertions(+), 33 deletions(-) create mode 100644 src/commonlib/bsd/cbfs_mcache.c diff --git a/src/commonlib/Makefile.inc b/src/commonlib/Makefile.inc index b2225cb114..1a38e4a89f 100644 --- a/src/commonlib/Makefile.inc +++ b/src/commonlib/Makefile.inc @@ -37,6 +37,13 @@ postcar-y += bsd/cbfs_private.c ramstage-y += bsd/cbfs_private.c smm-y += bsd/cbfs_private.c +bootblock-y += bsd/cbfs_mcache.c +verstage-y += bsd/cbfs_mcache.c +romstage-y += bsd/cbfs_mcache.c +postcar-y += bsd/cbfs_mcache.c +ramstage-y += bsd/cbfs_mcache.c +smm-y += bsd/cbfs_mcache.c + decompressor-y += bsd/lz4_wrapper.c bootblock-y += bsd/lz4_wrapper.c verstage-y += bsd/lz4_wrapper.c diff --git a/src/commonlib/bsd/cbfs_mcache.c b/src/commonlib/bsd/cbfs_mcache.c new file mode 100644 index 0000000000..f54b6631af --- /dev/null +++ b/src/commonlib/bsd/cbfs_mcache.c @@ -0,0 +1,143 @@ +/* SPDX-License-Identifier: BSD-3-Clause OR GPL-2.0-or-later */ + +#include +#include + +/* + * A CBFS metadata cache is an in memory data structure storing CBFS file headers (= metadata). + * It is defined by its start pointer and size. It contains a sequence of variable-length + * union mcache_entry entries. There is no overall header structure for the cache. + * + * Each mcache_entry is the raw metadata for a CBFS file (including attributes) in the same form + * as stored on flash (i.e. values in big-endian), except that the CBFS magic signature in the + * first 8 bytes ('LARCHIVE') is overwritten with mcache-internal bookkeeping data. The first 4 + * bytes are a magic number (MCACHE_MAGIC_FILE) and the next 4 bytes are the absolute offset in + * bytes on the cbfs_dev_t that this metadata blob was found at. (Note that depending on the + * implementation of cbfs_dev_t, this offset may still be relative to the start of a subregion + * of the underlying storage device.) + * + * The length of an mcache_entry (i.e. length of the underlying metadata blob) is encoded in the + * metadata (entry->file.h.offset). The next mcache_entry begins at the next + * CBFS_MCACHE_ALIGNMENT boundary after that. The cache is terminated by a special 4-byte + * mcache_entry that consists only of a magic number (MCACHE_MAGIC_END or MCACHE_MAGIC_FULL). + */ + +#define MCACHE_MAGIC_FILE 0x454c4946 /* 'FILE' */ +#define MCACHE_MAGIC_FULL 0x4c4c5546 /* 'FULL' */ +#define MCACHE_MAGIC_END 0x444e4524 /* '$END' */ + +union mcache_entry { + union cbfs_mdata file; + struct { /* These fields exactly overlap file.h.magic */ + uint32_t magic; + uint32_t offset; + }; +}; + +struct cbfs_mcache_build_args { + void *mcache; + void *end; + int count; +}; + +static cb_err_t build_walker(cbfs_dev_t dev, size_t offset, const union cbfs_mdata *mdata, + size_t already_read, void *arg) +{ + struct cbfs_mcache_build_args *args = arg; + union mcache_entry *entry = args->mcache; + const uint32_t data_offset = be32toh(mdata->h.offset); + + if (args->end - args->mcache < data_offset) + return CB_CBFS_CACHE_FULL; + + if (cbfs_copy_fill_metadata(args->mcache, mdata, already_read, dev, offset)) + return CB_CBFS_IO; + + entry->magic = MCACHE_MAGIC_FILE; + entry->offset = offset; + + args->mcache += ALIGN_UP(data_offset, CBFS_MCACHE_ALIGNMENT); + args->count++; + + return CB_CBFS_NOT_FOUND; +} + +cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t size, + struct vb2_hash *metadata_hash) +{ + struct cbfs_mcache_build_args args = { + .mcache = mcache, + .end = mcache + ALIGN_DOWN(size, CBFS_MCACHE_ALIGNMENT) + - sizeof(uint32_t), /* leave space for terminating magic */ + .count = 0, + }; + + assert(size > sizeof(uint32_t) && IS_ALIGNED((uintptr_t)mcache, CBFS_MCACHE_ALIGNMENT)); + cb_err_t ret = cbfs_walk(dev, build_walker, &args, metadata_hash, 0); + union mcache_entry *entry = args.mcache; + if (ret == CB_CBFS_NOT_FOUND) { + ret = CB_SUCCESS; + entry->magic = MCACHE_MAGIC_END; + } else if (ret == CB_CBFS_CACHE_FULL) { + ERROR("mcache overflow, should increase CBFS_MCACHE size!\n"); + entry->magic = MCACHE_MAGIC_FULL; + } + + LOG("mcache @%p built for %d files, used %#zx of %#zx bytes\n", mcache, + args.count, args.mcache + sizeof(entry->magic) - mcache, size); + return ret; +} + +cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out) +{ + const size_t namesize = strlen(name) + 1; /* Count trailing \0 so we can memcmp() it. */ + const void *end = mcache + mcache_size; + const void *current = mcache; + + while (current + sizeof(uint32_t) < end) { + const union mcache_entry *entry = current; + + if (entry->magic == MCACHE_MAGIC_END) + return CB_CBFS_NOT_FOUND; + if (entry->magic == MCACHE_MAGIC_FULL) + return CB_CBFS_CACHE_FULL; + + assert(entry->magic == MCACHE_MAGIC_FILE); + const uint32_t data_offset = be32toh(entry->file.h.offset); + const uint32_t data_length = be32toh(entry->file.h.len); + if (namesize <= data_offset - offsetof(union cbfs_mdata, filename) && + memcmp(name, entry->file.filename, namesize) == 0) { + LOG("Found '%s' @%#x size %#x in mcache @%p\n", + name, entry->offset, data_length, current); + *data_offset_out = entry->offset + data_offset; + memcpy(mdata_out, &entry->file, data_offset); + return CB_SUCCESS; + } + + current += ALIGN_UP(data_offset, CBFS_MCACHE_ALIGNMENT); + } + + ERROR("CBFS mcache overflow!\n"); + return CB_ERR; +} + +size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size) +{ + const void *end = mcache + mcache_size; + const void *current = mcache; + + while (current + sizeof(uint32_t) < end) { + const union mcache_entry *entry = current; + + if (entry->magic == MCACHE_MAGIC_FULL || entry->magic == MCACHE_MAGIC_END) { + current += sizeof(entry->magic); + break; + } + + assert(entry->magic == MCACHE_MAGIC_FILE); + current += ALIGN_UP(be32toh(entry->file.h.offset), CBFS_MCACHE_ALIGNMENT); + } + + return current - mcache; +} diff --git a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h index e5aa852617..b61b956524 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cb_err.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cb_err.h @@ -39,6 +39,7 @@ enum cb_err { CB_CBFS_IO = -400, /**< Underlying I/O error */ CB_CBFS_NOT_FOUND = -401, /**< File not found in directory */ CB_CBFS_HASH_MISMATCH = -402, /**< Master hash validation failed */ + CB_CBFS_CACHE_FULL = -403, /**< Metadata cache overflowed */ }; /* Don't typedef the enum directly, so the size is unambiguous for serialization. */ diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h index aaee62f4c3..64dcf9f5ba 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_private.h @@ -113,4 +113,25 @@ cb_err_t cbfs_copy_fill_metadata(union cbfs_mdata *dst, const union cbfs_mdata * cb_err_t cbfs_lookup(cbfs_dev_t dev, const char *name, union cbfs_mdata *mdata_out, size_t *data_offset_out, struct vb2_hash *metadata_hash); +/* Both base address and size of CBFS mcaches must be aligned to this value! */ +#define CBFS_MCACHE_ALIGNMENT sizeof(uint32_t) /* Largest data type used in CBFS */ + +/* Build an in-memory CBFS metadata cache out of the CBFS on |dev| into a |mcache_size| bytes + * memory area at |mcache|. Also verify |metadata_hash| unless it is NULL. If this returns + * CB_CBFS_CACHE_FULL, the mcache is still valid and can be used, but lookups may return + * CB_CBFS_CACHE_FULL for files that didn't fit to indicate that the caller needs to fall back + * to cbfs_lookup(). */ +cb_err_t cbfs_mcache_build(cbfs_dev_t dev, void *mcache, size_t mcache_size, + struct vb2_hash *metadata_hash); + +/* + * Find a file named |name| in a CBFS metadata cache and copy its metadata into |mdata_out|. + * Pass out offset to the file data (on the original CBFS device used for cbfs_mcache_build()). + */ +cb_err_t cbfs_mcache_lookup(const void *mcache, size_t mcache_size, const char *name, + union cbfs_mdata *mdata_out, size_t *data_offset_out); + +/* Returns the amount of bytes actually used by the CBFS metadata cache in |mcache|. */ +size_t cbfs_mcache_real_size(const void *mcache, size_t mcache_size); + #endif /* _COMMONLIB_BSD_CBFS_PRIVATE_H_ */ diff --git a/src/commonlib/include/commonlib/cbmem_id.h b/src/commonlib/include/commonlib/cbmem_id.h index 6b4d60469e..ab7cf63843 100644 --- a/src/commonlib/include/commonlib/cbmem_id.h +++ b/src/commonlib/include/commonlib/cbmem_id.h @@ -67,6 +67,8 @@ #define CBMEM_ID_ROM2 0x524f4d32 #define CBMEM_ID_ROM3 0x524f4d33 #define CBMEM_ID_FMAP 0x464d4150 +#define CBMEM_ID_CBFS_RO_MCACHE 0x524d5346 +#define CBMEM_ID_CBFS_RW_MCACHE 0x574d5346 #define CBMEM_ID_FSP_LOGO 0x4c4f474f #define CBMEM_ID_SMM_COMBUFFER 0x53534d32 @@ -129,5 +131,7 @@ { CBMEM_ID_ROM1, "VGA ROM #1 "}, \ { CBMEM_ID_ROM2, "VGA ROM #2 "}, \ { CBMEM_ID_ROM3, "VGA ROM #3 "}, \ - { CBMEM_ID_FMAP, "FMAP "}, + { CBMEM_ID_FMAP, "FMAP "}, \ + { CBMEM_ID_CBFS_RO_MCACHE, "RO MCACHE "}, \ + { CBMEM_ID_CBFS_RW_MCACHE, "RW MCACHE "} #endif /* _CBMEM_ID_H_ */ diff --git a/src/include/cbfs.h b/src/include/cbfs.h index a35597d5b1..32ed7f899e 100644 --- a/src/include/cbfs.h +++ b/src/include/cbfs.h @@ -3,10 +3,10 @@ #ifndef _CBFS_H_ #define _CBFS_H_ +#include #include #include -#include -#include +#include /*********************************************** * Perform CBFS operations on the boot device. * @@ -42,8 +42,21 @@ size_t cbfs_load_and_decompress(const struct region_device *rdev, size_t offset, /* Load stage into memory filling in prog. Return 0 on success. < 0 on error. */ int cbfs_prog_stage_load(struct prog *prog); -/* Returns the region device of the currently active CBFS. - Return < 0 on error, 0 on success. */ -int cbfs_boot_region_device(struct region_device *rdev); +struct cbfs_boot_device { + struct region_device rdev; + void *mcache; + size_t mcache_size; +}; + +/* Helper to fill out |mcache| and |mcache_size| in a cbfs_boot_device. */ +void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, uint32_t id); + +/* + * Retrieves the currently active CBFS boot device. If |force_ro| is set, will + * always return the read-only CBFS instead (this only makes a difference when + * CONFIG(VBOOT) is enabled). May perform certain CBFS initialization tasks. + * Returns NULL on error (e.g. boot device IO error). + */ +const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro); #endif diff --git a/src/include/memlayout.h b/src/include/memlayout.h index bd1d6846f0..bf830b7d24 100644 --- a/src/include/memlayout.h +++ b/src/include/memlayout.h @@ -71,6 +71,9 @@ _ = ASSERT(sz >= FMAP_SIZE, \ STR(FMAP does not fit in FMAP_CACHE! (sz < FMAP_SIZE))); +#define CBFS_MCACHE(addr, sz) \ + REGION(cbfs_mcache, addr, sz, 4) + #if ENV_ROMSTAGE_OR_BEFORE #define PRERAM_CBFS_CACHE(addr, size) \ REGION(preram_cbfs_cache, addr, size, 4) \ diff --git a/src/include/symbols.h b/src/include/symbols.h index 371d84bf9b..6fe24f5e44 100644 --- a/src/include/symbols.h +++ b/src/include/symbols.h @@ -33,6 +33,7 @@ DECLARE_REGION(stack) DECLARE_REGION(preram_cbfs_cache) DECLARE_REGION(postram_cbfs_cache) DECLARE_REGION(cbfs_cache) +DECLARE_REGION(cbfs_mcache) DECLARE_REGION(fmap_cache) DECLARE_REGION(tpm_tcpa_log) diff --git a/src/lib/Kconfig b/src/lib/Kconfig index d6e7e51d5c..ab2b9c59b9 100644 --- a/src/lib/Kconfig +++ b/src/lib/Kconfig @@ -80,3 +80,24 @@ config ESPI_DEBUG help This option enables eSPI library helper functions for displaying debug information. + +config NO_CBFS_MCACHE + bool + default y + help + Disables the CBFS metadata cache. This means that your platform does + not need to provide a CBFS_MCACHE section in memlayout and can save + the associated CAR/SRAM size. In that case every single CBFS file + lookup must re-read the same CBFS directory entries from flash to find + the respective file. + +config CBFS_MCACHE_RW_PERCENTAGE + int + depends on VBOOT && !NO_CBFS_MCACHE + default 25 if CHROMEOS # Chrome OS stores many L10n files in RO only + default 50 + help + The amount of the CBFS_MCACHE area that's used for the RW CBFS, in + percent from 0 to 100. The remaining area will be used for the RO + CBFS. Default is an even 50/50 split. When VBOOT is disabled, this + will automatically be 0 (meaning the whole MCACHE is used for RO). diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 447d91f1be..3b7d4292d0 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -3,6 +3,7 @@ #include #include #include +#include #include #include #include @@ -16,22 +17,33 @@ #include #include +static cb_err_t cbfs_boot_lookup(const struct cbfs_boot_device *cbd, + const char *name, union cbfs_mdata *mdata, size_t *data_offset) +{ + cb_err_t err = CB_CBFS_CACHE_FULL; + if (!CONFIG(NO_CBFS_MCACHE) && !ENV_SMM) + err = cbfs_mcache_lookup(cbd->mcache, cbd->mcache_size, + name, mdata, data_offset); + if (err == CB_CBFS_CACHE_FULL) + err = cbfs_lookup(&cbd->rdev, name, mdata, data_offset, NULL); + return err; +} + int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) { - struct region_device rdev; - - if (cbfs_boot_region_device(&rdev)) + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + if (!cbd) return -1; size_t data_offset; - cb_err_t err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL); + cb_err_t err = cbfs_boot_lookup(cbd, name, &fh->mdata, &data_offset); if (CONFIG(VBOOT_ENABLE_CBFS_FALLBACK) && err == CB_CBFS_NOT_FOUND) { printk(BIOS_INFO, "CBFS: Fall back to RO region for %s\n", name); - if (fmap_locate_area_as_rdev("COREBOOT", &rdev)) + if (!(cbd = cbfs_get_boot_device(true))) return -1; - err = cbfs_lookup(&rdev, name, &fh->mdata, &data_offset, NULL); + err = cbfs_boot_lookup(cbd, name, &fh->mdata, &data_offset); } if (err) return -1; @@ -39,7 +51,8 @@ int cbfs_boot_locate(struct cbfsf *fh, const char *name, uint32_t *type) size_t msize = be32toh(fh->mdata.h.offset); if (rdev_chain(&fh->metadata, &addrspace_32bit.rdev, (uintptr_t)&fh->mdata, msize) || - rdev_chain(&fh->data, &rdev, data_offset, be32toh(fh->mdata.h.len))) + rdev_chain(&fh->data, &cbd->rdev, data_offset, + be32toh(fh->mdata.h.len))) return -1; if (type) { if (!*type) @@ -333,9 +346,86 @@ out: return 0; } -int cbfs_boot_region_device(struct region_device *rdev) +void cbfs_boot_device_find_mcache(struct cbfs_boot_device *cbd, uint32_t id) { - boot_device_init(); - return vboot_locate_cbfs(rdev) && - fmap_locate_area_as_rdev("COREBOOT", rdev); + if (CONFIG(NO_CBFS_MCACHE) || ENV_SMM) + return; + + const struct cbmem_entry *entry; + if (cbmem_possibly_online() && + (entry = cbmem_entry_find(id))) { + cbd->mcache = cbmem_entry_start(entry); + cbd->mcache_size = cbmem_entry_size(entry); + } else if (ENV_ROMSTAGE_OR_BEFORE) { + u8 *boundary = _ecbfs_mcache - REGION_SIZE(cbfs_mcache) * + CONFIG_CBFS_MCACHE_RW_PERCENTAGE / 100; + boundary = (u8 *)ALIGN_DOWN((uintptr_t)boundary, + CBFS_MCACHE_ALIGNMENT); + if (id == CBMEM_ID_CBFS_RO_MCACHE) { + cbd->mcache = _cbfs_mcache; + cbd->mcache_size = boundary - _cbfs_mcache; + } else if (id == CBMEM_ID_CBFS_RW_MCACHE) { + cbd->mcache = boundary; + cbd->mcache_size = _ecbfs_mcache - boundary; + } + } } + +const struct cbfs_boot_device *cbfs_get_boot_device(bool force_ro) +{ + static struct cbfs_boot_device ro; + + /* Ensure we always init RO mcache, even if first file is from RW. + Otherwise it may not be available when needed in later stages. */ + if (ENV_INITIAL_STAGE && !force_ro && !region_device_sz(&ro.rdev)) + cbfs_get_boot_device(true); + + if (!force_ro) { + const struct cbfs_boot_device *rw = vboot_get_cbfs_boot_device(); + /* This will return NULL if vboot isn't enabled, didn't run yet + or decided to boot into recovery mode. */ + if (rw) + return rw; + } + + if (region_device_sz(&ro.rdev)) + return &ro; + + if (fmap_locate_area_as_rdev("COREBOOT", &ro.rdev)) + return NULL; + + cbfs_boot_device_find_mcache(&ro, CBMEM_ID_CBFS_RO_MCACHE); + + if (ENV_INITIAL_STAGE && !CONFIG(NO_CBFS_MCACHE)) { + cb_err_t err = cbfs_mcache_build(&ro.rdev, ro.mcache, + ro.mcache_size, NULL); + if (err && err != CB_CBFS_CACHE_FULL) + die("Failed to build RO mcache"); + } + + return &ro; +} + +#if !CONFIG(NO_CBFS_MCACHE) +static void mcache_to_cbmem(const struct cbfs_boot_device *cbd, u32 cbmem_id) +{ + if (!cbd) + return; + + size_t real_size = cbfs_mcache_real_size(cbd->mcache, cbd->mcache_size); + void *cbmem_mcache = cbmem_add(cbmem_id, real_size); + if (!cbmem_mcache) { + printk(BIOS_ERR, "ERROR: Cannot allocate CBMEM mcache %#x (%#zx bytes)!\n", + cbmem_id, real_size); + return; + } + memcpy(cbmem_mcache, cbd->mcache, real_size); +} + +static void cbfs_mcache_migrate(int unused) +{ + mcache_to_cbmem(vboot_get_cbfs_boot_device(), CBMEM_ID_CBFS_RW_MCACHE); + mcache_to_cbmem(cbfs_get_boot_device(true), CBMEM_ID_CBFS_RO_MCACHE); +} +ROMSTAGE_CBMEM_INIT_HOOK(cbfs_mcache_migrate) +#endif diff --git a/src/lib/coreboot_table.c b/src/lib/coreboot_table.c index 69ded3c700..4cbf3c742e 100644 --- a/src/lib/coreboot_table.c +++ b/src/lib/coreboot_table.c @@ -220,11 +220,8 @@ static void lb_boot_media_params(struct lb_header *header) { struct lb_boot_media_params *bmp; const struct region_device *boot_dev; - struct region_device cbfs_dev; - - boot_device_init(); - - if (cbfs_boot_region_device(&cbfs_dev)) + const struct cbfs_boot_device *cbd = cbfs_get_boot_device(false); + if (!cbd) return; boot_dev = boot_device_ro(); @@ -235,8 +232,8 @@ static void lb_boot_media_params(struct lb_header *header) bmp->tag = LB_TAG_BOOT_MEDIA_PARAMS; bmp->size = sizeof(*bmp); - bmp->cbfs_offset = region_device_offset(&cbfs_dev); - bmp->cbfs_size = region_device_sz(&cbfs_dev); + bmp->cbfs_offset = region_device_offset(&cbd->rdev); + bmp->cbfs_size = region_device_sz(&cbd->rdev); bmp->boot_media_size = region_device_sz(boot_dev); bmp->fmap_offset = get_fmap_flash_offset(); diff --git a/src/security/vboot/vboot_common.h b/src/security/vboot/vboot_common.h index e64f6632a7..512da0e91f 100644 --- a/src/security/vboot/vboot_common.h +++ b/src/security/vboot/vboot_common.h @@ -3,6 +3,7 @@ #define __VBOOT_VBOOT_COMMON_H__ #include +#include #include /* @@ -50,14 +51,17 @@ int vboot_developer_mode_enabled(void); int vboot_recovery_mode_enabled(void); int vboot_can_enable_udc(void); void vboot_run_logic(void); -int vboot_locate_cbfs(struct region_device *rdev); +const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void); #else /* !CONFIG_VBOOT */ static inline int vboot_developer_mode_enabled(void) { return 0; } static inline int vboot_recovery_mode_enabled(void) { return 0; } /* If VBOOT is not enabled, we are okay enabling USB device controller (UDC). */ static inline int vboot_can_enable_udc(void) { return 1; } static inline void vboot_run_logic(void) {} -static inline int vboot_locate_cbfs(struct region_device *rdev) { return -1; } +static inline const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void) +{ + return NULL; +} #endif void vboot_save_data(struct vb2_context *ctx); diff --git a/src/security/vboot/vboot_loader.c b/src/security/vboot/vboot_loader.c index bca4c3e3b7..9c6e56e9af 100644 --- a/src/security/vboot/vboot_loader.c +++ b/src/security/vboot/vboot_loader.c @@ -1,6 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include +#include #include #include #include @@ -22,12 +25,27 @@ _Static_assert(!CONFIG(VBOOT_RETURN_FROM_VERSTAGE) || int vboot_executed; +static void build_rw_mcache(void) +{ + if (CONFIG(NO_CBFS_MCACHE)) + return; + + const struct cbfs_boot_device *cbd = vboot_get_cbfs_boot_device(); + if (!cbd) /* Don't build RW mcache in recovery mode. */ + return; + cb_err_t err = cbfs_mcache_build(&cbd->rdev, cbd->mcache, + cbd->mcache_size, NULL); + if (err && err != CB_CBFS_CACHE_FULL) + die("Failed to build RW mcache."); /* TODO: -> recovery? */ +} + void vboot_run_logic(void) { if (verification_should_run()) { /* Note: this path is not used for VBOOT_RETURN_FROM_VERSTAGE */ verstage_main(); vboot_executed = 1; + build_rw_mcache(); } else if (verstage_should_load()) { struct cbfsf file; struct prog verstage = @@ -55,21 +73,29 @@ void vboot_run_logic(void) return; vboot_executed = 1; + build_rw_mcache(); } } -int vboot_locate_cbfs(struct region_device *rdev) +const struct cbfs_boot_device *vboot_get_cbfs_boot_device(void) { - struct vb2_context *ctx; - /* Don't honor vboot results until the vboot logic has run. */ if (!vboot_logic_executed()) - return -1; + return NULL; - ctx = vboot_get_context(); + static struct cbfs_boot_device cbd; + if (region_device_sz(&cbd.rdev)) + return &cbd; + struct vb2_context *ctx = vboot_get_context(); if (ctx->flags & VB2_CONTEXT_RECOVERY_MODE) - return -1; + return NULL; - return vboot_locate_firmware(ctx, rdev); + boot_device_init(); + if (vboot_locate_firmware(ctx, &cbd.rdev)) + return NULL; + + cbfs_boot_device_find_mcache(&cbd, CBMEM_ID_CBFS_RW_MCACHE); + + return &cbd; } From aad4651e3eab260c94058536d373b2ff22b40d92 Mon Sep 17 00:00:00 2001 From: Yidi Lin Date: Fri, 20 Nov 2020 14:03:20 +0800 Subject: [PATCH 014/107] mb/google/asurada: Get RAM code from ADC 3 On Chromebooks the RAM code is implemented by the resistor straps that we can read and decode from ADC. For Asurada the RAM code can be read from ADC channel 3. Signed-off-by: CK Hu Signed-off-by: Yidi Lin Change-Id: Iaadabea1b6aa91c48b137f7c6784ab7ee0adc473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46391 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin Reviewed-by: Angel Pons --- src/mainboard/google/asurada/boardid.c | 57 +++++++++++++++++++++++++- 1 file changed, 56 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/asurada/boardid.c b/src/mainboard/google/asurada/boardid.c index 2c8efcddd8..cb91812bbf 100644 --- a/src/mainboard/google/asurada/boardid.c +++ b/src/mainboard/google/asurada/boardid.c @@ -1,9 +1,59 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include +#include +#include /* board_id is provided by ec/google/chromeec/ec_boardid.c */ +#define ADC_LEVELS 15 + +enum { + RAM_ID_CHANNEL = 3, +}; + +static const unsigned int ram_voltages[ADC_LEVELS] = { + /* ID : Voltage (unit: uV) */ + [0] = 74300, + [1] = 211700, + [2] = 318800, + [3] = 428600, + [4] = 541700, + [5] = 665800, + [6] = 781400, + [7] = 900000, + [8] = 1023100, + [9] = 1137000, + [10] = 1240000, + [11] = 1342600, + [12] = 1457500, + [13] = 1575600, + [14] = 1683600, +}; + +static const unsigned int *adc_voltages[] = { + [RAM_ID_CHANNEL] = ram_voltages, +}; + +static uint32_t get_adc_index(unsigned int channel) +{ + unsigned int value = auxadc_get_voltage_uv(channel); + + assert(channel < ARRAY_SIZE(adc_voltages)); + const unsigned int *voltages = adc_voltages[channel]; + assert(voltages); + + /* Find the closest voltage */ + uint32_t id; + for (id = 0; id < ADC_LEVELS - 1; id++) + if (value < (voltages[id] + voltages[id + 1]) / 2) + break; + + printk(BIOS_DEBUG, "ADC[%u]: Raw value=%u ID=%u\n", channel, value, id); + return id; +} + uint32_t sku_id(void) { return 0; @@ -11,5 +61,10 @@ uint32_t sku_id(void) uint32_t ram_code(void) { - return 0; + static uint32_t cached_ram_code = BOARD_ID_INIT; + + if (cached_ram_code == BOARD_ID_INIT) + cached_ram_code = get_adc_index(RAM_ID_CHANNEL); + + return cached_ram_code; } From 65d9a7ae3116b636f6fa75311a1fb648d944f91b Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 18 Nov 2020 23:46:24 +0530 Subject: [PATCH 015/107] vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1474_11 List of changes: 1. FSP-M Header: - Rename UPD Offset UnusedUpdSpace33 -> UnusedUpdSpace32 2. FSP-S Header: - Adjust UPD Offset for Reservedxx Change-Id: I99294da825f47135d1336a6ad90b1c9bb73eb849 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47722 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- .../intel/fsp/fsp2_0/alderlake/FspmUpd.h | 2 +- .../intel/fsp/fsp2_0/alderlake/FspsUpd.h | 112 +++++++++--------- 2 files changed, 55 insertions(+), 59 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index 552f50af3b..da746ba3e4 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -965,7 +965,7 @@ typedef struct { /** Offset 0x0B88 **/ - UINT8 UnusedUpdSpace33[6]; + UINT8 UnusedUpdSpace32[6]; /** Offset 0x0B8E **/ diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index e78311cec9..38945d0d2c 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -650,51 +650,47 @@ typedef struct { /** Offset 0x0951 - Reserved **/ - UINT8 Reserved35[105]; + UINT8 Reserved35[132]; -/** Offset 0x09BA - PCH Sata Pwr Opt Enable +/** Offset 0x09D5 - PCH Sata Pwr Opt Enable SATA Power Optimizer on PCH side. $EN_DIS **/ UINT8 SataPwrOptEnable; -/** Offset 0x09BB - Reserved +/** Offset 0x09D6 - Reserved **/ UINT8 Reserved36[50]; -/** Offset 0x09ED - Enable SATA Port DmVal +/** Offset 0x0A08 - Enable SATA Port DmVal DITO multiplier. Default is 15. **/ UINT8 SataPortsDmVal[8]; -/** Offset 0x09F5 - Reserved -**/ - UINT8 Reserved37; - -/** Offset 0x09F6 - Enable SATA Port DmVal +/** Offset 0x0A10 - Enable SATA Port DmVal DEVSLP Idle Timeout (DITO), Default is 625. **/ UINT16 SataPortsDitoVal[8]; -/** Offset 0x0A06 - Reserved +/** Offset 0x0A20 - Reserved **/ - UINT8 Reserved38[62]; + UINT8 Reserved37[62]; -/** Offset 0x0A44 - USB2 Port Over Current Pin +/** Offset 0x0A5E - USB2 Port Over Current Pin Describe the specific over current pin number of USB 2.0 Port N. **/ UINT8 Usb2OverCurrentPin[16]; -/** Offset 0x0A54 - USB3 Port Over Current Pin +/** Offset 0x0A6E - USB3 Port Over Current Pin Describe the specific over current pin number of USB 3.0 Port N. **/ UINT8 Usb3OverCurrentPin[10]; -/** Offset 0x0A5E - Reserved +/** Offset 0x0A78 - Reserved **/ - UINT8 Reserved39[14]; + UINT8 Reserved38[16]; -/** Offset 0x0A6C - Enable 8254 Static Clock Gating +/** Offset 0x0A88 - Enable 8254 Static Clock Gating Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support legacy OS using 8254 timer. Also enable this while S0ix is enabled. @@ -702,7 +698,7 @@ typedef struct { **/ UINT8 Enable8254ClockGating; -/** Offset 0x0A6D - Enable 8254 Static Clock Gating On S3 +/** Offset 0x0A89 - Enable 8254 Static Clock Gating On S3 This is only applicable when Enable8254ClockGating is disabled. FSP will do the 8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This avoids the SMI requirement for the programming. @@ -710,22 +706,22 @@ typedef struct { **/ UINT8 Enable8254ClockGatingOnS3; -/** Offset 0x0A6E - Reserved +/** Offset 0x0A8A - Reserved **/ - UINT8 Reserved40; + UINT8 Reserved39; -/** Offset 0x0A6F - Hybrid Storage Detection and Configuration Mode +/** Offset 0x0A8B - Hybrid Storage Detection and Configuration Mode Enables support for Hybrid storage devices. 0: Disabled; 1: Dynamic Configuration. Default is 0: Disabled 0: Disabled, 1: Dynamic Configuration **/ UINT8 HybridStorageMode; -/** Offset 0x0A70 - Reserved +/** Offset 0x0A8C - Reserved **/ - UINT8 Reserved41[89]; + UINT8 Reserved40[93]; -/** Offset 0x0AC9 - Enable PS_ON. +/** Offset 0x0AE9 - Enable PS_ON. PS_ON is a new C10 state from the CPU on desktop SKUs that enables a lower power target that will be required by the California Energy Commission (CEC). When FALSE, PS_ON is to be disabled. @@ -733,29 +729,29 @@ typedef struct { **/ UINT8 PsOnEnable; -/** Offset 0x0ACA - Reserved +/** Offset 0x0AEA - Reserved **/ - UINT8 Reserved42[310]; + UINT8 Reserved41[318]; -/** Offset 0x0C00 - RpPtmBytes +/** Offset 0x0C28 - RpPtmBytes **/ UINT8 RpPtmBytes[4]; -/** Offset 0x0C04 - Reserved +/** Offset 0x0C2C - Reserved **/ - UINT8 Reserved43[99]; + UINT8 Reserved42[95]; -/** Offset 0x0C67 - Enable/Disable IGFX PmSupport +/** Offset 0x0C8B - Enable/Disable IGFX PmSupport Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport $EN_DIS **/ UINT8 PmSupport; -/** Offset 0x0C68 - Reserved +/** Offset 0x0C8C - Reserved **/ - UINT8 Reserved44; + UINT8 Reserved43; -/** Offset 0x0C69 - GT Frequency Limit +/** Offset 0x0C8D - GT Frequency Limit 0xFF: Auto(Default), 2: 100 Mhz, 3: 150 Mhz, 4: 200 Mhz, 5: 250 Mhz, 6: 300 Mhz, 7: 350 Mhz, 8: 400 Mhz, 9: 450 Mhz, 0xA: 500 Mhz, 0xB: 550 Mhz, 0xC: 600 Mhz, 0xD: 650 Mhz, 0xE: 700 Mhz, 0xF: 750 Mhz, 0x10: 800 Mhz, 0x11: 850 Mhz, 0x12:900 Mhz, @@ -769,22 +765,22 @@ typedef struct { **/ UINT8 GtFreqMax; -/** Offset 0x0C6A - Reserved +/** Offset 0x0C8E - Reserved **/ - UINT8 Reserved45[24]; + UINT8 Reserved44[24]; -/** Offset 0x0C82 - Enable or Disable HWP +/** Offset 0x0CA6 - Enable or Disable HWP Enable or Disable HWP(Hardware P states) Support. 0: Disable; 1: Enable; 2-3:Reserved $EN_DIS **/ UINT8 Hwp; -/** Offset 0x0C83 - Reserved +/** Offset 0x0CA7 - Reserved **/ - UINT8 Reserved46[8]; + UINT8 Reserved45[8]; -/** Offset 0x0C8B - TCC Activation Offset +/** Offset 0x0CAF - TCC Activation Offset TCC Activation Offset. Offset from factory set TCC activation temperature at which the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation Temperature, in volts.For SKL Y SKU, the recommended default for this policy is @@ -792,63 +788,63 @@ typedef struct { **/ UINT8 TccActivationOffset; -/** Offset 0x0C8C - Reserved +/** Offset 0x0CB0 - Reserved **/ - UINT8 Reserved47[34]; + UINT8 Reserved46[34]; -/** Offset 0x0CAE - Enable or Disable CPU power states (C-states) +/** Offset 0x0CD2 - Enable or Disable CPU power states (C-states) Enable or Disable CPU power states (C-states). 0: Disable; 1: Enable $EN_DIS **/ UINT8 Cx; -/** Offset 0x0CAF - Reserved +/** Offset 0x0CD3 - Reserved **/ - UINT8 Reserved48[196]; + UINT8 Reserved47[196]; -/** Offset 0x0D73 - Enable LOCKDOWN SMI +/** Offset 0x0D97 - Enable LOCKDOWN SMI Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. $EN_DIS **/ UINT8 PchLockDownGlobalSmi; -/** Offset 0x0D74 - Enable LOCKDOWN BIOS Interface +/** Offset 0x0D98 - Enable LOCKDOWN BIOS Interface Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register. $EN_DIS **/ UINT8 PchLockDownBiosInterface; -/** Offset 0x0D75 - Unlock all GPIO pads +/** Offset 0x0D99 - Unlock all GPIO pads Force all GPIO pads to be unlocked for debug purpose. $EN_DIS **/ UINT8 PchUnlockGpioPads; -/** Offset 0x0D76 - Reserved +/** Offset 0x0D9A - Reserved **/ - UINT8 Reserved49[2]; + UINT8 Reserved48[2]; -/** Offset 0x0D78 - PCIE RP Ltr Max Snoop Latency +/** Offset 0x0D9C - PCIE RP Ltr Max Snoop Latency Latency Tolerance Reporting, Max Snoop Latency. **/ UINT16 PcieRpLtrMaxSnoopLatency[28]; -/** Offset 0x0DB0 - PCIE RP Ltr Max No Snoop Latency +/** Offset 0x0DD4 - PCIE RP Ltr Max No Snoop Latency Latency Tolerance Reporting, Max Non-Snoop Latency. **/ UINT16 PcieRpLtrMaxNoSnoopLatency[28]; -/** Offset 0x0DE8 - Reserved +/** Offset 0x0E0C - Reserved **/ - UINT8 Reserved50[313]; + UINT8 Reserved49[313]; -/** Offset 0x0F21 - LpmStateEnableMask +/** Offset 0x0F45 - LpmStateEnableMask **/ UINT8 LpmStateEnableMask; -/** Offset 0x0F22 - Reserved +/** Offset 0x0F46 - Reserved **/ - UINT8 Reserved51[702]; + UINT8 Reserved50[698]; } FSP_S_CONFIG; /** Fsp S UPD Configuration @@ -867,11 +863,11 @@ typedef struct { **/ FSP_S_CONFIG FspsConfig; -/** Offset 0x11E0 +/** Offset 0x1200 **/ - UINT8 UnusedUpdSpace45[6]; + UINT8 UnusedUpdSpace46[6]; -/** Offset 0x11E6 +/** Offset 0x1206 **/ UINT16 UpdTerminator; } FSPS_UPD; From ea3402213ff4b80bf8ebfb8502e49aa071cf3d74 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 14 Nov 2020 01:58:47 +0100 Subject: [PATCH 016/107] soc/amd: factor out vbnv_cmos_failed() into soc/amd/common/vboot Change-Id: I7f976c6c5a2a715e1a5372bb93fe657d0d86c848 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47584 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/soc/amd/common/Makefile.inc | 5 ++++- src/soc/amd/common/vboot/Makefile.inc | 6 ++++++ .../{picasso/pmutil.c => common/vboot/vbnv_cmos.c} | 0 src/soc/amd/picasso/Makefile.inc | 4 ---- src/soc/amd/stoneyridge/Makefile.inc | 4 ---- src/soc/amd/stoneyridge/pmutil.c | 14 -------------- 6 files changed, 10 insertions(+), 23 deletions(-) create mode 100644 src/soc/amd/common/vboot/Makefile.inc rename src/soc/amd/{picasso/pmutil.c => common/vboot/vbnv_cmos.c} (100%) delete mode 100644 src/soc/amd/stoneyridge/pmutil.c diff --git a/src/soc/amd/common/Makefile.inc b/src/soc/amd/common/Makefile.inc index c0757c5968..418539bca7 100644 --- a/src/soc/amd/common/Makefile.inc +++ b/src/soc/amd/common/Makefile.inc @@ -1 +1,4 @@ -subdirs-$(CONFIG_SOC_AMD_COMMON) += block +ifeq ($(CONFIG_SOC_AMD_COMMON),y) +subdirs-y += block +subdirs-y += vboot +endif diff --git a/src/soc/amd/common/vboot/Makefile.inc b/src/soc/amd/common/vboot/Makefile.inc new file mode 100644 index 0000000000..aff927a5d0 --- /dev/null +++ b/src/soc/amd/common/vboot/Makefile.inc @@ -0,0 +1,6 @@ +ifeq ($(CONFIG_VBOOT_VBNV_CMOS),y) +bootblock-y += vbnv_cmos.c +verstage-y += vbnv_cmos.c +romstage-y += vbnv_cmos.c +ramstage-y += vbnv_cmos.c +endif diff --git a/src/soc/amd/picasso/pmutil.c b/src/soc/amd/common/vboot/vbnv_cmos.c similarity index 100% rename from src/soc/amd/picasso/pmutil.c rename to src/soc/amd/common/vboot/vbnv_cmos.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index ffc1463b19..6ec4cd1151 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -23,14 +23,12 @@ bootblock-y += tsc_freq.c bootblock-y += gpio.c bootblock-y += smi_util.c bootblock-y += config.c -bootblock-y += pmutil.c bootblock-y += reset.c bootblock-$(CONFIG_VBOOT_STARTS_BEFORE_BOOTBLOCK) += bootblock/vboot_bootblock.c romstage-y += i2c.c romstage-y += romstage.c romstage-y += gpio.c -romstage-y += pmutil.c romstage-y += reset.c romstage-y += memmap.c romstage-y += uart.c @@ -45,7 +43,6 @@ romstage-y += config.c romstage-y += mrc_cache.c verstage-y += i2c.c -verstage-y += pmutil.c verstage-y += config.c verstage-y += aoac.c verstage_x86-y += gpio.c @@ -66,7 +63,6 @@ ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += gpio.c ramstage-y += aoac.c ramstage-y += southbridge.c -ramstage-y += pmutil.c ramstage-y += reset.c ramstage-y += acp.c ramstage-y += sata.c diff --git a/src/soc/amd/stoneyridge/Makefile.inc b/src/soc/amd/stoneyridge/Makefile.inc index fb0a45bd65..311ea6886b 100644 --- a/src/soc/amd/stoneyridge/Makefile.inc +++ b/src/soc/amd/stoneyridge/Makefile.inc @@ -17,7 +17,6 @@ bootblock-y += gpio.c bootblock-y += i2c.c bootblock-y += enable_usbdebug.c bootblock-y += monotonic_timer.c -bootblock-y += pmutil.c bootblock-y += tsc_freq.c bootblock-y += southbridge.c bootblock-$(CONFIG_HAVE_SMI_HANDLER) += smi_util.c @@ -28,7 +27,6 @@ romstage-y += romstage.c romstage-y += enable_usbdebug.c romstage-y += gpio.c romstage-y += monotonic_timer.c -romstage-y += pmutil.c romstage-y += smbus_spd.c romstage-y += memmap.c romstage-$(CONFIG_STONEYRIDGE_UART) += uart.c @@ -40,7 +38,6 @@ romstage-y += psp.c verstage-y += gpio.c verstage-y += i2c.c verstage-y += monotonic_timer.c -verstage-y += pmutil.c verstage-$(CONFIG_STONEYRIDGE_UART) += uart.c verstage-y += tsc_freq.c @@ -61,7 +58,6 @@ ramstage-y += gpio.c ramstage-y += monotonic_timer.c ramstage-y += southbridge.c ramstage-y += northbridge.c -ramstage-y += pmutil.c ramstage-y += sata.c ramstage-y += memmap.c ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c diff --git a/src/soc/amd/stoneyridge/pmutil.c b/src/soc/amd/stoneyridge/pmutil.c deleted file mode 100644 index a2ad2db4c1..0000000000 --- a/src/soc/amd/stoneyridge/pmutil.c +++ /dev/null @@ -1,14 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include - -int vbnv_cmos_failed(void) -{ - /* If CMOS power has failed, the century will be set to 0xff */ - return cmos_read(RTC_CLK_ALTCENTURY) == 0xff; -} From ea3417b5eb7de9d1c0a41724c0281fa7d30a97f8 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Fri, 20 Nov 2020 20:08:42 +0100 Subject: [PATCH 017/107] util/amdfwtool: add missing zero-initialization for local variable Change-Id: Ib156b16b874f74f58bd816071db3a7acf33c5aaf Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47817 Reviewed-by: Furquan Shaikh Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- util/amdfwtool/data_parse.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/util/amdfwtool/data_parse.c b/util/amdfwtool/data_parse.c index c2ce32befb..21e7317e22 100644 --- a/util/amdfwtool/data_parse.c +++ b/util/amdfwtool/data_parse.c @@ -224,7 +224,8 @@ static uint8_t find_register_fw_filename_bios_dir(char *fw_name, char *filename, { amd_bios_type fw_type = AMD_BIOS_INVALID; amd_bios_entry *bhd_tableptr; - uint8_t subprog, instance = 0; + uint8_t subprog = 0; + uint8_t instance = 0; (void) (cb_config); /* Remove warning and reserved for future. */ From 53ed3e501f4744b4dd42c1418819a5546fe4f0cf Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 20 Nov 2020 19:07:30 +0100 Subject: [PATCH 018/107] sb/intel/lynxpoint/smbus.c: Remove invalid PCI IDs These two IDs are for Cougar Point and Panther Point, the previous generation of Platform Controller Hubs. So, drop their device IDs. Change-Id: I27a58720f32b1cc3eb68c0af2d6819e16c36b954 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47816 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Nico Huber --- src/southbridge/intel/lynxpoint/smbus.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/southbridge/intel/lynxpoint/smbus.c b/src/southbridge/intel/lynxpoint/smbus.c index f616473fb9..2741951a4e 100644 --- a/src/southbridge/intel/lynxpoint/smbus.c +++ b/src/southbridge/intel/lynxpoint/smbus.c @@ -80,7 +80,7 @@ static struct device_operations smbus_ops = { }; static const unsigned short pci_device_ids[] = { - 0x1c22, 0x1e22, 0x8c22, 0x9c22, + 0x8c22, 0x9c22, 0 }; From 9065f4f8ed2facb60df3f4906b8e1e66e8958379 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Sat, 21 Nov 2020 02:12:54 +0100 Subject: [PATCH 019/107] soc/amd: move non-CAR linker scripts to common directory AMD family 17h and newer don't use cache as RAM, since the RAM is already initialized by the PSP when the x86 cores are released from reset. Therefore they use a different linker script as the rest of the x86 chips in coreboot do. Since there will be support for newer generations than Picasso will be added, move those linker scripts from soc/amd/picasso to soc/amd/common/block/cpu/noncar. TEST=Timeless build of amd/mandolin and amd/gardenia result in identical binaries. Change-Id: Ie60372aa498b6e505708f97213b502c9d0b3534b Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47828 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson --- src/soc/amd/common/block/cpu/Kconfig | 16 ++++++++++++++++ .../block/cpu/noncar}/memlayout.ld | 0 .../block/cpu/noncar}/memlayout_psp_verstage.ld | 2 ++ .../cpu/noncar}/memlayout_transfer_buffer.inc | 0 .../block/cpu/noncar}/memlayout_x86.ld | 0 src/soc/amd/picasso/Kconfig | 5 +---- 6 files changed, 19 insertions(+), 4 deletions(-) rename src/soc/amd/{picasso => common/block/cpu/noncar}/memlayout.ld (100%) rename src/soc/amd/{picasso => common/block/cpu/noncar}/memlayout_psp_verstage.ld (94%) rename src/soc/amd/{picasso => common/block/cpu/noncar}/memlayout_transfer_buffer.inc (100%) rename src/soc/amd/{picasso => common/block/cpu/noncar}/memlayout_x86.ld (100%) diff --git a/src/soc/amd/common/block/cpu/Kconfig b/src/soc/amd/common/block/cpu/Kconfig index f6756e18f8..826f80bdb5 100644 --- a/src/soc/amd/common/block/cpu/Kconfig +++ b/src/soc/amd/common/block/cpu/Kconfig @@ -11,3 +11,19 @@ config SOC_AMD_COMMON_BLOCK_CAR This is only used for AMD CPU before family 17h. From family 17h on the RAM is already initialized by the PSP before the x86 cores are released from reset. + +config SOC_AMD_COMMON_BLOCK_NONCAR + bool + default n + help + From family 17h on AMD CPUs/APUs don't use cache as RAM (CAR) any + more, since the RAM initialization is already done by the PSP when + the x86 cores are released from reset. + +if SOC_AMD_COMMON_BLOCK_NONCAR + +config MEMLAYOUT_LD_FILE + string + default "src/soc/amd/common/block/cpu/noncar/memlayout.ld" + +endif # SOC_AMD_COMMON_BLOCK_NONCAR diff --git a/src/soc/amd/picasso/memlayout.ld b/src/soc/amd/common/block/cpu/noncar/memlayout.ld similarity index 100% rename from src/soc/amd/picasso/memlayout.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout.ld diff --git a/src/soc/amd/picasso/memlayout_psp_verstage.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld similarity index 94% rename from src/soc/amd/picasso/memlayout_psp_verstage.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld index ca95cf81bd..aa27bae1d4 100644 --- a/src/soc/amd/picasso/memlayout_psp_verstage.ld +++ b/src/soc/amd/common/block/cpu/noncar/memlayout_psp_verstage.ld @@ -4,6 +4,8 @@ #include #include +/* TODO: Move defines to SoC-specific header file to allow SoC specific values if needed. */ + /* * Start of available space is 0x15000 and this is where the * header for the user app (verstage) must be mapped. diff --git a/src/soc/amd/picasso/memlayout_transfer_buffer.inc b/src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc similarity index 100% rename from src/soc/amd/picasso/memlayout_transfer_buffer.inc rename to src/soc/amd/common/block/cpu/noncar/memlayout_transfer_buffer.inc diff --git a/src/soc/amd/picasso/memlayout_x86.ld b/src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld similarity index 100% rename from src/soc/amd/picasso/memlayout_x86.ld rename to src/soc/amd/common/block/cpu/noncar/memlayout_x86.ld diff --git a/src/soc/amd/picasso/Kconfig b/src/soc/amd/picasso/Kconfig index 4d7d2a6c1a..6fa36641cd 100644 --- a/src/soc/amd/picasso/Kconfig +++ b/src/soc/amd/picasso/Kconfig @@ -29,6 +29,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_SYNC_LFENCE select UDELAY_TSC select SOC_AMD_COMMON + select SOC_AMD_COMMON_BLOCK_NONCAR select SOC_AMD_COMMON_BLOCK_HAS_ESPI select SOC_AMD_COMMON_BLOCK_IOMMU select SOC_AMD_COMMON_BLOCK_ACPIMMIO @@ -57,10 +58,6 @@ config CPU_SPECIFIC_OPTIONS select SUPPORT_CPU_UCODE_IN_CBFS select ACPI_NO_SMI_GNVS -config MEMLAYOUT_LD_FILE - string - default "src/soc/amd/picasso/memlayout.ld" - config EARLY_RESERVED_DRAM_BASE hex default 0x2000000 From d029a579badd2e71e87b84f66e5fbe87c1651bee Mon Sep 17 00:00:00 2001 From: Kevin Chiu Date: Tue, 3 Nov 2020 15:28:22 +0800 Subject: [PATCH 020/107] mb/google/zork: update berknip CHTC thermal setting Update APU CHTC thermal temperature protection point: Temperature limit(C'): 90 Update system config=2 to meet TDP 15W design. BUG=b:162377903 BRANCH=zork TEST=1. emerge-zork coreboot 2. check CHTC temperature by AMD utility Change-Id: I03245a824d838c2d9468ae0fa3cfa34389560e9d Signed-off-by: Kevin Chiu Reviewed-on: https://review.coreboot.org/c/coreboot/+/47158 Tested-by: build bot (Jenkins) Reviewed-by: Felix Held --- src/mainboard/google/zork/variants/berknip/overridetree.cb | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/zork/variants/berknip/overridetree.cb b/src/mainboard/google/zork/variants/berknip/overridetree.cb index 602b5c79de..f563419b29 100644 --- a/src/mainboard/google/zork/variants/berknip/overridetree.cb +++ b/src/mainboard/google/zork/variants/berknip/overridetree.cb @@ -6,7 +6,7 @@ chip soc/amd/picasso # For the below fields, 0 indicates use SOC default # System config index - register "system_config" = "3" + register "system_config" = "2" # Set STAPM confiuration. All of these fields must be set >0 to take affect register "slow_ppt_limit_mW" = "20000" @@ -14,6 +14,7 @@ chip soc/amd/picasso register "slow_ppt_time_constant_s" = "5" register "stapm_time_constant_s" = "200" register "sustained_power_limit_mW" = "12000" + register "thermctl_limit_degreeC" = "90" register "telemetry_vddcr_vdd_slope_mA" = "65599" register "telemetry_vddcr_vdd_offset" = "0" From 59996e03774e5430bd94a8a0eb51a927a1ef4eb1 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 14 Nov 2020 16:34:35 +0100 Subject: [PATCH 021/107] nb/intel/sandybridge: Use one sequence for write leveling In order to run a write leveling test, one needs to unset the Qoff bit in MR1, then run the test, and finally set Qoff again. The current IOSAV sequence uses two subsequences to perform the test, while the other two are unused. It is possible to perform the two necessary MR1 updates in the same sequence, which can potentially improve runtime (not measured). Since `write_mrreg` is no longer used, it is necessary to handle address mirroring explicitly. This can be accomplished with the recently-added `ddr3_mirror_mrreg` function, which is also used in `write_mrreg`. Tested on Asus P8H61-M PRO, still boots. Change-Id: I65ca1aa32cdb177d2a9e27c3b02e74ac0c882794 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47614 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../intel/sandybridge/raminit_common.c | 56 ++++++++++++++++--- 1 file changed, 48 insertions(+), 8 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 885689c94f..92d0c4f47d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1696,14 +1696,39 @@ static void precharge(ramctr_timing *ctrl) static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) { - /* enable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 7); + /* First DQS/DQS# rising edge after write leveling mode is programmed */ + const u32 tWLMRD = 40; + + u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; + int bank = 1; + + if (ctrl->rank_mirror[channel][slotrank]) + ddr3_mirror_mrreg(&bank, &mr1reg); wait_for_iosav(channel); const struct iosav_ssq sequence[] = { - /* DRAM command NOP */ + /* DRAM command MRS: enable DQs on this slotrank */ [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = tWLMRD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = mr1reg, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + }, + /* DRAM command NOP */ + [1] = { .sp_cmd_ctrl = { .command = IOSAV_NOP, .ranksel_ap = 1, @@ -1722,7 +1747,7 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) }, }, /* DRAM command NOP */ - [1] = { + [2] = { .sp_cmd_ctrl = { .command = IOSAV_NOP_ALT, .ranksel_ap = 1, @@ -1740,6 +1765,25 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) .rank = slotrank, }, }, + /* DRAM command MRS: disable DQs on this slotrank */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = mr1reg | 1 << 12, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + }, }; iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); @@ -1747,10 +1791,6 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) iosav_run_once(channel); wait_for_iosav(channel); - - /* disable DQs on this slotrank */ - write_mrreg(ctrl, channel, slotrank, 1, - make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); } static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) From 593f4ca10b8ce8e859b9ec23412154bce8850e63 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Wed, 11 Nov 2020 19:55:51 +0100 Subject: [PATCH 022/107] nb/intel/sandybridge: Clean up TC_OTHP writes ODT stretch is configured for both slots in `dram_odt_stretch`. Also drop an unjustified OR, which is setting ODT stretch for one slot. Tested on Asus P8H61-M PRO, still boots. Change-Id: I3a9076afec96e33cfdd12f9b78ca4101b3776dab Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47490 Reviewed-by: Frans Hendriks Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/northbridge/intel/sandybridge/raminit_common.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 92d0c4f47d..a48a84f58b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -142,7 +142,7 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) void dram_timing_regs(ramctr_timing *ctrl) { - u32 reg, addr, val32; + u32 reg, val32; int channel; FOR_ALL_CHANNELS { @@ -169,14 +169,13 @@ void dram_timing_regs(ramctr_timing *ctrl) MCHBAR32(TC_RAP_ch(channel)) = reg; /* Other parameters */ - addr = TC_OTHP_ch(channel); reg = 0; reg |= (ctrl->tXPDLL << 0); reg |= (ctrl->tXP << 5); reg |= (ctrl->tAONPD << 8); reg |= 0xa0000; - printram("OTHP [%x] = %x\n", addr, reg); - MCHBAR32(addr) = reg; + printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), reg); + MCHBAR32(TC_OTHP_ch(channel)) = reg; /* Debug parameters - only applies to Ivy Bridge */ if (IS_IVY_CPU(ctrl->cpu)) { @@ -195,8 +194,6 @@ void dram_timing_regs(ramctr_timing *ctrl) MCHBAR32(TC_DTP_ch(channel)) = reg; } - MCHBAR32_OR(addr, 0x00020000); - dram_odt_stretch(ctrl, channel); /* From 7a612749434f2d8577606db52cf750d374a61adb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 12 Nov 2020 13:34:03 +0100 Subject: [PATCH 023/107] nb/intel/sandybridge: Use bitfields to program MCMAIN timings Tested on Asus P8H61-M PRO, still boots. Change-Id: I9a996de5d596cdb541c8b327f119425243724007 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47512 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 187 ++++++++++-------- .../intel/sandybridge/raminit_common.h | 102 ++++++++++ 2 files changed, 210 insertions(+), 79 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index a48a84f58b..c8757e4e05 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -135,63 +135,67 @@ static void dram_odt_stretch(ramctr_timing *ctrl, int channel) printk(RAM_DEBUG, "OTHP Workaround [%x] = %x\n", addr, MCHBAR32(addr)); } else { addr = TC_OTHP_ch(channel); - MCHBAR32_AND_OR(addr, ~(0xf << 16), (stretch << 16) | (stretch << 18)); + union tc_othp_reg tc_othp = { + .raw = MCHBAR32(addr), + }; + tc_othp.odt_delay_d0 = stretch; + tc_othp.odt_delay_d1 = stretch; + MCHBAR32(addr) = tc_othp.raw; printk(RAM_DEBUG, "OTHP [%x] = %x\n", addr, MCHBAR32(addr)); } } void dram_timing_regs(ramctr_timing *ctrl) { - u32 reg, val32; int channel; FOR_ALL_CHANNELS { /* BIN parameters */ - reg = 0; - reg |= (ctrl->tRCD << 0); - reg |= (ctrl->tRP << 4); - reg |= (ctrl->CAS << 8); - reg |= (ctrl->CWL << 12); - reg |= (ctrl->tRAS << 16); - printram("DBP [%x] = %x\n", TC_DBP_ch(channel), reg); - MCHBAR32(TC_DBP_ch(channel)) = reg; + const union tc_dbp_reg tc_dbp = { + .tRCD = ctrl->tRCD, + .tRP = ctrl->tRP, + .tAA = ctrl->CAS, + .tCWL = ctrl->CWL, + .tRAS = ctrl->tRAS, + }; + printram("DBP [%x] = %x\n", TC_DBP_ch(channel), tc_dbp.raw); + MCHBAR32(TC_DBP_ch(channel)) = tc_dbp.raw; /* Regular access parameters */ - reg = 0; - reg |= (ctrl->tRRD << 0); - reg |= (ctrl->tRTP << 4); - reg |= (ctrl->tCKE << 8); - reg |= (ctrl->tWTR << 12); - reg |= (ctrl->tFAW << 16); - reg |= (ctrl->tWR << 24); - reg |= (3 << 30); - printram("RAP [%x] = %x\n", TC_RAP_ch(channel), reg); - MCHBAR32(TC_RAP_ch(channel)) = reg; + const union tc_rap_reg tc_rap = { + .tRRD = ctrl->tRRD, + .tRTP = ctrl->tRTP, + .tCKE = ctrl->tCKE, + .tWTR = ctrl->tWTR, + .tFAW = ctrl->tFAW, + .tWR = ctrl->tWR, + .tCMD = 3, + }; + printram("RAP [%x] = %x\n", TC_RAP_ch(channel), tc_rap.raw); + MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; /* Other parameters */ - reg = 0; - reg |= (ctrl->tXPDLL << 0); - reg |= (ctrl->tXP << 5); - reg |= (ctrl->tAONPD << 8); - reg |= 0xa0000; - printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), reg); - MCHBAR32(TC_OTHP_ch(channel)) = reg; + const union tc_othp_reg tc_othp = { + .tXPDLL = ctrl->tXPDLL, + .tXP = ctrl->tXP, + .tAONPD = ctrl->tAONPD, + .tCPDED = 2, + .tPRPDEN = 2, + }; + printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), tc_othp.raw); + MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; /* Debug parameters - only applies to Ivy Bridge */ if (IS_IVY_CPU(ctrl->cpu)) { - reg = 0; - /* * If tXP and tXPDLL are very high, we need to increase them by one. * This can only happen on Ivy Bridge, and when overclocking the RAM. */ - if (ctrl->tXP >= 8) - reg |= (1 << 12); - - if (ctrl->tXPDLL >= 32) - reg |= (1 << 13); - - MCHBAR32(TC_DTP_ch(channel)) = reg; + const union tc_dtp_reg tc_dtp = { + .overclock_tXP = ctrl->tXP >= 8, + .overclock_tXPDLL = ctrl->tXPDLL >= 32, + }; + MCHBAR32(TC_DTP_ch(channel)) = tc_dtp.raw; } dram_odt_stretch(ctrl, channel); @@ -201,28 +205,31 @@ void dram_timing_regs(ramctr_timing *ctrl) * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. */ - val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); + const u32 val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); - reg = ((ctrl->tREFI & 0xffff) << 0) | - ((ctrl->tRFC & 0x01ff) << 16) | (((val32 / 1024) & 0x7f) << 25); + const union tc_rftp_reg tc_rftp = { + .tREFI = ctrl->tREFI, + .tRFC = ctrl->tRFC, + .tREFIx9 = val32 / 1024, + }; + printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), tc_rftp.raw); + MCHBAR32(TC_RFTP_ch(channel)) = tc_rftp.raw; - printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), reg); - MCHBAR32(TC_RFTP_ch(channel)) = reg; - - MCHBAR32_OR(TC_RFP_ch(channel), 0xff); + union tc_rfp_reg tc_rfp = { + .raw = MCHBAR32(TC_RFP_ch(channel)), + }; + tc_rfp.oref_ri = 0xff; + MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; /* Self-refresh timing parameters */ - reg = 0; - val32 = tDLLK; - reg = (reg & ~0x00000fff) | (val32 << 0); - val32 = ctrl->tXSOffset; - reg = (reg & ~0x0000f000) | (val32 << 12); - val32 = tDLLK - ctrl->tXSOffset; - reg = (reg & ~0x03ff0000) | (val32 << 16); - val32 = ctrl->tMOD - 8; - reg = (reg & ~0xf0000000) | (val32 << 28); - printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), reg); - MCHBAR32(TC_SRFTP_ch(channel)) = reg; + const union tc_srftp_reg tc_srftp = { + .tXSDLL = tDLLK, + .tXS_offset = ctrl->tXSOffset, + .tZQOPER = tDLLK - ctrl->tXSOffset, + .tMOD = ctrl->tMOD - 8, + }; + printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), tc_srftp.raw); + MCHBAR32(TC_SRFTP_ch(channel)) = tc_srftp.raw; } } @@ -2215,14 +2222,16 @@ static int try_cmd_stretch(ramctr_timing *ctrl, int channel, int cmd_stretch) ctrl->cmd_stretch[channel] = cmd_stretch; - MCHBAR32(TC_RAP_ch(channel)) = - (ctrl->tRRD << 0) - | (ctrl->tRTP << 4) - | (ctrl->tCKE << 8) - | (ctrl->tWTR << 12) - | (ctrl->tFAW << 16) - | (ctrl->tWR << 24) - | (ctrl->cmd_stretch[channel] << 30); + const union tc_rap_reg tc_rap = { + .tRRD = ctrl->tRRD, + .tRTP = ctrl->tRTP, + .tCKE = ctrl->tCKE, + .tWTR = ctrl->tWTR, + .tFAW = ctrl->tFAW, + .tWR = ctrl->tWR, + .tCMD = ctrl->cmd_stretch[channel], + }; + MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; if (ctrl->cmd_stretch[channel] == 2) delta = 2; @@ -2980,7 +2989,6 @@ void set_read_write_timings(ramctr_timing *ctrl) int channel, slotrank; FOR_ALL_POPULATED_CHANNELS { - u32 b20, b4_8_12; int min_pi = 10000; int max_pi = -10000; @@ -2989,14 +2997,23 @@ void set_read_write_timings(ramctr_timing *ctrl) min_pi = MIN(ctrl->timings[channel][slotrank].pi_coding, min_pi); } - b20 = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; + const u32 tWRDRDD = (max_pi - min_pi > 51) ? 0 : ctrl->ref_card_offset[channel]; - b4_8_12 = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 0x3330 : 0x2220; + const u32 val = (ctrl->pi_coding_threshold < max_pi - min_pi) ? 3 : 2; dram_odt_stretch(ctrl, channel); - MCHBAR32(TC_RWP_ch(channel)) = (1 << 27) | (2 << 24) | (b20 << 20) | - ((ctrl->ref_card_offset[channel] + 2) << 16) | b4_8_12; + const union tc_rwp_reg tc_rwp = { + .tRRDR = 0, + .tRRDD = val, + .tWWDR = val, + .tWWDD = val, + .tRWDRDD = ctrl->ref_card_offset[channel] + 2, + .tWRDRDD = tWRDRDD, + .tRWSR = 2, + .dec_wrd = 1, + }; + MCHBAR32(TC_RWP_ch(channel)) = tc_rwp.raw; } } @@ -3028,8 +3045,13 @@ void final_registers(ramctr_timing *ctrl) /* FIXME: This register only exists on Ivy Bridge */ MCHBAR32(WMM_READ_CONFIG) = 0x46; - FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_OTHP_ch(channel), ~(3 << 12), 1 << 12); + FOR_ALL_CHANNELS { + union tc_othp_reg tc_othp = { + .raw = MCHBAR32(TC_OTHP_ch(channel)), + }; + tc_othp.tCPDED = 1; + MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; + } if (is_mobile) /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ @@ -3067,8 +3089,13 @@ void final_registers(ramctr_timing *ctrl) MCHBAR32_AND_OR(MEM_TRML_THRESHOLDS_CONFIG, ~0x00ffffff, 0x00e4d5d0); MCHBAR32_AND(MEM_TRML_INTERRUPT, ~0x1f); - FOR_ALL_CHANNELS - MCHBAR32_AND_OR(TC_RFP_ch(channel), ~(3 << 16), 1 << 16); + FOR_ALL_CHANNELS { + union tc_rfp_reg tc_rfp = { + .raw = MCHBAR32(TC_RFP_ch(channel)), + }; + tc_rfp.refresh_2x_control = 1; + MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; + } MCHBAR32_OR(MC_INIT_STATE_G, 1 << 0); MCHBAR32_OR(MC_INIT_STATE_G, 1 << 7); @@ -3107,14 +3134,16 @@ void restore_timings(ramctr_timing *ctrl) int channel, lane; FOR_ALL_POPULATED_CHANNELS { - MCHBAR32(TC_RAP_ch(channel)) = - (ctrl->tRRD << 0) - | (ctrl->tRTP << 4) - | (ctrl->tCKE << 8) - | (ctrl->tWTR << 12) - | (ctrl->tFAW << 16) - | (ctrl->tWR << 24) - | (ctrl->cmd_stretch[channel] << 30); + const union tc_rap_reg tc_rap = { + .tRRD = ctrl->tRRD, + .tRTP = ctrl->tRTP, + .tCKE = ctrl->tCKE, + .tWTR = ctrl->tWTR, + .tFAW = ctrl->tFAW, + .tWR = ctrl->tWR, + .tCMD = ctrl->cmd_stretch[channel], + }; + MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; } udelay(1); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 80693bb30e..0aa687da70 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -98,6 +98,108 @@ struct iosav_ssq { } addr_update; }; +union tc_dbp_reg { + struct { + u32 tRCD : 4; /* [ 3.. 0] */ + u32 tRP : 4; /* [ 7.. 4] */ + u32 tAA : 4; /* [11.. 8] */ + u32 tCWL : 4; /* [15..12] */ + u32 tRAS : 8; /* [23..16] */ + u32 : 8; + }; + u32 raw; +}; + +union tc_rap_reg { + struct { + u32 tRRD : 4; /* [ 3.. 0] */ + u32 tRTP : 4; /* [ 7.. 4] */ + u32 tCKE : 4; /* [11.. 8] */ + u32 tWTR : 4; /* [15..12] */ + u32 tFAW : 8; /* [23..16] */ + u32 tWR : 5; /* [28..24] */ + u32 dis_3st : 1; /* [29..29] */ + u32 tCMD : 2; /* [31..30] */ + }; + u32 raw; +}; + +union tc_rwp_reg { + struct { + u32 tRRDR : 3; /* [ 2.. 0] */ + u32 : 1; + u32 tRRDD : 3; /* [ 6.. 4] */ + u32 : 1; + u32 tWWDR : 3; /* [10.. 8] */ + u32 : 1; + u32 tWWDD : 3; /* [14..12] */ + u32 : 1; + u32 tRWDRDD : 3; /* [18..16] */ + u32 : 1; + u32 tWRDRDD : 3; /* [22..20] */ + u32 : 1; + u32 tRWSR : 3; /* [26..24] */ + u32 dec_wrd : 1; /* [27..27] */ + u32 : 4; + }; + u32 raw; +}; + +union tc_othp_reg { + struct { + u32 tXPDLL : 5; /* [ 4.. 0] */ + u32 tXP : 3; /* [ 7.. 5] */ + u32 tAONPD : 4; /* [11.. 8] */ + u32 tCPDED : 2; /* [13..12] */ + u32 tPRPDEN : 2; /* [15..14] */ + u32 odt_delay_d0 : 2; /* [17..16] */ + u32 odt_delay_d1 : 2; /* [19..18] */ + u32 : 12; + }; + u32 raw; +}; + +union tc_dtp_reg { + struct { + u32 : 12; + u32 overclock_tXP : 1; /* [12..12] */ + u32 overclock_tXPDLL : 1; /* [13..13] */ + u32 : 18; + }; + u32 raw; +}; + +union tc_rfp_reg { + struct { + u32 oref_ri : 8; /* [ 7.. 0] */ + u32 refresh_high_wm : 4; /* [11.. 8] */ + u32 refresh_panic_wm : 4; /* [15..12] */ + u32 refresh_2x_control : 2; /* [17..16] */ + u32 : 14; + }; + u32 raw; +}; + +union tc_rftp_reg { + struct { + u32 tREFI : 16; /* [15.. 0] */ + u32 tRFC : 9; /* [24..16] */ + u32 tREFIx9 : 7; /* [31..25] */ + }; + u32 raw; +}; + +union tc_srftp_reg { + struct { + u32 tXSDLL : 12; /* [11.. 0] */ + u32 tXS_offset : 4; /* [15..12] */ + u32 tZQOPER : 10; /* [25..16] */ + u32 : 2; + u32 tMOD : 4; /* [31..28] */ + }; + u32 raw; +}; + typedef struct ramctr_timing_st ramctr_timing; void iosav_write_sequence(const int ch, const struct iosav_ssq *seq, const unsigned int length); From 8137806326a22fcff2a2029245e415117df77c38 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 12 Nov 2020 13:46:21 +0100 Subject: [PATCH 024/107] nb/intel/sandybridge: Move constants out of for-loop Most per-channel registers are programmed with the same values. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ifddff3043b68113058859cef08625b90012ca424 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47513 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 114 +++++++++--------- 1 file changed, 60 insertions(+), 54 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c8757e4e05..d18e302de0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -149,69 +149,82 @@ void dram_timing_regs(ramctr_timing *ctrl) { int channel; + /* BIN parameters */ + const union tc_dbp_reg tc_dbp = { + .tRCD = ctrl->tRCD, + .tRP = ctrl->tRP, + .tAA = ctrl->CAS, + .tCWL = ctrl->CWL, + .tRAS = ctrl->tRAS, + }; + + /* Regular access parameters */ + const union tc_rap_reg tc_rap = { + .tRRD = ctrl->tRRD, + .tRTP = ctrl->tRTP, + .tCKE = ctrl->tCKE, + .tWTR = ctrl->tWTR, + .tFAW = ctrl->tFAW, + .tWR = ctrl->tWR, + .tCMD = 3, + }; + + /* Other parameters */ + const union tc_othp_reg tc_othp = { + .tXPDLL = ctrl->tXPDLL, + .tXP = ctrl->tXP, + .tAONPD = ctrl->tAONPD, + .tCPDED = 2, + .tPRPDEN = 2, + }; + + /* + * If tXP and tXPDLL are very high, we need to increase them by one. + * This can only happen on Ivy Bridge, and when overclocking the RAM. + */ + const union tc_dtp_reg tc_dtp = { + .overclock_tXP = ctrl->tXP >= 8, + .overclock_tXPDLL = ctrl->tXPDLL >= 32, + }; + + /* + * TC-Refresh timing parameters: + * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow + * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. + */ + const u32 val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); + + const union tc_rftp_reg tc_rftp = { + .tREFI = ctrl->tREFI, + .tRFC = ctrl->tRFC, + .tREFIx9 = val32 / 1024, + }; + + /* Self-refresh timing parameters */ + const union tc_srftp_reg tc_srftp = { + .tXSDLL = tDLLK, + .tXS_offset = ctrl->tXSOffset, + .tZQOPER = tDLLK - ctrl->tXSOffset, + .tMOD = ctrl->tMOD - 8, + }; + FOR_ALL_CHANNELS { - /* BIN parameters */ - const union tc_dbp_reg tc_dbp = { - .tRCD = ctrl->tRCD, - .tRP = ctrl->tRP, - .tAA = ctrl->CAS, - .tCWL = ctrl->CWL, - .tRAS = ctrl->tRAS, - }; printram("DBP [%x] = %x\n", TC_DBP_ch(channel), tc_dbp.raw); MCHBAR32(TC_DBP_ch(channel)) = tc_dbp.raw; - /* Regular access parameters */ - const union tc_rap_reg tc_rap = { - .tRRD = ctrl->tRRD, - .tRTP = ctrl->tRTP, - .tCKE = ctrl->tCKE, - .tWTR = ctrl->tWTR, - .tFAW = ctrl->tFAW, - .tWR = ctrl->tWR, - .tCMD = 3, - }; printram("RAP [%x] = %x\n", TC_RAP_ch(channel), tc_rap.raw); MCHBAR32(TC_RAP_ch(channel)) = tc_rap.raw; - /* Other parameters */ - const union tc_othp_reg tc_othp = { - .tXPDLL = ctrl->tXPDLL, - .tXP = ctrl->tXP, - .tAONPD = ctrl->tAONPD, - .tCPDED = 2, - .tPRPDEN = 2, - }; printram("OTHP [%x] = %x\n", TC_OTHP_ch(channel), tc_othp.raw); MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; - /* Debug parameters - only applies to Ivy Bridge */ if (IS_IVY_CPU(ctrl->cpu)) { - /* - * If tXP and tXPDLL are very high, we need to increase them by one. - * This can only happen on Ivy Bridge, and when overclocking the RAM. - */ - const union tc_dtp_reg tc_dtp = { - .overclock_tXP = ctrl->tXP >= 8, - .overclock_tXPDLL = ctrl->tXPDLL >= 32, - }; + /* Debug parameters - only applies to Ivy Bridge */ MCHBAR32(TC_DTP_ch(channel)) = tc_dtp.raw; } dram_odt_stretch(ctrl, channel); - /* - * TC-Refresh timing parameters: - * The tREFIx9 field should be programmed to minimum of 8.9 * tREFI (to allow - * for possible delays from ZQ or isoc) and tRASmax (70us) divided by 1024. - */ - const u32 val32 = MIN((ctrl->tREFI * 89) / 10, (70000 << 8) / ctrl->tCK); - - const union tc_rftp_reg tc_rftp = { - .tREFI = ctrl->tREFI, - .tRFC = ctrl->tRFC, - .tREFIx9 = val32 / 1024, - }; printram("REFI [%x] = %x\n", TC_RFTP_ch(channel), tc_rftp.raw); MCHBAR32(TC_RFTP_ch(channel)) = tc_rftp.raw; @@ -221,13 +234,6 @@ void dram_timing_regs(ramctr_timing *ctrl) tc_rfp.oref_ri = 0xff; MCHBAR32(TC_RFP_ch(channel)) = tc_rfp.raw; - /* Self-refresh timing parameters */ - const union tc_srftp_reg tc_srftp = { - .tXSDLL = tDLLK, - .tXS_offset = ctrl->tXSOffset, - .tZQOPER = tDLLK - ctrl->tXSOffset, - .tMOD = ctrl->tMOD - 8, - }; printram("SRFTP [%x] = %x\n", TC_SRFTP_ch(channel), tc_srftp.raw); MCHBAR32(TC_SRFTP_ch(channel)) = tc_srftp.raw; } From 737f111d2c5b981b3fe9bca03105fb79ceea1e81 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 13 Nov 2020 14:07:30 +0100 Subject: [PATCH 025/107] nb/intel/sandybridge: Use bitfield for GDCRCMDPICODING This register's layout makes no sense, so use bitfields for clarity. Tested on Asus P8H61-M PRO, still boots. Change-Id: I61efc7349badc2c3297c9b71535dceecaba509d0 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47571 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 19 ++++++++++++------- .../intel/sandybridge/raminit_common.h | 19 +++++++++++++++++++ 2 files changed, 31 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d18e302de0..60f9e1fdd6 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -917,7 +917,7 @@ static const u32 lane_base[] = { void program_timings(ramctr_timing *ctrl, int channel) { - u32 reg32, reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; + u32 reg_roundtrip_latency, reg_pi_code, reg_logic_delay, reg_io_latency; int lane; int slotrank, slot; int full_shift = 0; @@ -950,13 +950,18 @@ void program_timings(ramctr_timing *ctrl, int channel) } /* Enable CMD XOVER */ - reg32 = get_XOVER_CMD(ctrl->rankmap[channel]); - reg32 |= (pi_coding_ctrl[0] & 0x3f) << 6; - reg32 |= (pi_coding_ctrl[0] & 0x40) << 9; - reg32 |= (pi_coding_ctrl[1] & 0x7f) << 18; - reg32 |= (full_shift & 0x3f) | ((full_shift & 0x40) << 6); + union gdcr_cmd_pi_coding_reg cmd_pi_coding = { + .raw = get_XOVER_CMD(ctrl->rankmap[channel]), + }; + cmd_pi_coding.cmd_pi_code = full_shift & 0x3f; + cmd_pi_coding.cmd_logic_delay = !!(full_shift & 0x40); - MCHBAR32(GDCRCMDPICODING_ch(channel)) = reg32; + cmd_pi_coding.ctl_pi_code_d0 = pi_coding_ctrl[0] & 0x3f; + cmd_pi_coding.ctl_pi_code_d1 = pi_coding_ctrl[1] & 0x3f; + cmd_pi_coding.ctl_logic_delay_d0 = !!(pi_coding_ctrl[0] & 0x40); + cmd_pi_coding.ctl_logic_delay_d1 = !!(pi_coding_ctrl[1] & 0x40); + + MCHBAR32(GDCRCMDPICODING_ch(channel)) = cmd_pi_coding.raw; /* Enable CLK XOVER */ reg_pi_code = get_XOVER_CLK(ctrl->rankmap[channel]); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 0aa687da70..798b4828e5 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -98,6 +98,25 @@ struct iosav_ssq { } addr_update; }; +union gdcr_cmd_pi_coding_reg { + struct { + u32 cmd_pi_code : 6; /* [ 5.. 0] */ + u32 ctl_pi_code_d0 : 6; /* [11.. 6] */ + u32 cmd_logic_delay : 1; /* [12..12] */ + u32 cmd_phase_delay : 1; /* [13..13] */ + u32 cmd_xover_enable : 1; /* [14..14] */ + u32 ctl_logic_delay_d0 : 1; /* [15..15] */ + u32 ctl_phase_delay_d0 : 1; /* [16..16] */ + u32 ctl_xover_enable_d0 : 1; /* [17..17] */ + u32 ctl_pi_code_d1 : 6; /* [23..18] */ + u32 ctl_logic_delay_d1 : 1; /* [24..24] */ + u32 ctl_phase_delay_d1 : 1; /* [25..25] */ + u32 ctl_xover_enable_d1 : 1; /* [26..26] */ + u32 : 5; + }; + u32 raw; +}; + union tc_dbp_reg { struct { u32 tRCD : 4; /* [ 3.. 0] */ From 58b609bf30b98a2fe63d1aac17923359c7d11157 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 13 Nov 2020 14:35:29 +0100 Subject: [PATCH 026/107] nb/intel/sandybridge: Use bitfield for GDCRTRAININGMOD register Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie4b5777dd3789d4cd818ee66bdf3074ad055c818 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47572 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../intel/sandybridge/raminit_common.c | 38 ++++++++++++++++--- .../intel/sandybridge/raminit_common.h | 23 +++++++++++ 2 files changed, 55 insertions(+), 6 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 60f9e1fdd6..5aaafdd9f1 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1351,7 +1351,12 @@ int read_training(ramctr_timing *ctrl) /* Execute command queue */ iosav_run_once(channel); - MCHBAR32(GDCRTRAININGMOD) = (slotrank << 2) | 0x8001; + const union gdcr_training_mod_reg training_mod = { + .receive_enable_mode = 1, + .training_rank_sel = slotrank, + .odt_always_on = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; ctrl->timings[channel][slotrank].io_latency = 4; ctrl->timings[channel][slotrank].roundtrip_latency = 55; @@ -1814,7 +1819,14 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) int statistics[NUM_LANES][128]; int lane; - MCHBAR32(GDCRTRAININGMOD) = 0x108052 | (slotrank << 2); + const union gdcr_training_mod_reg training_mod = { + .write_leveling_mode = 1, + .training_rank_sel = slotrank, + .enable_dqs_wl = 5, + .odt_always_on = 1, + .force_drive_enable = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { @@ -1884,7 +1896,12 @@ static int get_timB_high_adjust(u64 val) static void train_write_flyby(ramctr_timing *ctrl) { int channel, slotrank, lane, old; - MCHBAR32(GDCRTRAININGMOD) = 0x200; + + const union gdcr_training_mod_reg training_mod = { + .dq_dqs_training_res = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + FOR_ALL_POPULATED_CHANNELS { fill_pattern1(ctrl, channel); } @@ -2046,7 +2063,13 @@ int write_training(ramctr_timing *ctrl) write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); - MCHBAR32(GDCRTRAININGMOD) = 0x108052; + const union gdcr_training_mod_reg training_mod = { + .write_leveling_mode = 1, + .enable_dqs_wl = 5, + .odt_always_on = 1, + .force_drive_enable = 1, + }; + MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; toggle_io_reset(); @@ -2522,8 +2545,11 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr } for (i = 0; i < 3; i++) { - MCHBAR32(GDCRTRAININGMOD_ch(channel)) = reg3000b24[i] << 24; - printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), reg3000b24[i] << 24); + const union gdcr_training_mod_reg training_mod = { + .vref_gen_ctl = reg3000b24[i], + }; + MCHBAR32(GDCRTRAININGMOD_ch(channel)) = training_mod.raw; + printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), training_mod.raw); for (pat = 0; pat < NUM_PATTERNS; pat++) { fill_pattern5(ctrl, channel, pat); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 798b4828e5..4a7e8065c2 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -117,6 +117,29 @@ union gdcr_cmd_pi_coding_reg { u32 raw; }; +union gdcr_training_mod_reg { + struct { + u32 receive_enable_mode : 1; /* [ 0.. 0] */ + u32 write_leveling_mode : 1; /* [ 1.. 1] */ + u32 training_rank_sel : 2; /* [ 3.. 2] */ + u32 enable_dqs_wl : 4; /* [ 7.. 4] */ + u32 dqs_logic_delay_wl : 1; /* [ 8.. 8] */ + u32 dq_dqs_training_res : 1; /* [ 9.. 9] */ + u32 : 4; + u32 delay_dq : 1; /* [14..14] */ + u32 odt_always_on : 1; /* [15..15] */ + u32 : 4; + u32 force_drive_enable : 1; /* [20..20] */ + u32 dft_tx_pi_clk_view : 1; /* [21..21] */ + u32 dft_tx_pi_clk_swap : 1; /* [22..22] */ + u32 early_odt_en : 1; /* [23..23] */ + u32 vref_gen_ctl : 6; /* [29..24] */ + u32 ext_vref_sel : 1; /* [30..30] */ + u32 tx_fifo_always_on : 1; /* [31..31] */ + }; + u32 raw; +}; + union tc_dbp_reg { struct { u32 tRCD : 4; /* [ 3.. 0] */ From 7f5a97ce98120561dff449cbbf9f953bd9b6d623 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 13 Nov 2020 16:58:46 +0100 Subject: [PATCH 027/107] nb/intel/sandybridge: Rename `read_training` function Given that it sets the receive enable mode bit in the GDCRTRAININGMOD register, it's clear that this is about receive enable calibration. Remove a potentially-outdated comment. Proper documentation will be written once code refactoring and various improvements are complete. Change-Id: Iaefc8905adf2878bec3b43494dc53530064a9f5d Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47576 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../intel/sandybridge/raminit_common.c | 20 +------------------ .../intel/sandybridge/raminit_common.h | 2 +- .../intel/sandybridge/raminit_native.c | 2 +- 3 files changed, 3 insertions(+), 21 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5aaafdd9f1..5332e24f8b 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1316,25 +1316,7 @@ static void compute_final_logic_delay(ramctr_timing *ctrl, int channel, int slot printram("4028 -= %d;\n", logic_delay_min); } -/* - * Compensate the skew between DQS and DQs. - * - * To ease PCB design, a small skew between Data Strobe signals and Data Signals is allowed. - * The controller has to measure and compensate this skew for every byte-lane. By delaying - * either all DQ signals or DQS signal, a full phase shift can be introduced. It is assumed - * that one byte-lane's DQs signals have the same routing delay. - * - * To measure the actual skew, the DRAM is placed in "read leveling" mode. In read leveling - * mode the DRAM-chip outputs an alternating periodic pattern. The memory controller iterates - * over all possible values to do a full phase shift and issues read commands. With DQS and - * DQ in phase the data being read is expected to alternate on every byte: - * - * 0xFF 0x00 0xFF ... - * - * Once the controller has detected this pattern a bit in the result register is set for the - * current phase shift. - */ -int read_training(ramctr_timing *ctrl) +int receive_enable_calibration(ramctr_timing *ctrl) { int channel, slotrank, lane; int err; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 4a7e8065c2..10dd59d844 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -400,7 +400,7 @@ void dram_dimm_set_mapping(ramctr_timing *ctrl, int training); void dram_zones(ramctr_timing *ctrl, int training); void dram_memorymap(ramctr_timing *ctrl, int me_uma_size); void dram_jedecreset(ramctr_timing *ctrl); -int read_training(ramctr_timing *ctrl); +int receive_enable_calibration(ramctr_timing *ctrl); int write_training(ramctr_timing *ctrl); int command_training(ramctr_timing *ctrl); int read_mpr_training(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index 454ba011ab..e0b5a3dfc2 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -680,7 +680,7 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ /* Prepare for memory training */ prepare_training(ctrl); - err = read_training(ctrl); + err = receive_enable_calibration(ctrl); if (err) return err; From 068c2595f2a3cc57d73849926f420bd6f63d72f6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 14 Nov 2020 01:31:15 +0100 Subject: [PATCH 028/107] nb/intel/sandybridge: Run `read_mpr_training` before write training Reference code does this, so follow suit. Tested on Asus P8H61-M PRO, still boots. Change-Id: I21c5161da55b380dd4b2d574b22a1ef038f55fce Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47611 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/raminit_native.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index e0b5a3dfc2..ae9a4f46fa 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -684,16 +684,16 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ if (err) return err; + err = read_mpr_training(ctrl); + if (err) + return err; + err = write_training(ctrl); if (err) return err; printram("CP5a\n"); - err = read_mpr_training(ctrl); - if (err) - return err; - printram("CP5b\n"); err = command_training(ctrl); From 9426721807e0f531ea198ff932b8548d48550780 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 14 Nov 2020 16:49:29 +0100 Subject: [PATCH 029/107] nb/intel/sandybridge: Make helper for write leveling sequence Encapsulate the IOSAV sequence into a helper to help reduce clutter. Tested on Asus P8H61-M PRO, still boots. Change-Id: I58595a5c53fcdc3f29fa55b015a82cbfe85cd6cb Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47615 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 83 +----------------- .../intel/sandybridge/raminit_common.h | 2 + .../intel/sandybridge/raminit_iosav.c | 87 +++++++++++++++++++ 3 files changed, 90 insertions(+), 82 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 5332e24f8b..b9a35f0992 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1698,9 +1698,6 @@ static void precharge(ramctr_timing *ctrl) static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) { - /* First DQS/DQS# rising edge after write leveling mode is programmed */ - const u32 tWLMRD = 40; - u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; int bank = 1; @@ -1709,85 +1706,7 @@ static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); - const struct iosav_ssq sequence[] = { - /* DRAM command MRS: enable DQs on this slotrank */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = tWLMRD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = mr1reg, - .rowbits = 6, - .bank = bank, - .rank = slotrank, - }, - }, - /* DRAM command NOP */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_NOP, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->CWL + ctrl->tWLO, - .data_direction = SSQ_WR, - }, - .sp_cmd_addr = { - .address = 8, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command NOP */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_NOP_ALT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->CAS + 38, - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 4, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - }, - /* DRAM command MRS: disable DQs on this slotrank */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_MRS, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tMOD, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = mr1reg | 1 << 12, - .rowbits = 6, - .bank = bank, - .rank = slotrank, - }, - }, - }; - iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); + iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); /* Execute command queue */ iosav_run_once(channel); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 10dd59d844..c1fb10b207 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -253,6 +253,8 @@ void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); void iosav_write_read_mpr_sequence( int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_jedec_write_leveling_sequence( + ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg); void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2); void iosav_write_command_training_sequence( diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index 11b2acb252..25f5ae705d 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -199,6 +199,93 @@ void iosav_write_read_mpr_sequence( iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } +void iosav_write_jedec_write_leveling_sequence( + ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg) +{ + /* First DQS/DQS# rising edge after write leveling mode is programmed */ + const u32 tWLMRD = 40; + + const struct iosav_ssq sequence[] = { + /* DRAM command MRS: enable DQs on this slotrank */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = tWLMRD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = mr1reg, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + }, + /* DRAM command NOP */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CWL + ctrl->tWLO, + .data_direction = SSQ_WR, + }, + .sp_cmd_addr = { + .address = 8, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }, + /* DRAM command NOP */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_NOP_ALT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->CAS + 38, + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 4, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + }, + /* DRAM command MRS: disable DQs on this slotrank */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_MRS, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tMOD, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = mr1reg | 1 << 12, + .rowbits = 6, + .bank = bank, + .rank = slotrank, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, u32 gap0, u32 loops0, u32 gap1, u32 loops2, u32 wrap2) { From c6d2feaee53cfce3ca54d389b51593fc86e25576 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 14 Nov 2020 16:52:33 +0100 Subject: [PATCH 030/107] nb/intel/sandybridge: Do not rewrite write leveling sequence There's no need to reprogram the exact same sequence over a hundred times. Move it out of the timB loop, and drop the `test_timB` function. Tested on Asus P8H61-M PRO, still boots. Change-Id: I375e325cf8b5369889b9cb059c3675cd00bdbb3f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47616 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 33 ++++++++----------- 1 file changed, 14 insertions(+), 19 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b9a35f0992..57c376b1aa 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1696,24 +1696,6 @@ static void precharge(ramctr_timing *ctrl) } } -static void test_timB(ramctr_timing *ctrl, int channel, int slotrank) -{ - u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; - int bank = 1; - - if (ctrl->rank_mirror[channel][slotrank]) - ddr3_mirror_mrreg(&bank, &mr1reg); - - wait_for_iosav(channel); - - iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); -} - static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) { int timB; @@ -1729,13 +1711,26 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) }; MCHBAR32(GDCRTRAININGMOD) = training_mod.raw; + u32 mr1reg = make_mr1(ctrl, slotrank, channel) | 1 << 7; + int bank = 1; + + if (ctrl->rank_mirror[channel][slotrank]) + ddr3_mirror_mrreg(&bank, &mr1reg); + + wait_for_iosav(channel); + + iosav_write_jedec_write_leveling_sequence(ctrl, channel, slotrank, bank, mr1reg); + for (timB = 0; timB < 128; timB++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane].timB = timB; } program_timings(ctrl, channel); - test_timB(ctrl, channel, slotrank); + /* Execute command queue */ + iosav_run_once(channel); + + wait_for_iosav(channel); FOR_ALL_LANES { statistics[lane][timB] = !((MCHBAR32(lane_base[lane] + From 820bce7322d2af612a39c94c3391b317e33adfb8 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sat, 14 Nov 2020 17:02:55 +0100 Subject: [PATCH 031/107] nb/intel/sandybridge: Encapsulate JEDEC write leveling Create and rename a few functions to contain the entire JEDEC write leveling algorithm. Not all write training is JEDEC write leveling. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie9c6315340164029e30354723b4103d906633602 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47617 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 34 ++++++++++++------- 1 file changed, 22 insertions(+), 12 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 57c376b1aa..ef4ae455f8 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1696,7 +1696,7 @@ static void precharge(ramctr_timing *ctrl) } } -static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) +static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) { int timB; int statistics[NUM_LANES][128]; @@ -1767,14 +1767,12 @@ static int discover_timB(ramctr_timing *ctrl, int channel, int slotrank) return 0; } -static int get_timB_high_adjust(u64 val) +static int get_dqs_flyby_adjust(u64 val) { int i; - /* DQS is good enough */ if (val == 0xffffffffffffffffLL) return 0; - if (val >= 0xf000000000000000LL) { /* DQS is late, needs negative adjustment */ for (i = 0; i < 8; i++) @@ -1889,9 +1887,10 @@ static void train_write_flyby(ramctr_timing *ctrl) u64 res = MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT1(channel)); res |= ((u64) MCHBAR32(lane_base[lane] + GDCRTRAININGRESULT2(channel))) << 32; + old = ctrl->timings[channel][slotrank].lanes[lane].timB; ctrl->timings[channel][slotrank].lanes[lane].timB += - get_timB_high_adjust(res) * 64; + get_dqs_flyby_adjust(res) * 64; printram("High adjust %d:%016llx\n", lane, res); printram("Bval+: %d, %d, %d, %x -> %x\n", channel, slotrank, lane, @@ -1942,13 +1941,9 @@ static void disable_refresh_machine(ramctr_timing *ctrl) * the DRAM-chip samples the CLK on every DQS edge and feeds back the sampled value on the data * lanes (DQ). */ -int write_training(ramctr_timing *ctrl) +static int jedec_write_leveling(ramctr_timing *ctrl) { - int channel, slotrank, lane; - int err; - - FOR_ALL_POPULATED_CHANNELS - MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); + int channel, slotrank; disable_refresh_machine(ctrl); @@ -1971,7 +1966,7 @@ int write_training(ramctr_timing *ctrl) /* Set any valid value for timB, it gets corrected later */ FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_timB(ctrl, channel, slotrank); + const int err = write_level_rank(ctrl, channel, slotrank); if (err) return err; } @@ -2003,6 +1998,21 @@ int write_training(ramctr_timing *ctrl) toggle_io_reset(); + return 0; +} + +int write_training(ramctr_timing *ctrl) +{ + int channel, slotrank, lane; + int err; + + FOR_ALL_POPULATED_CHANNELS + MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); + + err = jedec_write_leveling(ctrl); + if (err) + return err; + printram("CPE\n"); precharge(ctrl); printram("CPF\n"); From a1f1714ca5bcef864d154676b48fc30fa459f8dc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 15 Nov 2020 12:50:03 +0100 Subject: [PATCH 032/107] nb/intel/sandybridge: Clarify register write It is necessary to program this register before doing an I/O reset. Change-Id: Iada74b7ee704f47cc07c71123a62b826d62cfc50 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47619 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/raminit_common.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index ef4ae455f8..0939fe6348 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1954,6 +1954,7 @@ static int jedec_write_leveling(ramctr_timing *ctrl) write_mrreg(ctrl, channel, slotrank, 1, make_mr1(ctrl, slotrank, channel) | 1 << 12 | 1 << 7); + /* Needs to be programmed before I/O reset below */ const union gdcr_training_mod_reg training_mod = { .write_leveling_mode = 1, .enable_dqs_wl = 5, From c39d11cec0505e95e2bcf9e88145f1e35939a4c2 Mon Sep 17 00:00:00 2001 From: Felix Singer Date: Sat, 21 Nov 2020 14:33:15 +0000 Subject: [PATCH 033/107] mb/*: Use ACPI_DSDT_REV_2 instead of hard-coded value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I6c5b86c348386aa17ee42bdaf34aa388fe6207f9 Signed-off-by: Felix Singer Reviewed-on: https://review.coreboot.org/c/coreboot/+/47839 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- src/mainboard/kontron/bsl6/dsdt.asl | 2 +- src/mainboard/siemens/chili/dsdt.asl | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/kontron/bsl6/dsdt.asl b/src/mainboard/kontron/bsl6/dsdt.asl index 225c8a5ec9..3be51152d6 100644 --- a/src/mainboard/kontron/bsl6/dsdt.asl +++ b/src/mainboard/kontron/bsl6/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 diff --git a/src/mainboard/siemens/chili/dsdt.asl b/src/mainboard/siemens/chili/dsdt.asl index 6fd12b15f2..9b49942047 100644 --- a/src/mainboard/siemens/chili/dsdt.asl +++ b/src/mainboard/siemens/chili/dsdt.asl @@ -4,7 +4,7 @@ DefinitionBlock( "dsdt.aml", "DSDT", - 0x02, // DSDT revision: ACPI v2.0 and up + ACPI_DSDT_REV_2, OEM_ID, ACPI_TABLE_CREATOR, 0x20110725 // OEM revision From 4c76d25717048c71533c67cec21085dfc27538f9 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 15 Nov 2020 13:06:53 +0100 Subject: [PATCH 034/107] nb/intel/sandybridge: Drop `precharge` function This is a copy of `find_predefined_pattern` without any effect. Tested on Asus P8H61-M PRO, still boots. Change-Id: Ieb72066ca25b40b6e60f04e6c4097a0ccc2a56b3 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47620 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 49 +------------------ 1 file changed, 2 insertions(+), 47 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 0939fe6348..c41b0f1392 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1651,51 +1651,6 @@ static void fill_pattern1(ramctr_timing *ctrl, int channel) program_wdb_pattern_length(channel, 16); } -static void precharge(ramctr_timing *ctrl) -{ - int channel, slotrank, lane; - - FOR_ALL_POPULATED_CHANNELS { - FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 16; - ctrl->timings[channel][slotrank].lanes[lane].rising = 16; - } - - program_timings(ctrl, channel); - - FOR_ALL_POPULATED_RANKS { - wait_for_iosav(channel); - - iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } - - FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { - ctrl->timings[channel][slotrank].lanes[lane].falling = 48; - ctrl->timings[channel][slotrank].lanes[lane].rising = 48; - } - - program_timings(ctrl, channel); - - FOR_ALL_POPULATED_RANKS { - wait_for_iosav(channel); - - iosav_write_read_mpr_sequence( - channel, slotrank, ctrl->tMOD, 3, 4, 1, ctrl->CAS + 8); - - /* Execute command queue */ - iosav_run_once(channel); - - wait_for_iosav(channel); - } - } -} - static int write_level_rank(ramctr_timing *ctrl, int channel, int slotrank) { int timB; @@ -2010,12 +1965,12 @@ int write_training(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); + printram("CPE\n"); + err = jedec_write_leveling(ctrl); if (err) return err; - printram("CPE\n"); - precharge(ctrl); printram("CPF\n"); FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { From c674223fd419709da2907e8c839131e3250daa25 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 15 Nov 2020 13:26:21 +0100 Subject: [PATCH 035/107] nb/intel/sandybridge: Remove spurious writes to IOSAV BW mask The byte-wise error mask only needs to be set for certain corner cases in read MPR training. Thus, minimize writes to this register. Tested on Asus P8H61-M PRO, still boots. Change-Id: I0bb8d99ad60c4964f896d303878e5982ae1dcdbe Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47621 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 27 +++---------------- 1 file changed, 4 insertions(+), 23 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index c41b0f1392..68281dd582 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1405,9 +1405,7 @@ int receive_enable_calibration(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS { program_timings(ctrl, channel); } - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } + return 0; } @@ -1959,7 +1957,7 @@ static int jedec_write_leveling(ramctr_timing *ctrl) int write_training(ramctr_timing *ctrl) { - int channel, slotrank, lane; + int channel, slotrank; int err; FOR_ALL_POPULATED_CHANNELS @@ -1973,10 +1971,6 @@ int write_training(ramctr_timing *ctrl) printram("CPF\n"); - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } - FOR_ALL_POPULATED_CHANNELS { fill_pattern0(ctrl, channel, 0xaaaaaaaa, 0x55555555); } @@ -1996,9 +1990,6 @@ int write_training(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } return 0; } @@ -2275,6 +2266,7 @@ static void find_predefined_pattern(ramctr_timing *ctrl, const int channel) fill_pattern0(ctrl, channel, 0, 0); FOR_ALL_LANES { + MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; MCHBAR32(IOSAV_By_BW_SERROR_C_ch(channel, lane)); } @@ -2338,10 +2330,6 @@ int read_mpr_training(ramctr_timing *ctrl) toggle_io_reset(); FOR_ALL_POPULATED_CHANNELS { - FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } - find_predefined_pattern(ctrl, channel); fill_pattern0(ctrl, channel, 0, 0xffffffff); @@ -2521,9 +2509,6 @@ int discover_edges_write(ramctr_timing *ctrl) FOR_ALL_POPULATED_CHANNELS program_timings(ctrl, channel); - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } return 0; } @@ -3030,7 +3015,7 @@ void final_registers(ramctr_timing *ctrl) void restore_timings(ramctr_timing *ctrl) { - int channel, lane; + int channel; FOR_ALL_POPULATED_CHANNELS { const union tc_rap_reg tc_rap = { @@ -3051,10 +3036,6 @@ void restore_timings(ramctr_timing *ctrl) wait_for_iosav(channel); } - FOR_ALL_POPULATED_CHANNELS FOR_ALL_LANES { - MCHBAR32(IOSAV_By_BW_MASK_ch(channel, lane)) = 0; - } - FOR_ALL_POPULATED_CHANNELS MCHBAR32_OR(TC_RWP_ch(channel), 1 << 27); From 801a5cbaac21d36042c80b47c9444ea7e48edb1a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Sun, 15 Nov 2020 15:48:29 +0100 Subject: [PATCH 036/107] nb/intel/sandybridge: Relocate PREA-ACT-RD sequence Tested on Asus P8H61-M PRO, still boots. Change-Id: Ie5e243380d940ca89857b230e15091ac01fde928 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47622 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 94 +----------------- .../intel/sandybridge/raminit_common.h | 1 + .../intel/sandybridge/raminit_iosav.c | 97 +++++++++++++++++++ 3 files changed, 99 insertions(+), 93 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 68281dd582..4ba2f0de82 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -1428,99 +1428,7 @@ static void test_tx_dq(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); - const struct iosav_ssq rd_sequence[] = { - /* DRAM command PREA */ - [0] = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }, - /* DRAM command ACT */ - [1] = { - .sp_cmd_ctrl = { - .command = IOSAV_ACT, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 8, - .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), - .post_ssq_wait = ctrl->CAS, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_bank = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command RD */ - [2] = { - .sp_cmd_ctrl = { - .command = IOSAV_RD, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 500, - .cmd_delay_gap = 4, - .post_ssq_wait = MAX(ctrl->tRTP, 8), - .data_direction = SSQ_RD, - }, - .sp_cmd_addr = { - .address = 0, - .rowbits = 0, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .inc_addr_8 = 1, - .addr_wrap = 18, - }, - }, - /* DRAM command PREA */ - [3] = { - .sp_cmd_ctrl = { - .command = IOSAV_PRE, - .ranksel_ap = 1, - }, - .subseq_ctrl = { - .cmd_executions = 1, - .cmd_delay_gap = 3, - .post_ssq_wait = ctrl->tRP, - .data_direction = SSQ_NA, - }, - .sp_cmd_addr = { - .address = 1024, - .rowbits = 6, - .bank = 0, - .rank = slotrank, - }, - .addr_update = { - .addr_wrap = 18, - }, - }, - }; - iosav_write_sequence(channel, rd_sequence, ARRAY_SIZE(rd_sequence)); + iosav_write_prea_act_read_sequence(ctrl, channel, slotrank); /* Execute command queue */ iosav_run_once(channel); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index c1fb10b207..44f4768a95 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -253,6 +253,7 @@ void iosav_write_zqcs_sequence(int channel, int slotrank, u32 gap, u32 post, u32 void iosav_write_prea_sequence(int channel, int slotrank, u32 post, u32 wrap); void iosav_write_read_mpr_sequence( int channel, int slotrank, u32 tMOD, u32 loops, u32 gap, u32 loops2, u32 post2); +void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank); void iosav_write_jedec_write_leveling_sequence( ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg); void iosav_write_misc_write_sequence(ramctr_timing *ctrl, int channel, int slotrank, diff --git a/src/northbridge/intel/sandybridge/raminit_iosav.c b/src/northbridge/intel/sandybridge/raminit_iosav.c index 25f5ae705d..d83dfd8e9a 100644 --- a/src/northbridge/intel/sandybridge/raminit_iosav.c +++ b/src/northbridge/intel/sandybridge/raminit_iosav.c @@ -199,6 +199,103 @@ void iosav_write_read_mpr_sequence( iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); } +void iosav_write_prea_act_read_sequence(ramctr_timing *ctrl, int channel, int slotrank) +{ + const struct iosav_ssq sequence[] = { + /* DRAM command PREA */ + [0] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }, + /* DRAM command ACT */ + [1] = { + .sp_cmd_ctrl = { + .command = IOSAV_ACT, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 8, + .cmd_delay_gap = MAX(ctrl->tRRD, (ctrl->tFAW >> 2) + 1), + .post_ssq_wait = ctrl->CAS, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_bank = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command RD */ + [2] = { + .sp_cmd_ctrl = { + .command = IOSAV_RD, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 500, + .cmd_delay_gap = 4, + .post_ssq_wait = MAX(ctrl->tRTP, 8), + .data_direction = SSQ_RD, + }, + .sp_cmd_addr = { + .address = 0, + .rowbits = 0, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .inc_addr_8 = 1, + .addr_wrap = 18, + }, + }, + /* DRAM command PREA */ + [3] = { + .sp_cmd_ctrl = { + .command = IOSAV_PRE, + .ranksel_ap = 1, + }, + .subseq_ctrl = { + .cmd_executions = 1, + .cmd_delay_gap = 3, + .post_ssq_wait = ctrl->tRP, + .data_direction = SSQ_NA, + }, + .sp_cmd_addr = { + .address = 1024, + .rowbits = 6, + .bank = 0, + .rank = slotrank, + }, + .addr_update = { + .addr_wrap = 18, + }, + }, + }; + iosav_write_sequence(channel, sequence, ARRAY_SIZE(sequence)); +} + void iosav_write_jedec_write_leveling_sequence( ramctr_timing *ctrl, int channel, int slotrank, int bank, u32 mr1reg) { From 08f749d5f6a4efd7f69ea56e70a231ceebacde09 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 17 Nov 2020 16:50:56 +0100 Subject: [PATCH 037/107] nb/intel/sandybridge: Rename and clean up `discover_edges_write` This is actually an (incomplete) aggressive read training algorithm. Rename functions and variables accordingly, and tidy up declarations. Tested on Asus P8H61-M PRO, still boots. Change-Id: I8a4900f8e3acffe4e4d75a51a2588ad6b65eb411 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47679 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 38 +++++++++---------- .../intel/sandybridge/raminit_common.h | 2 +- .../intel/sandybridge/raminit_native.c | 2 +- 3 files changed, 21 insertions(+), 21 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 4ba2f0de82..7e937862db 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2286,25 +2286,23 @@ int read_mpr_training(ramctr_timing *ctrl) return 0; } -static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotrank, int *edges) +static int find_agrsv_read_margin(ramctr_timing *ctrl, int channel, int slotrank, int *edges) { - int edge; + const int rd_vref_offsets[] = { 0, 0xc, 0x2c }; + u32 raw_stats[MAX_EDGE_TIMING + 1]; - int stats[MAX_EDGE_TIMING + 1]; - const int reg3000b24[] = { 0, 0xc, 0x2c }; - int lane, i; int lower[NUM_LANES]; int upper[NUM_LANES]; - int pat; + int lane, i, read_pi, pat; FOR_ALL_LANES { lower[lane] = 0; upper[lane] = MAX_EDGE_TIMING; } - for (i = 0; i < 3; i++) { + for (i = 0; i < ARRAY_SIZE(rd_vref_offsets); i++) { const union gdcr_training_mod_reg training_mod = { - .vref_gen_ctl = reg3000b24[i], + .vref_gen_ctl = rd_vref_offsets[i], }; MCHBAR32(GDCRTRAININGMOD_ch(channel)) = training_mod.raw; printram("[%x] = 0x%08x\n", GDCRTRAININGMOD_ch(channel), training_mod.raw); @@ -2313,12 +2311,12 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr fill_pattern5(ctrl, channel, pat); printram("using pattern %d\n", pat); - for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) { + for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) { FOR_ALL_LANES { ctrl->timings[channel][slotrank].lanes[lane]. - rising = edge; + rising = read_pi; ctrl->timings[channel][slotrank].lanes[lane]. - falling = edge; + falling = read_pi; } program_timings(ctrl, channel); @@ -2339,13 +2337,15 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr } /* FIXME: This register only exists on Ivy Bridge */ - raw_stats[edge] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); + raw_stats[read_pi] = MCHBAR32(IOSAV_BYTE_SERROR_C_ch(channel)); } FOR_ALL_LANES { + int stats[MAX_EDGE_TIMING + 1]; struct run rn; - for (edge = 0; edge <= MAX_EDGE_TIMING; edge++) - stats[edge] = !!(raw_stats[edge] & (1 << lane)); + + for (read_pi = 0; read_pi <= MAX_EDGE_TIMING; read_pi++) + stats[read_pi] = !!(raw_stats[read_pi] & (1 << lane)); rn = get_longest_zero_run(stats, MAX_EDGE_TIMING + 1); @@ -2374,7 +2374,7 @@ static int discover_edges_write_real(ramctr_timing *ctrl, int channel, int slotr return 0; } -int discover_edges_write(ramctr_timing *ctrl) +int aggressive_read_training(ramctr_timing *ctrl) { int falling_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int rising_edges[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -2385,20 +2385,20 @@ int discover_edges_write(ramctr_timing *ctrl) * also use a single loop. It would seem that it is a debugging configuration. */ MCHBAR32(IOSAV_DC_MASK) = 0x300; - printram("discover falling edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); + printram("discover falling edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x300); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_edges_write_real(ctrl, channel, slotrank, + err = find_agrsv_read_margin(ctrl, channel, slotrank, falling_edges[channel][slotrank]); if (err) return err; } MCHBAR32(IOSAV_DC_MASK) = 0x200; - printram("discover rising edges write:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); + printram("discover rising edges aggressive:\n[%x] = %x\n", IOSAV_DC_MASK, 0x200); FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS { - err = discover_edges_write_real(ctrl, channel, slotrank, + err = find_agrsv_read_margin(ctrl, channel, slotrank, rising_edges[channel][slotrank]); if (err) return err; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 44f4768a95..050aa7047c 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -407,7 +407,7 @@ int receive_enable_calibration(ramctr_timing *ctrl); int write_training(ramctr_timing *ctrl); int command_training(ramctr_timing *ctrl); int read_mpr_training(ramctr_timing *ctrl); -int discover_edges_write(ramctr_timing *ctrl); +int aggressive_read_training(ramctr_timing *ctrl); int discover_timC_write(ramctr_timing *ctrl); void normalize_training(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index ae9a4f46fa..eecd938ec7 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -702,7 +702,7 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ printram("CP5c\n"); - err = discover_edges_write(ctrl); + err = aggressive_read_training(ctrl); if (err) return err; From 1146332b9c3a0a21424b72bf7e68f07eb370f60b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Nov 2020 11:04:28 +0100 Subject: [PATCH 038/107] nb/intel/sandybridge: Increase tRWDRDD with fast RAM This has been reported to increase stability, and vendor BIOS also does the same. Change-Id: I4e3ea76f61771683dea61b18bee531516cda5843 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47744 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/raminit_common.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 7e937862db..6ba91c96e3 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2778,6 +2778,9 @@ void prepare_training(ramctr_timing *ctrl) void set_read_write_timings(ramctr_timing *ctrl) { + /* Use a larger delay when running fast to improve stability */ + const u32 tRWDRDD_inc = ctrl->tCK <= TCK_1066MHZ ? 4 : 2; + int channel, slotrank; FOR_ALL_POPULATED_CHANNELS { @@ -2800,7 +2803,7 @@ void set_read_write_timings(ramctr_timing *ctrl) .tRRDD = val, .tWWDR = val, .tWWDD = val, - .tRWDRDD = ctrl->ref_card_offset[channel] + 2, + .tRWDRDD = ctrl->ref_card_offset[channel] + tRWDRDD_inc, .tWRDRDD = tWRDRDD, .tRWSR = 2, .dec_wrd = 1, From 2ad03a43ecf0c97634f27ebcc2132b8e4286ceb3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Nov 2020 11:07:27 +0100 Subject: [PATCH 039/107] nb/intel/sandybridge: Lower tPRPDEN to 1 This is the default value, and matches what vendor firmware does. Change-Id: Id0c9758a845d711a87c4b06f89fa0926ae658e02 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47745 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/raminit_common.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 6ba91c96e3..b06734c0e0 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -175,7 +175,7 @@ void dram_timing_regs(ramctr_timing *ctrl) .tXP = ctrl->tXP, .tAONPD = ctrl->tAONPD, .tCPDED = 2, - .tPRPDEN = 2, + .tPRPDEN = 1, }; /* From 09fc4b90ebfdb81914f6b89b676db101a417414a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Nov 2020 12:02:07 +0100 Subject: [PATCH 040/107] nb/intel/sandybridge: Refine power-down mode logic When memory is running at fast frequencies, power-down modes can lessen system stability. Check tXP and tXPDLL values and use safer power down modes if their values are high. Do not use APD with DLL-off on mobile: vendor firmware does not use it, and it can influence system stability. Change-Id: Ic8e98162ca86ae454a8c951be163d58960940e0e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47746 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/Kconfig | 9 +++++ .../intel/sandybridge/raminit_common.c | 34 +++++++++++++------ .../intel/sandybridge/raminit_common.h | 9 +++++ 3 files changed, 41 insertions(+), 11 deletions(-) diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index ef6dc3daf5..9cd522f85b 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -99,6 +99,15 @@ config DCACHE_RAM_MRC_VAR_SIZE hex default 0x0 +config RAMINIT_ALWAYS_ALLOW_DLL_OFF + bool "Also enable memory DLL-off mode on desktops and servers" + default n + help + If enabled, allow enabling DLL-off mode for platforms other than + mobile. Saves power at the expense of higher exit latencies. Has + no effect on mobile platforms, where DLL-off is always allowed. + Power down is disabled for stability when running at high clocks. + config RAMINIT_ENABLE_ECC bool "Enable ECC if supported" default y diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index b06734c0e0..d533ca8a30 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -688,11 +688,29 @@ static void write_mrreg(ramctr_timing *ctrl, int channel, int slotrank, int reg, iosav_run_once(channel); } +/* Obtain optimal power down mode for current configuration */ +static enum pdwm_mode get_power_down_mode(ramctr_timing *ctrl) +{ + if (ctrl->tXP > 8) + return PDM_NONE; + + if (ctrl->tXPDLL > 32) + return PDM_PPD; + + if (CONFIG(RAMINIT_ALWAYS_ALLOW_DLL_OFF) || get_platform_type() == PLATFORM_MOBILE) + return PDM_DLL_OFF; + + return PDM_APD_PPD; +} + static u32 make_mr0(ramctr_timing *ctrl, u8 rank) { u16 mr0reg, mch_cas, mch_wr; static const u8 mch_wr_t[12] = { 1, 2, 3, 4, 0, 5, 0, 6, 0, 7, 0, 0 }; - const size_t is_mobile = get_platform_type() == PLATFORM_MOBILE; + + const enum pdwm_mode power_down = get_power_down_mode(ctrl); + + const bool slow_exit = power_down == PDM_DLL_OFF || power_down == PDM_APD_DLL_OFF; /* Convert CAS to MCH register friendly */ if (ctrl->CAS < 12) { @@ -712,8 +730,8 @@ static u32 make_mr0(ramctr_timing *ctrl, u8 rank) mr0reg |= (mch_cas & 0xe) << 3; mr0reg |= mch_wr << 9; - /* Precharge PD - Fast (desktop) 1 or slow (mobile) 0 - mostly power-saving feature */ - mr0reg |= !is_mobile << 12; + /* Precharge PD - Use slow exit when DLL-off is used - mostly power-saving feature */ + mr0reg |= !slow_exit << 12; return mr0reg; } @@ -2830,8 +2848,6 @@ static int encode_wm(int ns) /* FIXME: values in this function should be hardware revision-dependent */ void final_registers(ramctr_timing *ctrl) { - const bool is_mobile = get_platform_type() == PLATFORM_MOBILE; - int channel; int t1_cycles = 0, t1_ns = 0, t2_ns; int t3_ns; @@ -2848,12 +2864,8 @@ void final_registers(ramctr_timing *ctrl) MCHBAR32(TC_OTHP_ch(channel)) = tc_othp.raw; } - if (is_mobile) - /* APD - DLL Off, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_CONFIG) = 0x00000740; - else - /* APD - PPD, 64 DCLKs until idle, decision per rank */ - MCHBAR32(PM_PDWN_CONFIG) = 0x00000340; + /* 64 DCLKs until idle, decision per rank */ + MCHBAR32(PM_PDWN_CONFIG) = get_power_down_mode(ctrl) << 8 | 64; FOR_ALL_CHANNELS MCHBAR32(PM_TRML_M_CONFIG_ch(channel)) = 0x00000aaa; diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 050aa7047c..80d30744a2 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -273,6 +273,15 @@ void iosav_write_memory_test_sequence(ramctr_timing *ctrl, int channel, int slot */ #define MRC_CACHE_VERSION 5 +enum pdwm_mode { + PDM_NONE = 0, + PDM_APD = 1, + PDM_PPD = 2, + PDM_APD_PPD = 3, + PDM_DLL_OFF = 6, + PDM_APD_DLL_OFF = 7, +}; + typedef struct odtmap_st { u16 rttwr; u16 rttnom; From 9fbb1b096ff64e83a822d165fb732f22a2ec6e79 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Nov 2020 12:53:36 +0100 Subject: [PATCH 041/107] nb/intel/sandybridge: Only use write Vref if supported Only some Ivy Bridge SKUs support write Vref control. Change-Id: I4e606c69c6758d909946da43c3d243e3af8833cf Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47747 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/northbridge/intel/sandybridge/raminit_common.c | 7 +++++++ src/northbridge/intel/sandybridge/registers/host_bridge.h | 1 + 2 files changed, 8 insertions(+) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index d533ca8a30..01dfcc4a7e 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2459,6 +2459,13 @@ int discover_timC_write(ramctr_timing *ctrl) int upper[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; int channel, slotrank, lane; + /* Changing the write Vref is only supported on some Ivy Bridge SKUs */ + if (!IS_IVY_CPU(ctrl->cpu)) + return 0; + + if (!(pci_read_config32(HOST_BRIDGE, CAPID0_A) & CAPID_WRTVREF)) + return 0; + FOR_ALL_CHANNELS FOR_ALL_POPULATED_RANKS FOR_ALL_LANES { lower[channel][slotrank][lane] = 0; upper[channel][slotrank][lane] = MAX_TIMC; diff --git a/src/northbridge/intel/sandybridge/registers/host_bridge.h b/src/northbridge/intel/sandybridge/registers/host_bridge.h index 4814b94b6f..95998714c8 100644 --- a/src/northbridge/intel/sandybridge/registers/host_bridge.h +++ b/src/northbridge/intel/sandybridge/registers/host_bridge.h @@ -52,6 +52,7 @@ #define CAPID_ECCDIS (1 << 25) #define CAPID_DDPCD (1 << 14) #define CAPID_PDCD (1 << 12) +#define CAPID_WRTVREF (1 << 1) #define CAPID_DDRSZ(x) (((x) >> 19) & 0x3) #define CAPID0_B 0xe8 /* Capabilities Register B */ From 2a7d752aaa9f999059cf3b88956961ecc1540ba6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Nov 2020 12:49:07 +0100 Subject: [PATCH 042/107] nb/intel/sandybridge: Rename and refactor `discover_timC_write` This is actually aggressive write training, similar to aggressive read training. Rename it accordingly and refactor it to improve clarity. Enabling IOSAV_n_SPECIAL_COMMAND_ADDR optimizations must only be done for later Ivy Bridge steppings. Therefore, guard the code accordingly. Change-Id: Ia3331b95c265113d94cb5d66c57a97cb77fc3dc9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47748 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.c | 53 +++++++++---------- .../intel/sandybridge/raminit_common.h | 2 +- .../intel/sandybridge/raminit_native.c | 2 +- 3 files changed, 28 insertions(+), 29 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.c b/src/northbridge/intel/sandybridge/raminit_common.c index 01dfcc4a7e..399ba5a16d 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.c +++ b/src/northbridge/intel/sandybridge/raminit_common.c @@ -2438,7 +2438,7 @@ int aggressive_read_training(ramctr_timing *ctrl) return 0; } -static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) +static void test_aggressive_write(ramctr_timing *ctrl, int channel, int slotrank) { wait_for_iosav(channel); @@ -2450,9 +2450,15 @@ static void test_timC_write(ramctr_timing *ctrl, int channel, int slotrank) wait_for_iosav(channel); } -int discover_timC_write(ramctr_timing *ctrl) +static void set_write_vref(const int channel, const u8 wr_vref) { - const u8 rege3c_b24[3] = { 0, 0x0f, 0x2f }; + MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~(0x3f << 24), wr_vref << 24); + udelay(2); +} + +int aggressive_write_training(ramctr_timing *ctrl) +{ + const u8 wr_vref_offsets[3] = { 0, 0x0f, 0x2f }; int i, pat; int lower[NUM_CHANNELS][NUM_SLOTRANKS][NUM_LANES]; @@ -2471,21 +2477,17 @@ int discover_timC_write(ramctr_timing *ctrl) upper[channel][slotrank][lane] = MAX_TIMC; } - /* - * Enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. - * FIXME: This must only be done on Ivy Bridge. - */ - MCHBAR32(MCMNTS_SPARE) = 1; + /* Only enable IOSAV_n_SPECIAL_COMMAND_ADDR optimization on later steppings */ + const bool enable_iosav_opt = IS_IVY_CPU_D(ctrl->cpu) || IS_IVY_CPU_E(ctrl->cpu); + + if (enable_iosav_opt) + MCHBAR32(MCMNTS_SPARE) = 1; + printram("discover timC write:\n"); - for (i = 0; i < 3; i++) + for (i = 0; i < ARRAY_SIZE(wr_vref_offsets); i++) { FOR_ALL_POPULATED_CHANNELS { - - /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND_OR(GDCRCMDDEBUGMUXCFG_Cz_S(channel), - ~0x3f000000, rege3c_b24[i] << 24); - - udelay(2); + set_write_vref(channel, wr_vref_offsets[i]); for (pat = 0; pat < NUM_PATTERNS; pat++) { FOR_ALL_POPULATED_RANKS { @@ -2505,9 +2507,8 @@ int discover_timC_write(ramctr_timing *ctrl) } program_timings(ctrl, channel); - test_timC_write (ctrl, channel, slotrank); + test_aggressive_write(ctrl, channel, slotrank); - /* FIXME: Another IVB-only register! */ raw_stats[timC] = MCHBAR32( IOSAV_BYTE_SERROR_C_ch(channel)); } @@ -2546,18 +2547,16 @@ int discover_timC_write(ramctr_timing *ctrl) } } } - - FOR_ALL_CHANNELS { - /* FIXME: Setting the Write VREF must only be done on Ivy Bridge */ - MCHBAR32_AND(GDCRCMDDEBUGMUXCFG_Cz_S(channel), ~0x3f000000); - udelay(2); } - /* - * Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization. - * FIXME: This must only be done on Ivy Bridge. - */ - MCHBAR32(MCMNTS_SPARE) = 0; + FOR_ALL_CHANNELS { + /* Restore nominal write Vref after training */ + set_write_vref(channel, 0); + } + + /* Disable IOSAV_n_SPECIAL_COMMAND_ADDR optimization */ + if (enable_iosav_opt) + MCHBAR32(MCMNTS_SPARE) = 0; printram("CPB\n"); diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index 80d30744a2..f2d0fb5060 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -417,7 +417,7 @@ int write_training(ramctr_timing *ctrl); int command_training(ramctr_timing *ctrl); int read_mpr_training(ramctr_timing *ctrl); int aggressive_read_training(ramctr_timing *ctrl); -int discover_timC_write(ramctr_timing *ctrl); +int aggressive_write_training(ramctr_timing *ctrl); void normalize_training(ramctr_timing *ctrl); int channel_test(ramctr_timing *ctrl); void set_scrambling_seed(ramctr_timing *ctrl); diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index eecd938ec7..aec6a857cf 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -706,7 +706,7 @@ int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, int s3resume, int me_ if (err) return err; - err = discover_timC_write(ctrl); + err = aggressive_write_training(ctrl); if (err) return err; From 2921cbf277f533126e1bd84702e83957c977f5b6 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Nov 2020 16:41:40 +0100 Subject: [PATCH 043/107] nb/intel/sandybridge: Correct get_COMP2 function Values differ between Sandy and Ivy Bridge. Remove the lookup table, since it contains duplicated values and is hard to see which values correspond to which frequencies. New values come from reference code. Change-Id: I3b28568f0053f1b39618e16bdffc24207547d81f Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47765 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_native.c | 21 +++++++++++++------ .../intel/sandybridge/raminit_tables.c | 17 --------------- .../intel/sandybridge/raminit_tables.h | 2 -- 3 files changed, 15 insertions(+), 25 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index aec6a857cf..e7a3352b28 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -157,14 +157,23 @@ static u8 get_AONPD(u32 FRQ, u8 base_freq) return frq_aonpd_map[0][FRQ - 3]; } -/* Get COMP2 based on frequency index */ -static u32 get_COMP2(u32 FRQ, u8 base_freq) +/* Get COMP2 based on CPU generation and clock speed */ +static u32 get_COMP2(const ramctr_timing *ctrl) { - if (base_freq == 100) - return frq_comp2_map[1][FRQ - 7]; + const bool is_ivybridge = IS_IVY_CPU(ctrl->cpu); + if (ctrl->tCK <= TCK_1066MHZ) + return is_ivybridge ? 0x0C235924 : 0x0C21410C; + else if (ctrl->tCK <= TCK_933MHZ) + return is_ivybridge ? 0x0C446964 : 0x0C42514C; + else if (ctrl->tCK <= TCK_800MHZ) + return is_ivybridge ? 0x0C6671E4 : 0x0C6369CC; + else if (ctrl->tCK <= TCK_666MHZ) + return is_ivybridge ? 0x0CA8C264 : 0x0CA57A4C; + else if (ctrl->tCK <= TCK_533MHZ) + return is_ivybridge ? 0x0CEBDB64 : 0x0CE7C34C; else - return frq_comp2_map[0][FRQ - 3]; + return is_ivybridge ? 0x0D6FF5E4 : 0x0D6BEDCC; } static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) @@ -586,7 +595,7 @@ static void dram_ioregs(ramctr_timing *ctrl) printram("done\n"); /* Set COMP2 */ - MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl->FRQ, ctrl->base_freq); + MCHBAR32(CRCOMPOFST2) = get_COMP2(ctrl); printram("COMP2 done\n"); /* Set COMP1 */ diff --git a/src/northbridge/intel/sandybridge/raminit_tables.c b/src/northbridge/intel/sandybridge/raminit_tables.c index c3ba9de863..3643dcb4c2 100644 --- a/src/northbridge/intel/sandybridge/raminit_tables.c +++ b/src/northbridge/intel/sandybridge/raminit_tables.c @@ -91,23 +91,6 @@ const u8 frq_aonpd_map[2][8] = { }, }; -const u32 frq_comp2_map[2][8] = { - { /* 133 MHz */ - /* FRQ: 7, 8, 9, 10, */ - 0x0CA8C264, 0x0C6671E4, 0x0C6671E4, 0x0C446964, - - /* FRQ: 11, 12, N/A, N/A, */ - 0x0C235924, 0x0C235924, 0, 0, - }, - { /* 100 MHz */ - /* FRQ: 3, 4, 5, 6, */ - 0x0D6FF5E4, 0x0CEBDB64, 0x0CA8C264, 0x0C6671E4, - - /* FRQ: 7, 8, 9, 10, */ - 0x0C446964, 0x0C235924, 0x0C235924, 0x0C235924, - }, -}; - const u32 pattern[32][16] = { {0x00000000, 0x00000000, 0xffffffff, 0xffffffff, 0x00000000, 0x00000000, 0xffffffff, 0xffffffff, diff --git a/src/northbridge/intel/sandybridge/raminit_tables.h b/src/northbridge/intel/sandybridge/raminit_tables.h index 49101cb5ee..308448f967 100644 --- a/src/northbridge/intel/sandybridge/raminit_tables.h +++ b/src/northbridge/intel/sandybridge/raminit_tables.h @@ -21,8 +21,6 @@ extern const u8 frq_xp_map[2][8]; extern const u8 frq_aonpd_map[2][8]; -extern const u32 frq_comp2_map[2][8]; - extern const u32 pattern[32][16]; extern const u8 use_base[63][32]; From 4f86d630066eea380be76952f533ddaa5a8b28fd Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Nov 2020 17:18:46 +0100 Subject: [PATCH 044/107] nb/intel/sandybridge: Clean up COMPOFST1 logic This register needs to be updated differently depending on the CPU generation and stepping. Handle this as per reference code. Further, introduce a bitfield for the register to make the code easier to read. Change-Id: I51649cb2fd06c5896f90559f59f25d49a8e6695e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47766 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../intel/sandybridge/raminit_common.h | 17 +++++++ .../intel/sandybridge/raminit_native.c | 45 ++++++++++++++++--- 2 files changed, 55 insertions(+), 7 deletions(-) diff --git a/src/northbridge/intel/sandybridge/raminit_common.h b/src/northbridge/intel/sandybridge/raminit_common.h index f2d0fb5060..debfaa2f2a 100644 --- a/src/northbridge/intel/sandybridge/raminit_common.h +++ b/src/northbridge/intel/sandybridge/raminit_common.h @@ -140,6 +140,23 @@ union gdcr_training_mod_reg { u32 raw; }; +union comp_ofst_1_reg { + struct { + u32 dq_odt_down : 3; /* [ 2.. 0] */ + u32 dq_odt_up : 3; /* [ 5.. 3] */ + u32 clk_odt_down : 3; /* [ 8.. 6] */ + u32 clk_odt_up : 3; /* [11.. 9] */ + u32 dq_drv_down : 3; /* [14..12] */ + u32 dq_drv_up : 3; /* [17..15] */ + u32 clk_drv_down : 3; /* [20..18] */ + u32 clk_drv_up : 3; /* [23..21] */ + u32 ctl_drv_down : 3; /* [26..24] */ + u32 ctl_drv_up : 3; /* [29..27] */ + u32 : 2; + }; + u32 raw; +}; + union tc_dbp_reg { struct { u32 tRCD : 4; /* [ 3.. 0] */ diff --git a/src/northbridge/intel/sandybridge/raminit_native.c b/src/northbridge/intel/sandybridge/raminit_native.c index e7a3352b28..3522e96ecc 100644 --- a/src/northbridge/intel/sandybridge/raminit_native.c +++ b/src/northbridge/intel/sandybridge/raminit_native.c @@ -176,6 +176,43 @@ static u32 get_COMP2(const ramctr_timing *ctrl) return is_ivybridge ? 0x0D6FF5E4 : 0x0D6BEDCC; } +/* Get updated COMP1 based on CPU generation and stepping */ +static u32 get_COMP1(ramctr_timing *ctrl, const int channel) +{ + const union comp_ofst_1_reg orig_comp = { + .raw = MCHBAR32(CRCOMPOFST1_ch(channel)), + }; + + if (IS_SANDY_CPU(ctrl->cpu) && !IS_SANDY_CPU_D2(ctrl->cpu)) { + union comp_ofst_1_reg comp_ofst_1 = orig_comp; + + comp_ofst_1.clk_odt_up = 1; + comp_ofst_1.clk_drv_up = 1; + comp_ofst_1.ctl_drv_up = 1; + + return comp_ofst_1.raw; + } + + /* Fix PCODE COMP offset bug: revert to default values */ + union comp_ofst_1_reg comp_ofst_1 = { + .dq_odt_down = 4, + .dq_odt_up = 4, + .clk_odt_down = 4, + .clk_odt_up = orig_comp.clk_odt_up, + .dq_drv_down = 4, + .dq_drv_up = orig_comp.dq_drv_up, + .clk_drv_down = 4, + .clk_drv_up = orig_comp.clk_drv_up, + .ctl_drv_down = 4, + .ctl_drv_up = orig_comp.ctl_drv_up, + }; + + if (IS_IVY_CPU(ctrl->cpu)) + comp_ofst_1.dq_drv_up = 2; /* 28p6 ohms */ + + return comp_ofst_1.raw; +} + static void normalize_tclk(ramctr_timing *ctrl, bool ref_100mhz_support) { if (ctrl->tCK <= TCK_1200MHZ) { @@ -568,8 +605,6 @@ static void dram_freq(ramctr_timing *ctrl) static void dram_ioregs(ramctr_timing *ctrl) { - u32 reg; - int channel; /* IO clock */ @@ -600,11 +635,7 @@ static void dram_ioregs(ramctr_timing *ctrl) /* Set COMP1 */ FOR_ALL_POPULATED_CHANNELS { - reg = MCHBAR32(CRCOMPOFST1_ch(channel)); - reg = (reg & ~0x00000e00) | (1 << 9); /* ODT */ - reg = (reg & ~0x00e00000) | (1 << 21); /* clk drive up */ - reg = (reg & ~0x38000000) | (1 << 27); /* ctl drive up */ - MCHBAR32(CRCOMPOFST1_ch(channel)) = reg; + MCHBAR32(CRCOMPOFST1_ch(channel)) = get_COMP1(ctrl, channel); } printram("COMP1 done\n"); From 0b6ab953f3ee4c1fb9fe7ab7d580f3a7165b6c98 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Nov 2020 12:13:09 +0100 Subject: [PATCH 045/107] util/inteltool/ivy_memory.c: Properly mask tAONPD This field is only 4 bits wide. Change-Id: I2cb746e98176d58fc5be423e18babdaa8801b096 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47749 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Arthur Heymans --- util/inteltool/ivy_memory.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 7a81a92dba..3836c11c15 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -158,7 +158,7 @@ void ivybridge_dump_timings(const char *dump_spd_file) reg = read_mchbar32(0x400c + channel * 0x400); tXPDLL[channel] = reg & 0x1f; tXP[channel] = (reg >> 5) & 7; - tAONPD[channel] = (reg >> 8) & 0xff; + tAONPD[channel] = (reg >> 8) & 0xf; } printf(".mobile = %d,\n", (mr0[0] >> 12) & 1); print_time("CAS", CAS, tCK); From 121d2de18d87008de9d12f3294acf5cd15930f56 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Nov 2020 12:20:37 +0100 Subject: [PATCH 046/107] util/inteltool/ivy_memory.c: Do not rely on MR0 values MR0 may not always be programmed in the training result registers. Thus, do not rely on its values. Also account for per-channel differences. Change-Id: Iaf3b545ea55735b46caf1bd62d5859f2b3efa159 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47750 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Stefan Reinauer --- util/inteltool/ivy_memory.c | 39 +++++++++++++++++++++++-------------- 1 file changed, 24 insertions(+), 15 deletions(-) diff --git a/util/inteltool/ivy_memory.c b/util/inteltool/ivy_memory.c index 3836c11c15..15d3a10bc0 100644 --- a/util/inteltool/ivy_memory.c +++ b/util/inteltool/ivy_memory.c @@ -60,7 +60,7 @@ void ivybridge_dump_timings(const char *dump_spd_file) u32 mr0[2]; u32 mr1[2]; u32 reg; - unsigned int CAS = 0; + unsigned int CAS[2] = { 0 }; int tWR = 0, tRFC = 0; int tFAW[2], tWTR[2], tCKE[2], tRTP[2], tRRD[2]; int channel, slot; @@ -108,14 +108,16 @@ void ivybridge_dump_timings(const char *dump_spd_file) tCK = (64 * 10 * 3) / reg; - if (mr0[0] & 1) { - CAS = ((mr0[0] >> 4) & 0x7) + 12; - } else { - CAS = ((mr0[0] >> 4) & 0x7) + 4; - } - for (channel = 0; channel < 2; channel++) { mad_dimm[channel] = read_mchbar32(0x5004 + 4 * channel); + + if (mr0[channel]) { + if (mr0[channel] & 1) { + CAS[channel] = ((mr0[channel] >> 4) & 0x7) + 12; + } else { + CAS[channel] = ((mr0[channel] >> 4) & 0x7) + 4; + } + } } printf(".rankmap = { 0x%x, 0x%x },\n", rankmap[0], rankmap[1]); @@ -135,7 +137,7 @@ void ivybridge_dump_timings(const char *dump_spd_file) ctWR); if (!tWR) tWR = ctWR; - if (((mr0[channel] >> 9) & 7) != mr0_wr_t[tWR - 5]) + if (mr0[channel] && ((mr0[channel] >> 9) & 7) != mr0_wr_t[tWR - 5]) printf("/* encoded tWR mismatch: %d, %d */\n", ((mr0[channel] >> 9) & 7), mr0_wr_t[tWR - 5]); @@ -149,9 +151,13 @@ void ivybridge_dump_timings(const char *dump_spd_file) reg = read_mchbar32(0x4000 + 0x400 * channel); tRAS[channel] = reg >> 16; tCWL[channel] = (reg >> 12) & 0xf; - if (CAS != ((reg >> 8) & 0xf)) - printf("/* CAS mismatch: %d, %d. */\n", CAS, - (reg >> 8) & 0xf); + if (CAS[channel]) { + if (CAS[channel] != ((reg >> 8) & 0xf)) + printf("/* CAS mismatch: %d, %d. */\n", CAS[channel], + (reg >> 8) & 0xf); + } else { + CAS[channel] = (reg >> 8) & 0xf; + } tRP[channel] = (reg >> 4) & 0xf; tRCD[channel] = reg & 0xf; @@ -161,7 +167,10 @@ void ivybridge_dump_timings(const char *dump_spd_file) tAONPD[channel] = (reg >> 8) & 0xf; } printf(".mobile = %d,\n", (mr0[0] >> 12) & 1); - print_time("CAS", CAS, tCK); + + if (two_channels && CAS[0] != CAS[1]) + printf("/* CAS mismatch: %d, %d */\n", CAS[0], CAS[1]); + print_time("CAS", CAS[0], tCK); print_time("tWR", tWR, tCK); printf(".reg_4004_b30 = { %d, %d },\n", reg_4004_b30[0], @@ -315,10 +324,10 @@ void ivybridge_dump_timings(const char *dump_spd_file) spd[channel][slot][12] = make_spd_time(1, tCK); spd[channel][slot][13] = 0; spd[channel][slot][14] = - (1 << (CAS - 4)) & 0xff; - spd[channel][slot][15] = (1 << (CAS - 4)) >> 8; + (1 << (CAS[channel] - 4)) & 0xff; + spd[channel][slot][15] = (1 << (CAS[channel] - 4)) >> 8; spd[channel][slot][16] = - make_spd_time(CAS, tCK); + make_spd_time(CAS[channel], tCK); spd[channel][slot][17] = make_spd_time(tWR, tCK); spd[channel][slot][18] = From 6c8ba9b9ae0a0eb04f6c7be3ba8185f49db13d00 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Fri, 20 Nov 2020 22:26:38 -0800 Subject: [PATCH 047/107] vc/amd/pi/00670F00: Add raw AGESA binary only to COREBOOT CBFS If AGESA is added as a raw binary (and not a stage), then cbfstool does not perform relocation. In this case, it should be added only to COREBOOT (i.e. default) CBFS since the binary needs to be present only in one specific location that is present in the default CBFS. Change-Id: I7a7edc217663f9d1d36b05308bbd35f56a28b9b1 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/47832 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/vendorcode/amd/pi/00670F00/Makefile.inc | 1 + 1 file changed, 1 insertion(+) diff --git a/src/vendorcode/amd/pi/00670F00/Makefile.inc b/src/vendorcode/amd/pi/00670F00/Makefile.inc index 46af6559bd..71898a3c54 100644 --- a/src/vendorcode/amd/pi/00670F00/Makefile.inc +++ b/src/vendorcode/amd/pi/00670F00/Makefile.inc @@ -170,6 +170,7 @@ $(CONFIG_AGESA_CBFS_NAME)-align := 4096 else $(CONFIG_AGESA_CBFS_NAME)-type := raw $(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION) +regions-for-file-$(CONFIG_AGESA_CBFS_NAME) = COREBOOT endif # CONFIG_AGESA_BINARY_PI_AS_STAGE endif # AGESA_BINARYPI_INPUT_FILE == "" From f61011a56fba8fce5eee19f8c4e5979c4427c81e Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Fri, 20 Nov 2020 15:36:22 -0700 Subject: [PATCH 048/107] mb/google/brya: Add new google brya mainboard This commit is a stub for brya, which is a an Intel Alder Lake-P reference platform. BUG=b:173562731 TEST=util/abuild/abuild -p none -t google/brya -a -c max Signed-off-by: Tim Wawrzynczak Change-Id: Ia34130ff92a0a07063cb8e80527204b3a80184a0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47819 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: EricR Lai --- src/mainboard/google/brya/Kconfig | 29 +++++++++++++++++++ src/mainboard/google/brya/Kconfig.name | 4 +++ src/mainboard/google/brya/board_info.txt | 6 ++++ src/mainboard/google/brya/dsdt.asl | 14 +++++++++ .../brya/variants/baseboard/devicetree.cb | 5 ++++ 5 files changed, 58 insertions(+) create mode 100644 src/mainboard/google/brya/Kconfig create mode 100644 src/mainboard/google/brya/Kconfig.name create mode 100644 src/mainboard/google/brya/board_info.txt create mode 100644 src/mainboard/google/brya/dsdt.asl create mode 100644 src/mainboard/google/brya/variants/baseboard/devicetree.cb diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig new file mode 100644 index 0000000000..f538adef01 --- /dev/null +++ b/src/mainboard/google/brya/Kconfig @@ -0,0 +1,29 @@ +config BOARD_GOOGLE_BASEBOARD_BRYA + def_bool n + select BOARD_ROMSIZE_KB_32768 + select HAVE_ACPI_TABLES + select SOC_INTEL_ALDERLAKE + +if BOARD_GOOGLE_BASEBOARD_BRYA + +config BASEBOARD_BRYA_LAPTOP + def_bool n + select SYSTEM_TYPE_LAPTOP + +config DEVICETREE + string + default "variants/baseboard/devicetree.cb" + +config MAINBOARD_DIR + string + default "google/brya" + +config MAINBOARD_FAMILY + string + default "Google_Brya0" if BOARD_GOOGLE_BRYA0 + +config MAINBOARD_PART_NUMBER + string + default "brya" if BOARD_GOOGLE_BRYA0 + +endif # BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/Kconfig.name b/src/mainboard/google/brya/Kconfig.name new file mode 100644 index 0000000000..db2252afe3 --- /dev/null +++ b/src/mainboard/google/brya/Kconfig.name @@ -0,0 +1,4 @@ +config BOARD_GOOGLE_BRYA0 + bool "Brya 0" + select BOARD_GOOGLE_BASEBOARD_BRYA + select BASEBOARD_BRYA_LAPTOP diff --git a/src/mainboard/google/brya/board_info.txt b/src/mainboard/google/brya/board_info.txt new file mode 100644 index 0000000000..dad16fa8b3 --- /dev/null +++ b/src/mainboard/google/brya/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Google +Board name: Brya +Category: laptop +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/google/brya/dsdt.asl b/src/mainboard/google/brya/dsdt.asl new file mode 100644 index 0000000000..10d08e26e2 --- /dev/null +++ b/src/mainboard/google/brya/dsdt.asl @@ -0,0 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ +} diff --git a/src/mainboard/google/brya/variants/baseboard/devicetree.cb b/src/mainboard/google/brya/variants/baseboard/devicetree.cb new file mode 100644 index 0000000000..fbd7d72f9f --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/devicetree.cb @@ -0,0 +1,5 @@ +chip soc/intel/alderlake + device cpu_cluster 0 on + device lapic 0 on end + end +end From f752fc654610cb8dd481a9b735b495e2109610e0 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 10 Nov 2020 14:55:53 -0700 Subject: [PATCH 049/107] mb/google/sarien: Configure IRQs as level triggered for HID over I2C As per HID over I2C Protocol Specification[1] Version 1.00 Section 7.4, the interrupt line used by the device is required to be level triggered. Hence, this change updates the configuration of the HID over I2C devices to be level triggered. References: [1] http://download.microsoft.com/download/7/d/d/7dd44bb7-2a7a-4505-ac1c-7227d3d96d5b/hid-over-i2c-protocol-spec-v1-0.docx BUG=b:172846122 TEST=./util/abuild/abuild Change-Id: I27c485c9c8c5d47a44fc050d8cf12c553bffd01e Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/47424 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/mainboard/google/sarien/variants/arcada/devicetree.cb | 2 +- src/mainboard/google/sarien/variants/sarien/devicetree.cb | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/sarien/variants/arcada/devicetree.cb b/src/mainboard/google/sarien/variants/arcada/devicetree.cb index 74529d049d..9e05213440 100644 --- a/src/mainboard/google/sarien/variants/arcada/devicetree.cb +++ b/src/mainboard/google/sarien/variants/arcada/devicetree.cb @@ -337,7 +337,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""PNP0C50"" register "generic.desc" = ""Cirque Touchpad"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_B3_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_B3_IRQ)" register "generic.probed" = "1" register "hid_desc_reg_offset" = "0x20" device i2c 2a on end diff --git a/src/mainboard/google/sarien/variants/sarien/devicetree.cb b/src/mainboard/google/sarien/variants/sarien/devicetree.cb index 519c3eb6d9..005a783e4f 100644 --- a/src/mainboard/google/sarien/variants/sarien/devicetree.cb +++ b/src/mainboard/google/sarien/variants/sarien/devicetree.cb @@ -326,7 +326,7 @@ chip soc/intel/cannonlake chip drivers/i2c/hid register "generic.hid" = ""ELAN900C"" register "generic.desc" = ""ELAN Touchscreen"" - register "generic.irq" = "ACPI_IRQ_EDGE_LOW(GPP_C23_IRQ)" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C23_IRQ)" register "generic.probed" = "1" register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E7)" From 335eb1219c73032eee92462f76d508233fb97b55 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 19 Nov 2020 15:45:43 +0100 Subject: [PATCH 050/107] src/drivers/intel/fsp1_1/cache_as_ram.S: Clear _bss area only Whole car region is cleared, while only small part needs to be done. Clear .bss area only Tested on Facebook FBG1701 Change-Id: I021c2f7d3531c553015fde98d155915f897b434d Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/47760 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/drivers/intel/fsp1_1/cache_as_ram.S | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index 3be9eb92df..b5b47ce9a6 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -145,14 +145,13 @@ CAR_init_done: * mm1: high 32-bits of TSC value */ - /* coreboot assumes stack/heap region will be zero */ + /* clear .bss section */ cld - movl %ecx, %edi - neg %ecx - /* Clear up to Temp Ram top. */ - add %edx, %ecx + xor %eax, %eax + movl $(_ebss), %ecx + movl $(_bss), %edi + sub %edi, %ecx shrl $2, %ecx - xorl %eax, %eax rep stosl /* Need to align stack to 16 bytes at call instruction. Account for From c022a795033062ed1b1908d18fa419444e42aceb Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 20 Nov 2020 10:52:39 +0100 Subject: [PATCH 051/107] drivers/intel/fsp1_1: Add function to report FSP-T output This allows to compare the FSP-T output in %ecx and %edx to coreboot's CAR symbols. Tested on Facebook FBG1701 Change-Id: Ice748e542180f6e1dc1505e7f37b6b6c68772bda Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/47758 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/intel/fsp1_1/Makefile.inc | 1 + src/drivers/intel/fsp1_1/cache_as_ram.S | 13 ++++++++++ src/drivers/intel/fsp1_1/fsp_report.c | 27 +++++++++++++++++++++ src/drivers/intel/fsp1_1/include/fsp/util.h | 1 + 4 files changed, 42 insertions(+) create mode 100644 src/drivers/intel/fsp1_1/fsp_report.c diff --git a/src/drivers/intel/fsp1_1/Makefile.inc b/src/drivers/intel/fsp1_1/Makefile.inc index 5fc100aa4b..abac7fba17 100644 --- a/src/drivers/intel/fsp1_1/Makefile.inc +++ b/src/drivers/intel/fsp1_1/Makefile.inc @@ -9,6 +9,7 @@ verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += verstage.c bootblock-$(CONFIG_USE_GENERIC_FSP_CAR_INC) += cache_as_ram.S bootblock-y += fsp_util.c bootblock-y += ../../../cpu/intel/microcode/microcode_asm.S +bootblock-y += fsp_report.c romstage-y += car.c romstage-y += fsp_util.c diff --git a/src/drivers/intel/fsp1_1/cache_as_ram.S b/src/drivers/intel/fsp1_1/cache_as_ram.S index b5b47ce9a6..f2d29aa4a8 100644 --- a/src/drivers/intel/fsp1_1/cache_as_ram.S +++ b/src/drivers/intel/fsp1_1/cache_as_ram.S @@ -145,6 +145,14 @@ CAR_init_done: * mm1: high 32-bits of TSC value */ + /* + * temp_memory_start/end reside in the .bss section, which gets cleared + * below. Save the FSP return value to the stack before writing those + * variables. + */ + push %ecx + push %edx + /* clear .bss section */ cld xor %eax, %eax @@ -154,6 +162,11 @@ CAR_init_done: shrl $2, %ecx rep stosl + pop %edx + movl %edx, temp_memory_end + pop %ecx + movl %ecx, temp_memory_start + /* Need to align stack to 16 bytes at call instruction. Account for the pushes below. */ andl $0xfffffff0, %esp diff --git a/src/drivers/intel/fsp1_1/fsp_report.c b/src/drivers/intel/fsp1_1/fsp_report.c new file mode 100644 index 0000000000..884218d7f7 --- /dev/null +++ b/src/drivers/intel/fsp1_1/fsp_report.c @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* filled in assembly after FSP-T ran */ +uintptr_t temp_memory_start; +uintptr_t temp_memory_end; + +void report_fsp_output(void) +{ + const struct region fsp_car_region = { + .offset = temp_memory_start, + .size = temp_memory_end - temp_memory_start, + }; + const struct region coreboot_car_region = { + .offset = (uintptr_t)_car_region_start, + .size = (uintptr_t)_car_region_size, + }; + printk(BIOS_DEBUG, "FSP: reported temp_mem region: [0x%08lx,0x%08lx)\n", + temp_memory_start, temp_memory_end); + if (!region_is_subregion(&fsp_car_region, &coreboot_car_region)) { + printk(BIOS_ERR, "Wrong CAR region used!\n"); + printk(BIOS_ERR, "Adapt DCACHE_RAM_BASE and DCACHE_RAM_SIZE to match FSP-T\n"); + } +} diff --git a/src/drivers/intel/fsp1_1/include/fsp/util.h b/src/drivers/intel/fsp1_1/include/fsp/util.h index 41ffedde1d..cab867a68d 100644 --- a/src/drivers/intel/fsp1_1/include/fsp/util.h +++ b/src/drivers/intel/fsp1_1/include/fsp/util.h @@ -31,6 +31,7 @@ void *get_next_resource_hob(const EFI_GUID *guid, const void *hob_start); void *get_first_resource_hob(const EFI_GUID *guid); void fsp_display_upd_value(const char *name, uint32_t size, uint64_t old, uint64_t new); +void report_fsp_output(void); /* Return version of FSP associated with fih. */ static inline uint32_t fsp_version(FSP_INFO_HEADER *fih) From 0948b363b0568e70af2352566dee39e0df82d96d Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 19 Nov 2020 15:13:02 +0100 Subject: [PATCH 052/107] soc/intel/braswell/bootblock/bootblock.c: Report the FSP-T output Report the FSP temporary RAM location Tested on Facebook FBG1701 Change-Id: Ia2ce48f7a7948d1fe51ad1ca33b8fb385674cb41 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/47759 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- src/soc/intel/braswell/bootblock/bootblock.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/src/soc/intel/braswell/bootblock/bootblock.c b/src/soc/intel/braswell/bootblock/bootblock.c index 10ac02584d..ae1c97a9c4 100644 --- a/src/soc/intel/braswell/bootblock/bootblock.c +++ b/src/soc/intel/braswell/bootblock/bootblock.c @@ -5,6 +5,7 @@ #include #include #include +#include #include #include #include @@ -117,6 +118,8 @@ void bootblock_soc_early_init(void) } void bootblock_soc_init(void) { + report_fsp_output(); + /* Continue chipset initialization */ soc_rtc_init(); set_max_freq(); From 0fcd37172f22a55fecd5ae6752fc18218b88a8f3 Mon Sep 17 00:00:00 2001 From: Maxim Polyakov Date: Sat, 20 Jun 2020 17:26:21 +0300 Subject: [PATCH 053/107] mb/kontron: Add Kontron mAL10 COMe module support This patch adds support for the Kontron mAL10 COMe module with the Apollo Lake SoC together with Kontron T10-TNI carrierboard. Working: - UART console and I2C on Kontron kempld; - USB2/3 - Ethernet controller - eMMC - SATA - PCIe ports - IGD/DP - SMBus - HWM Not tested: - IGD/LVDS - SDIO TODO: - HDA (codec IDT 92HD73C1X5, currently disabled) Tested payloads: - SeaBIOS - Tianocore, UEFIPayload - without video, EFI-shell in console only Tested on COMe module with Intel Atom x5-E3940 processor (4 Core, 1.6/1.8GHz, 9.5W TDP). Xubuntu 18.04.2 was used as a bootable OS (5.0.0-32-generic linux kernel) Change-Id: Ib8432e10396f77eb05a71af1ccaaa4437a2e43ea Signed-off-by: Maxim Polyakov Reviewed-on: https://review.coreboot.org/c/coreboot/+/39133 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- Documentation/mainboard/index.md | 4 + Documentation/mainboard/kontron/mal10.md | 106 +++++++ src/mainboard/kontron/mal10/Kconfig | 58 ++++ src/mainboard/kontron/mal10/Kconfig.name | 2 + src/mainboard/kontron/mal10/Makefile.inc | 9 + src/mainboard/kontron/mal10/acpi/dptf.asl | 31 ++ src/mainboard/kontron/mal10/board_info.txt | 6 + src/mainboard/kontron/mal10/bootblock.c | 26 ++ .../mal10/carriers/t10-tni/Makefile.inc | 1 + .../mal10/carriers/t10-tni/board_info.txt | 8 + .../kontron/mal10/carriers/t10-tni/gpio.c | 267 ++++++++++++++++++ .../carriers/t10-tni/include/carrier/gpio.h | 32 +++ .../mal10/carriers/t10-tni/overridetree.cb | 42 +++ src/mainboard/kontron/mal10/cmos.default | 6 + src/mainboard/kontron/mal10/cmos.layout | 55 ++++ src/mainboard/kontron/mal10/dsdt.asl | 29 ++ src/mainboard/kontron/mal10/mal10.fmd | 21 ++ src/mainboard/kontron/mal10/ramstage.c | 47 +++ src/mainboard/kontron/mal10/romstage.c | 28 ++ .../kontron/mal10/variants/mal10/Makefile.inc | 1 + .../mal10/variants/mal10/board_info.txt | 8 + .../kontron/mal10/variants/mal10/data.vbt | Bin 0 -> 6154 bytes .../mal10/variants/mal10/devicetree.cb | 114 ++++++++ .../mal10/variants/mal10/gma-mainboard.ads | 13 + .../kontron/mal10/variants/mal10/gpio.c | 36 +++ .../variants/mal10/include/variant/gpio.h | 11 + 26 files changed, 961 insertions(+) create mode 100644 Documentation/mainboard/kontron/mal10.md create mode 100644 src/mainboard/kontron/mal10/Kconfig create mode 100644 src/mainboard/kontron/mal10/Kconfig.name create mode 100644 src/mainboard/kontron/mal10/Makefile.inc create mode 100644 src/mainboard/kontron/mal10/acpi/dptf.asl create mode 100644 src/mainboard/kontron/mal10/board_info.txt create mode 100644 src/mainboard/kontron/mal10/bootblock.c create mode 100644 src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc create mode 100644 src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt create mode 100644 src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c create mode 100644 src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h create mode 100644 src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb create mode 100644 src/mainboard/kontron/mal10/cmos.default create mode 100644 src/mainboard/kontron/mal10/cmos.layout create mode 100644 src/mainboard/kontron/mal10/dsdt.asl create mode 100644 src/mainboard/kontron/mal10/mal10.fmd create mode 100644 src/mainboard/kontron/mal10/ramstage.c create mode 100644 src/mainboard/kontron/mal10/romstage.c create mode 100644 src/mainboard/kontron/mal10/variants/mal10/Makefile.inc create mode 100644 src/mainboard/kontron/mal10/variants/mal10/board_info.txt create mode 100644 src/mainboard/kontron/mal10/variants/mal10/data.vbt create mode 100644 src/mainboard/kontron/mal10/variants/mal10/devicetree.cb create mode 100644 src/mainboard/kontron/mal10/variants/mal10/gma-mainboard.ads create mode 100644 src/mainboard/kontron/mal10/variants/mal10/gpio.c create mode 100644 src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index d6aed22128..4b46b7ce02 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -76,6 +76,10 @@ The boards in this section are not real mainboards, but emulators. - [IceLake RVP](intel/icelake_rvp.md) - [KBLRVP11](intel/kblrvp11.md) +## Kontron + +- [mAL-10](kontron/mal10.md) + ## Lenovo - [Mainboard codenames](lenovo/codenames.md) diff --git a/Documentation/mainboard/kontron/mal10.md b/Documentation/mainboard/kontron/mal10.md new file mode 100644 index 0000000000..b2eefc3df2 --- /dev/null +++ b/Documentation/mainboard/kontron/mal10.md @@ -0,0 +1,106 @@ +# Kontron mAL10 Computer-on-Modules platform + +The Kontron [mAL10] COMe is a credit card sized Computer-on-Modules +platform based on the Intel Atom E3900 Series, Pentium and Celeron +processors. + +## Technology + +```eval_rst ++------------------+----------------------------------+ +| COMe Type | mini pin-out type 10 | ++------------------+----------------------------------+ +| SoC | Intel Atom x5-E3940 (4 core) | ++------------------+----------------------------------+ +| GPU | Intel HD Graphics 500 | ++------------------+----------------------------------+ +| Coprocessor | Intel TXE 3.0 | ++------------------+----------------------------------+ +| RAM | 8GB DDR3L | ++------------------+----------------------------------+ +| eMMC Flash | 32GB eMMC pSLC | ++------------------+----------------------------------+ +| USB3 | x2 | ++------------------+----------------------------------+ +| USB2 | x6 | ++------------------+----------------------------------+ +| SATA | x2 | ++------------------+----------------------------------+ +| LAN | Intel I210IT, I211AT | ++------------------+----------------------------------+ +| Super IO/EC | Kontron CPLD/EC | ++------------------+----------------------------------+ +| HWM | NCT7802 | ++------------------+----------------------------------+ +``` + +## Building coreboot + +The following commands will build a working image: + +```bash +make distclean +make defconfig KBUILD_DEFCONFIG=configs/config.kontron_mal10 +make +``` +## Payloads +- SeaBIOS +- Tianocore +- Linux as payload + +## Flashing coreboot + +The SPI flash can be accessed internally using [flashrom]. +The following command is used to flash BIOS region. + +```bash +$ flashrom -p internal --ifd -i bios -w coreboot.rom --noverify-all +``` + +## Hardware Monitor + +The Nuvoton [NCT7802Y] is a hardware monitoring IC, capable of monitor critical +system parameters including power supply voltages, fan speeds, and temperatures. +The remote inputs can be connected to CPU/GPU thermal diode or any thermal diode +sensors and thermistor. + +- 6 temperature sensors; +- 5 voltage sensors; +- 3 fan speed sensors; +- 4 sets of temperature setting points. + +PECI is not supported by Apollo Lake Pentium/Celeron/Atom processors and the CPU +temperature value is taken from a thermal resistor (NTC) that is placed very +close to the CPU. + +## Known issues + +- Works only with Tianocore "UEFIPayload" payload edk2-stable201903-1569-g3e63a91 + Booting with the "CorebootPayload" [crashes]. +- Tianocore outputs video through an external GPU only. + +## Untested + +- IGD/LVDS +- SDIO + +## Tested and working + +- Kontron CPLD/EC (Serial ports, I2C port) +- NCT7802 [HWM](#Hardware Monitor) +- USB2/3 +- Gigabit Ethernet ports +- eMMC +- SATA +- PCIe ports +- IGD/DP + +## TODO +- Onboard audio (codec IDT 92HD73C1X5, currently disabled) +- S3 suspend/resume + +[mAL10]: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-modules/com-express/com-express-mini/come-mal10-e2-.html +[W25Q128FV]: https://www.winbond.com/resource-files/w25q128fv%20rev.m%2005132016%20kms.pdf +[flashrom]: https://flashrom.org/Flashrom +[NCT7802Y]: https://www.nuvoton.com/products/cloud-computing/hardware-monitors/desktop-server-series/nct7802y/?__locale=en +[crashes]: https://pastebin.com/cpCfrPCL diff --git a/src/mainboard/kontron/mal10/Kconfig b/src/mainboard/kontron/mal10/Kconfig new file mode 100644 index 0000000000..1705b9109c --- /dev/null +++ b/src/mainboard/kontron/mal10/Kconfig @@ -0,0 +1,58 @@ +if BOARD_KONTRON_COME_MAL10 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select HAVE_ACPI_TABLES + select HAVE_ACPI_RESUME + select HAVE_OPTION_TABLE + select HAVE_CMOS_DEFAULT + select INTEL_GMA_HAVE_VBT + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select ONBOARD_VGA_IS_PRIMARY + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_HAS_CRB_TPM + select EC_KONTRON_KEMPLD + select DRIVERS_I2C_NCT7802Y + +config MAINBOARD_DIR + string + default "kontron/mal10" + +# TODO: Add a new carrier boards here +choice + prompt "Carrier board" + default BOARD_KONTRON_T10_TNI + help + This option sets the type of carrier board to be used with + the Kontron mAL10 COMe module. + +config BOARD_KONTRON_T10_TNI + bool "Kontron i-T10-TNIx" + help + By selecting this option, the target ROM image will be built for + the Kontron Ref.Carrier-i T10-TNI carrier board. + +endchoice + +config VARIANT_DIR + string + default "mal10" + +config CARRIER_DIR + string + default "t10-tni" if BOARD_KONTRON_T10_TNI + +config MAINBOARD_PART_NUMBER + string + default "COMe-mAL10" + +config DEVICETREE + string + default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb" + +config OVERRIDE_DEVICETREE + string + default "carriers/$(CONFIG_CARRIER_DIR)/overridetree.cb" + +endif diff --git a/src/mainboard/kontron/mal10/Kconfig.name b/src/mainboard/kontron/mal10/Kconfig.name new file mode 100644 index 0000000000..ac54165880 --- /dev/null +++ b/src/mainboard/kontron/mal10/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_KONTRON_COME_MAL10 + bool "COMe-mAL10" diff --git a/src/mainboard/kontron/mal10/Makefile.inc b/src/mainboard/kontron/mal10/Makefile.inc new file mode 100644 index 0000000000..885786fc55 --- /dev/null +++ b/src/mainboard/kontron/mal10/Makefile.inc @@ -0,0 +1,9 @@ +bootblock-y += bootblock.c +ramstage-y += ramstage.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += variants/$(VARIANT_DIR)/gma-mainboard.ads + +subdirs-y += variants/$(VARIANT_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include + +subdirs-y += carriers/$(CARRIER_DIR) +CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/carriers/$(CARRIER_DIR)/include diff --git a/src/mainboard/kontron/mal10/acpi/dptf.asl b/src/mainboard/kontron/mal10/acpi/dptf.asl new file mode 100644 index 0000000000..240da453bd --- /dev/null +++ b/src/mainboard/kontron/mal10/acpi/dptf.asl @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#define DPTF_CPU_PASSIVE 90 +#define DPTF_CPU_CRITICAL 105 + +Name (DTRT, Package () { + /* CPU Throttle Effect on CPU */ + Package () { \_SB.PCI0.TCPU, \_SB.PCI0.TCPU, 100, 100, 0, 0, 0, 0 }, +}) + +Name (MPPC, Package () +{ + 0x2, /* Revision */ + Package () { /* Power Limit 1 */ + 0, /* PowerLimitIndex, 0 for Power Limit 1 */ + 3000, /* PowerLimitMinimum */ + 10000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 200 /* StepSize */ + }, + + Package () { /* Power Limit 2 */ + 1, /* PowerLimitIndex, 1 for Power Limit 2 */ + 10000, /* PowerLimitMinimum */ + 15000, /* PowerLimitMaximum */ + 1000, /* TimeWindowMinimum */ + 1000, /* TimeWindowMaximum */ + 1000 /* StepSize */ + } +}) diff --git a/src/mainboard/kontron/mal10/board_info.txt b/src/mainboard/kontron/mal10/board_info.txt new file mode 100644 index 0000000000..d93d125911 --- /dev/null +++ b/src/mainboard/kontron/mal10/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Kontron +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/bootblock.c b/src/mainboard/kontron/mal10/bootblock.c new file mode 100644 index 0000000000..5c40e2dc6c --- /dev/null +++ b/src/mainboard/kontron/mal10/bootblock.c @@ -0,0 +1,26 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +static void init_cpld(void) +{ + /* Set up LPC decoding for CPLD I/O port ranges */ + lpc_open_pmio_window(0x0A80, 2); + + /* Enable console serial ports */ + lpc_io_setup_comm_a_b(); + kempld_enable_uart_for_console(); +} + +void bootblock_mainboard_early_init(void) +{ + variant_early_gpio_configure(); + init_cpld(); +} + +void bootblock_mainboard_init(void) +{ +} diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc b/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc new file mode 100644 index 0000000000..c291d45ebd --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/Makefile.inc @@ -0,0 +1 @@ +ramstage-y += gpio.c diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt b/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt new file mode 100644 index 0000000000..2902dc4b85 --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Kontron +Board name: COMe-Ref-Carrier-i-T10-TNI +Board URL: https://www.kontron.com/products/boards-and-standard-form-factors/com-express/starterkits-and-evaluation-boards/come-ref.carrier-i-t10-tni.html +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c new file mode 100644 index 0000000000..f1f93bf4fc --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/gpio.c @@ -0,0 +1,267 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "include/carrier/gpio.h" + +static const struct pad_config gpio_table[] = { + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_0, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_1, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_2, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_3, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_4, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_5, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_6, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_7, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_8, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_9, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_10, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_11, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_12, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_13, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_14, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_BIDIRECT(GPIO_15, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_16, 1, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_17, 1, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPI_TRIG_OWN(GPIO_18, UP_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_19, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_20, DN_20K, DEEP, OFF, TxDRxE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_21, UP_20K, DEEP, OFF, TxDRxE, DRIVER), + /* GPIO_22 - GPIO (DW0: 0x44800102, DW1: 0x00024100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_22, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER), */ + /* NEED TO IGNORE: PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_22, + PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)), + /* GPIO_23 - GPIO (DW0: 0x44800102, DW1: 0x00024100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_23, NONE, DEEP, OFF, TxDRxE, DISPUPD, DRIVER), */ + /* NEED TO IGNORE : PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_23, + PAD_RESET(DEEP) | PAD_TRIG(OFF) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD) | PAD_CFG_OWN_GPIO(DRIVER)), + /* GPIO_24 - GPIO (DW0: 0x40800102, DW1: 0x00027100) */ + /* PAD_CFG_GPI_TRIG_IOS_OWN(GPIO_24, UP_20K, DEEP, LEVEL, TxDRxE, DISPUPD, ACPI), */ + /* NEED TO IGNORE: PAD_RX_POL(INVERT) */ + _PAD_CFG_STRUCT(GPIO_24, + PAD_RESET(DEEP) | PAD_RX_POL(INVERT) | PAD_BUF(TX_DISABLE), + PAD_PULL(UP_20K) | PAD_IOSSTATE(TxDRxE) | PAD_IOSTERM(DISPUPD)), + PAD_CFG_GPI_SCI_IOS(GPIO_25, UP_20K, DEEP, LEVEL, INVERT, TxDRxE, DISPUPD), + PAD_CFG_NF(GPIO_26, NATIVE, DEEP, NF5), + PAD_CFG_GPI_SCI_IOS(GPIO_27, NONE, DEEP, EDGE_SINGLE, INVERT, TxDRxE, DISPUPD), + PAD_CFG_GPIO_BIDIRECT(GPIO_28, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_29, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_30, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_31, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_BIDIRECT(GPIO_32, 1, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_33, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_34, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_35, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_36, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_37, DN_20K, DEEP, HIZCRx0, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_38, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_39, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_40, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_41, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(GPIO_42, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_43, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_44, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_45, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_46, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_47, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_48, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_49, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_BIDIRECT(GPIO_62, 1, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT_IOS(GPIO_63, 0, UP_20K, DEEP, OFF, TxLASTRxE, ENPU, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_64, 0, DN_20K, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_BIDIRECT(GPIO_65, 0, NONE, DEEP, OFF, DRIVER), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_66, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_67, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_68, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_69, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_70, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_71, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_72, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_73, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(TCK, DN_20K, DEEP, NF1), + PAD_CFG_NF(TRST_B, DN_20K, DEEP, NF1), + PAD_CFG_NF(TMS, UP_20K, DEEP, NF1), + PAD_CFG_NF(TDI, UP_20K, DEEP, NF1), + PAD_CFG_NF(CX_PMODE, NONE, DEEP, NF1), + PAD_CFG_NF(CX_PREQ_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(JTAGX, UP_20K, DEEP, NF1), + PAD_CFG_NF(CX_PRDY_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(TDO, UP_20K, DEEP, NF1), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(CNV_BRI_DT, DN_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_TERM_GPO(CNV_BRI_RSP, 1, UP_20K, DEEP), + PAD_CFG_TERM_GPO(CNV_RGI_DT, 0, UP_20K, DEEP), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_187, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_188, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_189, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_190, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_191, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_192, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_193, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_194, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_195, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_196, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_197, NATIVE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_198, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_199, UP_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF(GPIO_200, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_201, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_202, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_203, UP_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_204, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS0, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS1, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_FS2, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_RXD, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_TXD, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMC_SPI_CLK, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_PWRGOOD, NONE, DEEP, NF1), + PAD_CFG_NF(PMIC_RESET_B, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_213, NONE, DEEP, NF1), + PAD_CFG_NF(GPIO_214, DN_20K, DEEP, NF1), + PAD_CFG_NF(GPIO_215, DN_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_THERMTRIP_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_STDBY, DN_20K, DEEP, NF1), + PAD_CFG_NF(PROCHOT_B, UP_20K, DEEP, NF1), + PAD_CFG_NF(PMIC_I2C_SCL, UP_1K, DEEP, NF1), + PAD_CFG_NF(PMIC_I2C_SDA, UP_1K, DEEP, NF1), + PAD_CFG_GPIO_HI_Z(GPIO_74, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_75, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_76, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_77, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_78, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_79, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_80, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_81, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_82, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_83, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_NF(GPIO_84, DN_20K, DEEP, NF2), + PAD_CFG_GPIO_HI_Z(GPIO_85, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_86, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_87, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_88, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_89, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_90, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_91, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_92, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_98, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), + PAD_CFG_NF(FST_SPI_CLK_FB, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_HI_Z(GPIO_104, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_105, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_106, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_109, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_110, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_111, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_112, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_113, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_116, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_117, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_118, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_119, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_120, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_121, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_122, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_HI_Z(GPIO_123, DN_20K, DEEP, TxLASTRxE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_124, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_125, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_126, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_127, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_128, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_129, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_130, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_131, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_132, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_133, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_134, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_135, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_SCI_IOS(GPIO_136, UP_20K, DEEP, EDGE_SINGLE, INVERT, TxDRxE, SAME), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_137, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_138, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_139, UP_20K, DEEP, OFF, IGNORE, DRIVER), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_146, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_147, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_148, DN_20K, DEEP, NF3), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_149, DN_20K, DEEP, NF3), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_150, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_151, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_152, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_153, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_154, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_155, DN_20K, DEEP, NF2), + PAD_CFG_NF(GPIO_209, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_211, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_212, NATIVE, DEEP, NF1), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_0, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_1, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_2, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_3, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(OSC_CLK_OUT_4, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_AC_PRESENT, DN_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_BATLOW_B, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PLTRST_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_PWRBTN_B, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_RESETBUTTON_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S0_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S3_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SLP_S4_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(PMU_SUSCLK, NONE, DEEP, NF1), + PAD_CFG_GPO_IOSSTATE_IOSTERM(PMU_WAKE_B, 0, DEEP, UP_20K, IGNORE, SAME), + PAD_CFG_NF_IOSTANDBY_IGNORE(SUS_STAT_B, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SUSPWRDNACK, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_205, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_206, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_207, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(GPIO_208, NONE, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_156, DN_20K, DEEP, NF1, Tx0RxDCRx0), + PAD_CFG_NF_IOSSTATE(GPIO_157, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_158, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_159, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_160, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_161, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_162, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_163, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_164, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_165, UP_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_166, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_167, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_168, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_169, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_170, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_GPIO_DRIVER_HI_Z(GPIO_171, DN_20K, DEEP, IGNORE, SAME), + PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_172, DN_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF(GPIO_179, DN_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_173, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_174, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_175, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF_IOSSTATE(GPIO_176, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_GPI_TRIG_IOSSTATE_OWN(GPIO_177, UP_20K, DEEP, EDGE_BOTH, TxDRxE, DRIVER), + PAD_CFG_NF_IOSSTATE(GPIO_178, DN_20K, DEEP, NF1, HIZCRx1), + PAD_CFG_NF(GPIO_186, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE(GPIO_182, DN_20K, DEEP, NF1, HIZCRx0), + PAD_CFG_TERM_GPO(GPIO_183, 1, DN_20K, DEEP), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_ALERTB, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_CLK, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), +}; + +void carrier_gpio_configure(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h b/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h new file mode 100644 index 0000000000..9c9c8edc83 --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/include/carrier/gpio.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef T10_TNI_CFG_GPIO_H +#define T10_TNI_CFG_GPIO_H + +#include +#include + +/* + * Bidirectional GPIO port when both RX and TX buffer is enabled + * TODO: move this macros to src/soc/intel/common/block/include/intelblocks/gpio_defs.h + */ +#ifndef PAD_CFG_GPIO_BIDIRECT_IOS +#define PAD_CFG_GPIO_BIDIRECT_IOS(pad, val, pull, rst, trig, iosstate, iosterm, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own) | \ + PAD_IOSSTATE(iosstate) | PAD_IOSTERM(iosterm)) +#endif + +#ifndef PAD_CFG_GPIO_BIDIRECT +#define PAD_CFG_GPIO_BIDIRECT(pad, val, pull, rst, trig, own) \ + _PAD_CFG_STRUCT(pad, \ + PAD_FUNC(GPIO) | PAD_RESET(rst) | PAD_TRIG(trig) | \ + PAD_BUF(NO_DISABLE) | val, \ + PAD_PULL(pull) | PAD_CFG_OWN_GPIO(own)) +#endif + +void carrier_gpio_configure(void); + +#endif /* T10_TNI_CFG_GPIO_H */ diff --git a/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb new file mode 100644 index 0000000000..9248c0c21c --- /dev/null +++ b/src/mainboard/kontron/mal10/carriers/t10-tni/overridetree.cb @@ -0,0 +1,42 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + # Override USB port configuration + register "usb_config_override" = "1" + # USB 2.0 + register "usb2_port[0]" = "PORT_EN(OC1)" + register "usb2_port[1]" = "PORT_EN(OC1)" + register "usb2_port[2]" = "PORT_EN(OC1)" + register "usb2_port[3]" = "PORT_EN(OC1)" + register "usb2_port[4]" = "PORT_EN(OC1)" + register "usb2_port[5]" = "PORT_EN(OC1)" + register "usb2_port[6]" = "PORT_EN(OC_SKIP)" + register "usb2_port[7]" = "PORT_EN(OC_SKIP)" + # USB 3.0 + register "usb3_port[0]" = "PORT_EN(OC0)" + register "usb3_port[1]" = "PORT_EN(OC0)" + + device domain 0 on + device pci 0e.0 off end # TODO: Audio + device pci 13.0 on # PCIe-A 1 (Root Port 2) + register "pcie_rp_clkreq_pin[2]" = "0" + end + device pci 13.1 on # PCIe-A 2 (Root Port 3) + register "pcie_rp_clkreq_pin[3]" = "0" + end + device pci 13.2 on # PCIe-A 3 (Root Port 4) + register "pcie_rp_clkreq_pin[4]" = "0" + end + device pci 13.3 on # PCIe-A 4 (Root Port 5) + register "pcie_rp_clkreq_pin[5]" = "0" + end + device pci 14.0 on # PCIe-B 1 (Root Port 0) + register "pcie_rp_clkreq_pin[0]" = "1" + end + end +end diff --git a/src/mainboard/kontron/mal10/cmos.default b/src/mainboard/kontron/mal10/cmos.default new file mode 100644 index 0000000000..55cac796c6 --- /dev/null +++ b/src/mainboard/kontron/mal10/cmos.default @@ -0,0 +1,6 @@ +baud_rate = 115200 +debug_level = Info +power_on_after_fail = Enable +boot_devices = (hd0,0);(hd1,0) +boot_default = 0xff +cmos_defaults_loaded = No diff --git a/src/mainboard/kontron/mal10/cmos.layout b/src/mainboard/kontron/mal10/cmos.layout new file mode 100644 index 0000000000..cc5359f4b7 --- /dev/null +++ b/src/mainboard/kontron/mal10/cmos.layout @@ -0,0 +1,55 @@ +# ----------------------------------------------------------------- +entries + +# ----------------------------------------------------------------- +0 120 r 0 reserved_memory + +# ----------------------------------------------------------------- +# coreboot config options: console +395 4 e 3 debug_level + +# ----------------------------------------------------------------- +# coreboot config options: cpu +400 1 e 2 hyper_threading + +# coreboot config options: pch +408 2 e 4 power_on_after_fail + +# coreboot config options: mainboard +440 1 e 2 ethernet1 +441 1 e 2 ethernet2 + +# payload config options +512 256 s 0 boot_devices +768 8 h 0 boot_default +776 1 e 1 cmos_defaults_loaded + +# coreboot config options: check sums +984 16 h 0 check_sum + +# ----------------------------------------------------------------- + +enumerations + +#ID value text +1 0 No +1 1 Yes +2 0 Disable +2 1 Enable +3 1 Emergency +3 2 Alert +3 3 Critical +3 4 Error +3 5 Warning +3 6 Notice +3 7 Info +3 8 Debug +3 9 Spew +4 0 Disable +4 1 Enable +4 2 Keep +# ----------------------------------------------------------------- + +checksums + +checksum 392 983 984 diff --git a/src/mainboard/kontron/mal10/dsdt.asl b/src/mainboard/kontron/mal10/dsdt.asl new file mode 100644 index 0000000000..78d2c285a5 --- /dev/null +++ b/src/mainboard/kontron/mal10/dsdt.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20110725 // OEM revision +) +{ + #include + #include + #include + + Scope (\_SB) + { + Device(PCI0) + { + #include + #include + } + #include "acpi/dptf.asl" + #include + #include + } +} diff --git a/src/mainboard/kontron/mal10/mal10.fmd b/src/mainboard/kontron/mal10/mal10.fmd new file mode 100644 index 0000000000..21d780a066 --- /dev/null +++ b/src/mainboard/kontron/mal10/mal10.fmd @@ -0,0 +1,21 @@ +FLASH 16M { + SI_DESC 0x1000 + SI_BIOS 0xefe000 { + IFWI 0x2ff000 + OBB 0xbff000 { + FMAP 0x1000 + UNIFIED_MRC_CACHE 0x21000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + RW_VAR_MRC_CACHE 0x1000 + } + CONSOLE 0x20000 + COREBOOT(CBFS) + BIOS_UNUSABLE 0x40000 + } + } + SI_DEVICEEXT 0x101000 { + DEVICE_EXTENSION 0x100000 + UNUSED_HOLE 0x1000 + } +} diff --git a/src/mainboard/kontron/mal10/ramstage.c b/src/mainboard/kontron/mal10/ramstage.c new file mode 100644 index 0000000000..48194e6848 --- /dev/null +++ b/src/mainboard/kontron/mal10/ramstage.c @@ -0,0 +1,47 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_silicon_init_params(FSP_S_CONFIG *silconfig) +{ + carrier_gpio_configure(); + + /* + * CPU Power Management Configuration correspond to the BIOS Setup menu settings + * in the AMI UEFI v112. + * TODO: move these FSP options to device tree + */ + silconfig->EnableCx = 1; /* Enable CPU power states */ + silconfig->C1e = 1; /* enable Enhanced C-states */ + /* + * Attention! Do not change PkgCStateLimit! This causes spikes in the power + * consumption of the SoC when the system comes out of power saving mode, and + * voltage sagging at the output of DC-DC converters on the COMe module. In the + * AMI BIOS Setup shows this parameter, but does not allow changing it. + */ + silconfig->PkgCStateLimit = 0; /* Max Pkg Cstate : PkgC0C1 */ + silconfig->MaxCoreCState = 3; /* Max Core C-State : C6 */ + silconfig->CStateAutoDemotion = 0; /* Disable C1 and C3 Auto-demotion */ + silconfig->CStateUnDemotion = 0; /* Disable C1 and C3 Un-demotion */ + silconfig->PkgCStateDemotion = 1; /* enable package Cstate demotion */ + silconfig->PkgCStateUnDemotion = 1; /* enable package Cstate undemotion */ + silconfig->PmSupport = 1; /* GT PM Support */ + silconfig->EnableRenderStandby = 1; /* enable render standby */ + silconfig->LPSS_S0ixEnable = 1; /* LPSS IOSF PMCTL S0ix Enable */ + silconfig->InitS3Cpu = 1; /* initialize CPU during S3 resume */ + + /* Override High Precision Timer options */ + silconfig->HpetBdfValid = 1; + silconfig->HpetBusNumber = 0xFA; + silconfig->HpetDeviceNumber = 0x0F; + silconfig->HpetFunctionNumber = 0; + + /* Override APIC options */ + silconfig->IoApicId = 1; + silconfig->IoApicBdfValid = 1; + silconfig->IoApicBusNumber = 0xFA; + silconfig->IoApicDeviceNumber = 0x1F; + silconfig->IoApicFunctionNumber = 0; +} diff --git a/src/mainboard/kontron/mal10/romstage.c b/src/mainboard/kontron/mal10/romstage.c new file mode 100644 index 0000000000..9f1d7eb87d --- /dev/null +++ b/src/mainboard/kontron/mal10/romstage.c @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + mupd->FspmConfig.Package = 0; + mupd->FspmConfig.Profile = 0x19; + mupd->FspmConfig.MemoryDown = 0; + mupd->FspmConfig.DDR3LPageSize = 2; + mupd->FspmConfig.DualRankSupportEnable = 0; + mupd->FspmConfig.RmtMode = 0; + mupd->FspmConfig.MemorySizeLimit = 0; + mupd->FspmConfig.DIMM0SPDAddress = 0xA0; + mupd->FspmConfig.DIMM1SPDAddress = 0xA4; + + mupd->FspmConfig.RmtCheckRun = 1; + mupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0; + mupd->FspmConfig.EnhancePort8xhDecoding = 1; + + mupd->FspmConfig.MsgLevelMask = 0; + mupd->FspmConfig.MrcDataSaving = 0; + mupd->FspmConfig.MrcFastBoot = 1; + + mupd->FspmConfig.PrimaryVideoAdaptor = 2; +} diff --git a/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc b/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc new file mode 100644 index 0000000000..4b48156a52 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/Makefile.inc @@ -0,0 +1 @@ +bootblock-y += gpio.c diff --git a/src/mainboard/kontron/mal10/variants/mal10/board_info.txt b/src/mainboard/kontron/mal10/variants/mal10/board_info.txt new file mode 100644 index 0000000000..ce668920f5 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/board_info.txt @@ -0,0 +1,8 @@ +Vendor name: Kontron +Board name: COMe-mAL10 +Board URL: https://www.kontron.com/products/iot/iot-industry-4.0/iot-ready-boards-and-modules/com-express/com-express-mini/come-mal10-e2-.html +Category: mini +ROM protocol: SPI +ROM socketed: n +Flashrom support: y +Release year: 2019 diff --git a/src/mainboard/kontron/mal10/variants/mal10/data.vbt b/src/mainboard/kontron/mal10/variants/mal10/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..25be67554883e19d352f4749dfad0b334693ee0a GIT binary patch literal 6154 zcmeHLU2GIp6h1T4{kt=>yPcwxQp@GXvMta~TUbi1cD7qe7h1a8mRf(3Zp$v(SZHaB z77;tfk~A@xeNcmjXpJ!%d}*RS86!Rzi9~51#PDPZF+m~;i5PtV)^lfuZdUsC~X=;`e0ju+R&`=1%;>80Udhz54#=1~-sAY4FOlAxr*weeeuj{F&2dFPt zKufWmbq21{Wg6`1>n);z?rz$|Z2D1Y54H$C7!Y`PQ7DHM87IK$qOiv0g-4Jh$R}+CzDNEM`Df%`k*^{<>;y8Amm)ui zT#UR4If&eV{3vnn*pyDfPU1E}5}GEGb&j07>JM zOgbEJE%{wGB$LjESr0Tsz+rPW7E+xh>kTOgVJqE&lKHC5N+*-9C?p^K`EP5O4IcAZg^197z`EQow zu+3rVFZ{TJz_?>1Yb49mE_44aZMM(mPA8L@7FoN)+@=d9_oN4M>)^CYPteH+yw2zf z(*=3Amb2_hJXv`TTzK;HV8abU!b7_T>L4)9wOGc%a?GkjGt zq^m_`lSqOh?Glv(A~__|k3{8jk$f%Ei=vVgiA$ozk`j=}Hi_<)l$RxPSfU?G%2yIO zCDGp`#UYbSnQoMokW89ox?fgak;&^a{Y+NAmB|k>y(%jnH(BDQRcMjsAHu_)jaH&U8$Un7sE0yHTQ2qKi%cKo z`G?E{4`&Lu^Z5~COF#=izM4JaHxaV^LxOQXLj;_0hER#uwYf*37Q>sG8cFHPr_e zDoE0xEhjC6K^n>NYTjuGT*7t}2p<*?PDXO_wYDRvK5z-UfuPyP(&$57m8N!%m1^4Y z6oTEn0ZFa4bUe9hdF!zV!Nd@5F(wTJ*+j6>G)8eD2S&qmu_~!SR?F~%kihk5c(UAx2NvXW zM>SueXYVavr?st1&4mCS0|7TN`~2&oK!d0bSy8Vylhrc&fcq(uR9_oz4|nW|cW>|5 z9seIB*q~<8nwP-7^#tC@kKMVi{>e;IX3^UF;BYN=D}*=o9T0{XtmWQ-^Fq-Wz{nKc z6>6EW3z#lm@5jhZU?3T5YNp%qRH;G+V0#dIm5f`DHntW$L(8fbp)Z(E=Az0XRzH@3HbbHk5Hr1Ldz-NEqMF(N7!Y~{EcMYyq21onVQ`oKZgrvffhV) z4|`xE&*^{{5*=S*DblA@^GwOcmkZNG5!|_j<+UxHUA@okKXC9x-KoR7@Z}%pE}c7n wZc;eA@@()-{LG<=_a{D>xHvI|GLK@kucnMR{I|&> Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/kontron/mal10/variants/mal10/gpio.c b/src/mainboard/kontron/mal10/variants/mal10/gpio.c new file mode 100644 index 0000000000..1e88e38e5f --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/gpio.c @@ -0,0 +1,36 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "include/variant/gpio.h" + +static const struct pad_config gpio_table[] = { + /* SPI */ + PAD_CFG_NF(GPIO_97, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_98, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_99, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_100, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_101, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_102, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_103, NATIVE, DEEP, NF1), + PAD_CFG_NF(FST_SPI_CLK_FB, NATIVE, DEEP, NF1), + + /* SMBUS */ + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_ALERTB, NONE, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_CLK, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSTANDBY_IGNORE(SMB_DATA, UP_20K, DEEP, NF1), + + /* LPC */ + PAD_CFG_NF_IOSTANDBY_IGNORE(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT0, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKOUT1, NONE, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD0, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD1, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD2, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_AD3, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_CLKRUNB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), + PAD_CFG_NF_IOSSTATE_IOSTERM(LPC_FRAMEB, UP_20K, DEEP, NF1, HIZCRx1, DISPUPD), +}; + +void variant_early_gpio_configure(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h b/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h new file mode 100644 index 0000000000..d97e199fb8 --- /dev/null +++ b/src/mainboard/kontron/mal10/variants/mal10/include/variant/gpio.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAL_10_CFG_GPIO_H +#define MAL_10_CFG_GPIO_H + +#include +#include + +void variant_early_gpio_configure(void); + +#endif /* MAL_10_CFG_GPIO_H */ From 6d4de7eef9d22017bd592a0a35c30a9756393aa3 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 20 Nov 2020 18:28:38 +0100 Subject: [PATCH 054/107] payloads/external/Makefile.inc: Fix SeaBIOS option regressions Commit 14ca7407196 (Makefile.inc: Move adding SeaBIOS cbfs config files) introduced various regressions that were not spotted during review. TEST=Building with SEABIOS_THREAD_OPTIONROMS is working properly again. Change-Id: I4de0b11747e3df8dd31a85160add129d8cc6bd8a Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47814 Reviewed-by: Arthur Heymans Reviewed-by: Nico Huber Tested-by: build bot (Jenkins) --- payloads/external/Makefile.inc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 6208578b74..0300581ea4 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -121,14 +121,14 @@ ifeq ($(CONFIG_SEABIOS_ADD_SERCON_PORT_FILE),y) INTERMEDIATE+=seabios_sercon seabios_sercon: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Add sercon-port file\n" -# $(CBFSTOOL) $@.tmp add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port + $(CBFSTOOL) $< add-int -i $(CONFIG_SEABIOS_SERCON_PORT_ADDR) -n etc/sercon-port endif ifeq ($(CONFIG_SEABIOS_THREAD_OPTIONROMS),y) INTERMEDIATE+=seabios_thread_optionroms seabios_thread_optionroms: $(obj)/coreboot.pre $(CBFSTOOL) @printf " SeaBIOS Thread optionroms\n" - $(CBFSTOOL) $@.tmp add-int -i 2 -n etc/threads + $(CBFSTOOL) $< add-int -i 2 -n etc/threads endif # Depthcharge From 2687d37a3cf514a8e50c7567a9b0566736e7fe1f Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 20 Nov 2020 18:32:45 +0100 Subject: [PATCH 055/107] payloads/external: Fix up SPDX license headers Remove copyright notices and other unnecessary churn. Change-Id: Ie69cc121d2b6eed95aa3cbaa7215d61880148858 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47815 Reviewed-by: Nico Huber Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- payloads/external/LinuxBoot/Kconfig | 4 ---- payloads/external/LinuxBoot/Kconfig.name | 3 --- payloads/external/LinuxBoot/Makefile | 4 ---- payloads/external/LinuxBoot/targets/linux.mk | 4 ---- payloads/external/LinuxBoot/targets/u-root.mk | 4 ---- payloads/external/Makefile.inc | 7 ------- payloads/external/Memtest86Plus/Makefile | 4 ---- payloads/external/U-Boot/Makefile | 4 ---- payloads/external/Yabits/Makefile | 4 ---- payloads/external/iPXE/Kconfig | 2 -- payloads/external/iPXE/Makefile | 4 ---- payloads/external/tianocore/Makefile | 4 ---- 12 files changed, 48 deletions(-) diff --git a/payloads/external/LinuxBoot/Kconfig b/payloads/external/LinuxBoot/Kconfig index 6171217ee2..c2689e1871 100644 --- a/payloads/external/LinuxBoot/Kconfig +++ b/payloads/external/LinuxBoot/Kconfig @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only if PAYLOAD_LINUXBOOT diff --git a/payloads/external/LinuxBoot/Kconfig.name b/payloads/external/LinuxBoot/Kconfig.name index 013873269f..4d3decd923 100644 --- a/payloads/external/LinuxBoot/Kconfig.name +++ b/payloads/external/LinuxBoot/Kconfig.name @@ -1,6 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## ## SPDX-License-Identifier: GPL-2.0-only config PAYLOAD_LINUXBOOT diff --git a/payloads/external/LinuxBoot/Makefile b/payloads/external/LinuxBoot/Makefile index 45b1764932..c91b1d43da 100644 --- a/payloads/external/LinuxBoot/Makefile +++ b/payloads/external/LinuxBoot/Makefile @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only project_dir=linuxboot diff --git a/payloads/external/LinuxBoot/targets/linux.mk b/payloads/external/LinuxBoot/targets/linux.mk index 5dec401e1a..990672936d 100644 --- a/payloads/external/LinuxBoot/targets/linux.mk +++ b/payloads/external/LinuxBoot/targets/linux.mk @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only SHELL := /bin/bash diff --git a/payloads/external/LinuxBoot/targets/u-root.mk b/payloads/external/LinuxBoot/targets/u-root.mk index 07c453d65b..0cf91fec5b 100644 --- a/payloads/external/LinuxBoot/targets/u-root.mk +++ b/payloads/external/LinuxBoot/targets/u-root.mk @@ -1,7 +1,3 @@ -## -## Copyright (C) 2017 Facebook Inc. -## Copyright (C) 2018 9elements Cyber Security -## ## SPDX-License-Identifier: GPL-2.0-only project_dir=$(shell pwd)/linuxboot diff --git a/payloads/external/Makefile.inc b/payloads/external/Makefile.inc index 0300581ea4..823cd87ddf 100644 --- a/payloads/external/Makefile.inc +++ b/payloads/external/Makefile.inc @@ -1,10 +1,3 @@ -################################################################################ -## -## -## Copyright (C) 2009-2010 coresystems GmbH -## Copyright (C) 2015 Google Inc. -## Copyright (C) 2017 Facebook Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # set up payload config and version files for later inclusion diff --git a/payloads/external/Memtest86Plus/Makefile b/payloads/external/Memtest86Plus/Makefile index 5aec5c8156..3853cb9586 100644 --- a/payloads/external/Memtest86Plus/Makefile +++ b/payloads/external/Memtest86Plus/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2016 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only TAG-$(CONFIG_MEMTEST_MASTER)=origin/master diff --git a/payloads/external/U-Boot/Makefile b/payloads/external/U-Boot/Makefile index 6d186ad1c9..38dfe99a0e 100644 --- a/payloads/external/U-Boot/Makefile +++ b/payloads/external/U-Boot/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2015 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # 2019-4 tag diff --git a/payloads/external/Yabits/Makefile b/payloads/external/Yabits/Makefile index 74f00efa65..adac77e810 100644 --- a/payloads/external/Yabits/Makefile +++ b/payloads/external/Yabits/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2016 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only TAG-$(CONFIG_YABITS_MASTER)=origin/master diff --git a/payloads/external/iPXE/Kconfig b/payloads/external/iPXE/Kconfig index 0b81d183e9..6c8049a3d7 100644 --- a/payloads/external/iPXE/Kconfig +++ b/payloads/external/iPXE/Kconfig @@ -1,5 +1,3 @@ -## -## ## SPDX-License-Identifier: GPL-2.0-only config PXE diff --git a/payloads/external/iPXE/Makefile b/payloads/external/iPXE/Makefile index 2a9e8c9b64..3e12f611a1 100644 --- a/payloads/external/iPXE/Makefile +++ b/payloads/external/iPXE/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2016 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # 2019.3 - Last commit of March 2019 diff --git a/payloads/external/tianocore/Makefile b/payloads/external/tianocore/Makefile index 9945411880..3d3a3dd748 100644 --- a/payloads/external/tianocore/Makefile +++ b/payloads/external/tianocore/Makefile @@ -1,7 +1,3 @@ -## -## -## Copyright (C) 2017 Google Inc. -## ## SPDX-License-Identifier: GPL-2.0-only # force the shell to bash - the edksetup.sh script doesn't work with dash From 5ea7bb74bdca5047407993c7564d1f23ccf2dc1a Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 20 Nov 2020 16:18:16 +0100 Subject: [PATCH 056/107] Doc/releases/checklist.md: Add reminder to unpack relnotes Explicitly add this easy-to-forget step. Also add a missing period. Change-Id: Iaf13155fcc8a70f3565fb2404cef886524fa5161 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47811 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Documentation/releases/checklist.md | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index a80fd85804..1cfb1100c8 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -75,7 +75,8 @@ be more frequent than was needed, so we scaled it back to twice a year. - [ ] Test the release from the actual release tarballs. - [ ] Push signed Tag to repo. - [ ] Announce that the release tag is done on IRC. -- [ ] Upload release files to web server +- [ ] Upload release files to web server. +- [ ] Also extract the release notes and place them on the web server. - [ ] Upload crossgcc sources to web server. - [ ] Update download page to point to files, push to repo. - [ ] Write and publish blog post with release notes. From c930c87998c5182059fcdc8adea98779df9ce629 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Fri, 20 Nov 2020 16:27:26 +0100 Subject: [PATCH 057/107] Doc/releases/checklist.md: Fix up URLs Use angle brackets so that they appear as links, and update a link to a Gerrit change to use the current format. Change-Id: I41f82986429dcfd1cbc5b5c088a0c47bd24a57c4 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47812 Reviewed-by: Patrick Georgi Tested-by: build bot (Jenkins) --- Documentation/releases/checklist.md | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/Documentation/releases/checklist.md b/Documentation/releases/checklist.md index 1cfb1100c8..d777f0e38b 100644 --- a/Documentation/releases/checklist.md +++ b/Documentation/releases/checklist.md @@ -198,16 +198,16 @@ the coreboot server, and put them in the release directory at ```` People can now see the release tarballs on the website at -https://www.coreboot.org/releases/ + -The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at https://review.coreboot.org/cgit/homepage.git/tree/downloads.html +The downloads page is the official place to download the releases from, and it needs to be updated with links to the new release tarballs and .sig files. It can be found at -Here is an example commit to change it: https://review.coreboot.org/#/c/19515/ +Here is an example commit to change it: ## Upload crossgcc sources Sometimes the source files for older revisions of crossgcc disappear. To deal with that we maintain a mirror at -https://www.coreboot.org/releases/crossgcc-sources/ where we host the + where we host the sources used by the crossgcc scripts that are part of coreboot releases. Run @@ -221,7 +221,7 @@ sources. Download them yourself and copy them into the crossgcc-sources directory on the server. ## After the release is complete -Post the release notes on https://blogs.coreboot.org +Post the release notes on ## Making a branch At times we will need to create a branch, generally for patch fixes. From f9ed4d20f16facc486b960e0372d7a9dc0490c81 Mon Sep 17 00:00:00 2001 From: Eric Lai Date: Mon, 16 Nov 2020 15:38:53 +0800 Subject: [PATCH 058/107] drivers/i2c: Add a driver for Semtech SX9324 This adds a new driver for the SX9324 proximity detector device. Follow SX9324 datasheet Rev3. BUG=b:172397658 BRANCH=zork TEST=Test sx9324 is working as expected. Signed-off-by: Eric Lai Change-Id: Ifd582482728a2f535ed85f6696b2f5a4529ba421 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47640 Reviewed-by: Tim Wawrzynczak Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/i2c/sx9324/Kconfig | 6 ++ src/drivers/i2c/sx9324/Makefile.inc | 1 + src/drivers/i2c/sx9324/chip.h | 31 +++++++++ src/drivers/i2c/sx9324/registers.h | 50 +++++++++++++ src/drivers/i2c/sx9324/sx9324.c | 104 ++++++++++++++++++++++++++++ 5 files changed, 192 insertions(+) create mode 100644 src/drivers/i2c/sx9324/Kconfig create mode 100644 src/drivers/i2c/sx9324/Makefile.inc create mode 100644 src/drivers/i2c/sx9324/chip.h create mode 100644 src/drivers/i2c/sx9324/registers.h create mode 100644 src/drivers/i2c/sx9324/sx9324.c diff --git a/src/drivers/i2c/sx9324/Kconfig b/src/drivers/i2c/sx9324/Kconfig new file mode 100644 index 0000000000..77f6967b7e --- /dev/null +++ b/src/drivers/i2c/sx9324/Kconfig @@ -0,0 +1,6 @@ +config DRIVERS_I2C_SX9324 + bool + default n + depends on HAVE_ACPI_TABLES + help + Board has a Semtech SX9324 proximity sensor. diff --git a/src/drivers/i2c/sx9324/Makefile.inc b/src/drivers/i2c/sx9324/Makefile.inc new file mode 100644 index 0000000000..8811c996b0 --- /dev/null +++ b/src/drivers/i2c/sx9324/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_SX9324) += sx9324.c diff --git a/src/drivers/i2c/sx9324/chip.h b/src/drivers/i2c/sx9324/chip.h new file mode 100644 index 0000000000..9c9dd3cf35 --- /dev/null +++ b/src/drivers/i2c/sx9324/chip.h @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __DRIVERS_I2C_SX9324_CHIP_H__ +#define __DRIVERS_I2C_SX9324_CHIP_H__ + +#include +#include + +#define REGISTER(NAME) uint8_t NAME + +struct drivers_i2c_sx9324_config { + /* Device Description */ + const char *desc; + + /* ACPI _UID */ + unsigned int uid; + + /* Bus speed in Hz, default is I2C_SPEED_FAST */ + enum i2c_speed speed; + + /* Use GPIO-based interrupt instead of IO-APIC */ + struct acpi_gpio irq_gpio; + + /* IO-APIC interrupt */ + struct acpi_irq irq; +#include "registers.h" +}; + +#undef REGISTER + +#endif /* __DRIVERS_I2C_SX9324_CHIP_H__ */ diff --git a/src/drivers/i2c/sx9324/registers.h b/src/drivers/i2c/sx9324/registers.h new file mode 100644 index 0000000000..160e5e7b05 --- /dev/null +++ b/src/drivers/i2c/sx9324/registers.h @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef REGISTER +#error "define REGISTER(NAME) before including this file" +#endif + +REGISTER(reg_gnrl_ctrl0); +REGISTER(reg_gnrl_ctrl1); + +REGISTER(reg_afe_ctrl0); +REGISTER(reg_afe_ctrl1); +REGISTER(reg_afe_ctrl2); +REGISTER(reg_afe_ctrl3); +REGISTER(reg_afe_ctrl4); +REGISTER(reg_afe_ctrl5); +REGISTER(reg_afe_ctrl6); +REGISTER(reg_afe_ctrl7); +REGISTER(reg_afe_ctrl8); +REGISTER(reg_afe_ctrl9); + +REGISTER(reg_prox_ctrl0); +REGISTER(reg_prox_ctrl1); +REGISTER(reg_prox_ctrl2); +REGISTER(reg_prox_ctrl3); +REGISTER(reg_prox_ctrl4); +REGISTER(reg_prox_ctrl5); +REGISTER(reg_prox_ctrl6); +REGISTER(reg_prox_ctrl7); + +REGISTER(reg_adv_ctrl0); +REGISTER(reg_adv_ctrl1); +REGISTER(reg_adv_ctrl2); +REGISTER(reg_adv_ctrl3); +REGISTER(reg_adv_ctrl4); +REGISTER(reg_adv_ctrl5); +REGISTER(reg_adv_ctrl6); +REGISTER(reg_adv_ctrl7); +REGISTER(reg_adv_ctrl8); +REGISTER(reg_adv_ctrl9); +REGISTER(reg_adv_ctrl10); +REGISTER(reg_adv_ctrl11); +REGISTER(reg_adv_ctrl12); +REGISTER(reg_adv_ctrl13); +REGISTER(reg_adv_ctrl14); +REGISTER(reg_adv_ctrl15); +REGISTER(reg_adv_ctrl16); +REGISTER(reg_adv_ctrl17); +REGISTER(reg_adv_ctrl18); +REGISTER(reg_adv_ctrl19); +REGISTER(reg_adv_ctrl20); diff --git a/src/drivers/i2c/sx9324/sx9324.c b/src/drivers/i2c/sx9324/sx9324.c new file mode 100644 index 0000000000..2ca9f36345 --- /dev/null +++ b/src/drivers/i2c/sx9324/sx9324.c @@ -0,0 +1,104 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include "chip.h" + +#define I2C_SX9324_ACPI_ID "STH9324" +#define I2C_SX9324_CHIP_NAME "Semtech SX9324" + +#define REGISTER(NAME) acpi_dp_add_integer(dsd, \ + I2C_SX9324_ACPI_ID "," #NAME, \ + config->NAME) + +static void i2c_sx9324_fill_ssdt(const struct device *dev) +{ + struct drivers_i2c_sx9324_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dsd; + + if (!scope || !config) + return; + + if (config->speed) + i2c.speed = config->speed; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", I2C_SX9324_ACPI_ID); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(acpi_device_status(dev)); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + + if (config->irq_gpio.pin_count) + acpi_device_write_gpio(&config->irq_gpio); + else + acpi_device_write_interrupt(&config->irq); + + acpigen_write_resourcetemplate_footer(); + + /* DSD */ + dsd = acpi_dp_new_table("_DSD"); +#include "registers.h" + acpi_dp_write(dsd); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s at %s\n", acpi_device_path(dev), + config->desc ? : dev->chip_ops->name, dev_path(dev)); +} + +#undef REGISTER + +static const char *i2c_sx9324_acpi_name(const struct device *dev) +{ + static char name[5]; + + snprintf(name, sizeof(name), "SX%02.2X", dev->path.i2c.device); + return name; +} + +static struct device_operations i2c_sx9324_ops = { + .read_resources = noop_read_resources, + .set_resources = noop_set_resources, + .acpi_name = i2c_sx9324_acpi_name, + .acpi_fill_ssdt = i2c_sx9324_fill_ssdt, +}; + +static void i2c_sx9324_enable(struct device *dev) +{ + struct drivers_i2c_sx9324_config *config = dev->chip_info; + + if (!config) { + dev->enabled = 0; + return; + } + + dev->ops = &i2c_sx9324_ops; + + if (config->desc) + dev->name = config->desc; +} + +struct chip_operations drivers_i2c_sx9324_ops = { + CHIP_NAME(I2C_SX9324_CHIP_NAME) + .enable_dev = i2c_sx9324_enable +}; From 9226fe9aee7c06bce69881ca41393fdc8964f08f Mon Sep 17 00:00:00 2001 From: Paul Menzel Date: Thu, 19 Nov 2020 17:04:20 +0100 Subject: [PATCH 059/107] =?UTF-8?q?Documentation:=20Mention=20newer=20Inte?= =?UTF-8?q?l=20=CE=BC-code=20updates=20in=204.13=20release=20notes?= MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Start a new section *Notes* for these kind of information. Change-Id: I86be22cebb96e6f07676a9bc52794a4c12dad3e4 Signed-off-by: Paul Menzel Reviewed-on: https://review.coreboot.org/c/coreboot/+/47762 Reviewed-by: Michael Niewöhner Tested-by: build bot (Jenkins) --- .../releases/coreboot-4.13-relnotes.md | 24 +++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/Documentation/releases/coreboot-4.13-relnotes.md b/Documentation/releases/coreboot-4.13-relnotes.md index ae973d401c..971d438ee0 100644 --- a/Documentation/releases/coreboot-4.13-relnotes.md +++ b/Documentation/releases/coreboot-4.13-relnotes.md @@ -234,3 +234,27 @@ to ensure that the platforms listed above are fixed before the next release. If is interest in maintaining support for these platforms beyond the next release, please ensure that the platforms are fixed to conform to the expectations of resource allocation. + +Notes +----- + +### Intel microcode updates + +Intel microcode updates tagged *microcode-20200616* are still included in our +builds. Note, [Intel released new microcode updates] +(https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/blob/main/releasenote.md) +tagged + +1. *microcode-20201110* +2. *microcode-20201112* +3. *microcode-20201118* + +with security updates for [INTEL-SA-00381] +(https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00381.html) +and [INTEL-SA-00389] +(https://www.intel.com/content/www/us/en/security-center/advisory/intel-sa-00389.html). + +Due to too short time for rigorous testing and bad experience with botched +microcode updates in the past, these new updates are not included. Users wanting +to use those, can apply them in the operating system, or update the submodule +pointer themselves. From 86dce8fa75233c9e6639962e0f402adcd6530e66 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 19 Nov 2020 18:29:44 -0600 Subject: [PATCH 060/107] drivers/i2c/generic: Only write DDN field if description not empty DDN field isn't required, no point in writing an empty string to it. Change-Id: Ifea6e48c324598f114178e86a79f519ee35f5258 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47781 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/i2c/generic/generic.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/src/drivers/i2c/generic/generic.c b/src/drivers/i2c/generic/generic.c index cd7406893b..1c7267e897 100644 --- a/src/drivers/i2c/generic/generic.c +++ b/src/drivers/i2c/generic/generic.c @@ -72,7 +72,8 @@ void i2c_generic_fill_ssdt(const struct device *dev, if (config->cid) acpigen_write_name_string("_CID", config->cid); acpigen_write_name_integer("_UID", config->uid); - acpigen_write_name_string("_DDN", config->desc); + if (config->desc) + acpigen_write_name_string("_DDN", config->desc); acpigen_write_STA(acpi_device_status(dev)); /* Resources */ From 3d62781acb3ab7d2496d73b2198bb7e7dcf496c6 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Thu, 19 Nov 2020 18:31:17 -0600 Subject: [PATCH 061/107] drivers/i2c/hid: Use ACPI device name if provided by config Follow model of drivers/i2c/generic and use user-supplied device name if specified in the chip config. Change-Id: Ia783bac2797e239989c03a3421b9293a055db3d0 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/47782 Reviewed-by: Furquan Shaikh Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/i2c/hid/hid.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/drivers/i2c/hid/hid.c b/src/drivers/i2c/hid/hid.c index 0755852d94..2d213eb74e 100644 --- a/src/drivers/i2c/hid/hid.c +++ b/src/drivers/i2c/hid/hid.c @@ -28,6 +28,10 @@ static void i2c_hid_fill_ssdt_generator(const struct device *dev) static const char *i2c_hid_acpi_name(const struct device *dev) { static char name[5]; + struct drivers_i2c_hid_config *config = dev->chip_info; + if (config->generic.name) + return config->generic.name; + snprintf(name, sizeof(name), "H%03.3X", dev->path.i2c.device); name[4] = '\0'; return name; From 7e3bf0c5dd712864279fd90e83d7fe57386a7547 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Fri, 20 Nov 2020 08:17:31 +0100 Subject: [PATCH 062/107] mb/facebook/fbg1701: Add VBOOT support Add VBOOT support. Disable USE_VENDOR_ELTAN when VBOOT is enabled. Add FMD file and split binary into RW and RO region settings. Tested on Facebook FBG1701 Signed-off-by: Frans Hendriks Change-Id: I641bca58c0f7c81d5742235c8b2c184d13c00c55 Reviewed-on: https://review.coreboot.org/c/coreboot/+/46219 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Wim Vervoorn --- src/mainboard/facebook/fbg1701/Kconfig | 30 ++++++++++++++++++++- src/mainboard/facebook/fbg1701/vboot-rw.fmd | 21 +++++++++++++++ 2 files changed, 50 insertions(+), 1 deletion(-) create mode 100644 src/mainboard/facebook/fbg1701/vboot-rw.fmd diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 0f23ed2a0a..411033754a 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -20,7 +20,35 @@ config BOARD_SPECIFIC_OPTIONS select DISABLE_HPET select INTEL_GMA_HAVE_VBT select HAVE_SPD_IN_CBFS - select USE_VENDORCODE_ELTAN + +config USE_VENDORCODE_ELTAN + depends on !VBOOT + default y + +if VBOOT + +config VBOOT_VBNV_CMOS + default y + +config VBOOT_SLOTS_RW_A + default y + +config VBOOT_NO_BOARD_SUPPORT + default y + +config VBOOT_ENABLE_CBFS_FALLBACK + default y + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/vboot-rw.fmd" + +config RW_REGION_ONLY + default "%/payload logo.bmp %/ramstage vbt.bin %/dsdt.aml config %/postcar" + +config RO_REGION_ONLY + default "spd.bin fsp.bin cpu_microcode_blob.bin" + +endif # VBOOT config ONBOARD_SAMSUNG_MEM bool "Onboard memory manufacturer Samsung" diff --git a/src/mainboard/facebook/fbg1701/vboot-rw.fmd b/src/mainboard/facebook/fbg1701/vboot-rw.fmd new file mode 100644 index 0000000000..51ee470cc4 --- /dev/null +++ b/src/mainboard/facebook/fbg1701/vboot-rw.fmd @@ -0,0 +1,21 @@ +FLASH 8M { + SI_BIOS@0x200000 0x600000 { + MISC_RW@0x0 0x08000 { + RW_MRC_CACHE@0 0x08000 + } + RW_SECTION_A@0x08000 0x578000 { + VBLOCK_A@0x0 0x10000 + RW_FWID_A@0x10000 0x40 + FW_MAIN_A(CBFS)@0x10040 0x567FC0 + } + WP_RO@0x580000 0x080000 { + RO_SECTION@0x0000 0x80000 { + FMAP@0x0 0x400 + RO_FRID@0xA00 0x40 + RO_FRID_PAD@0xA40 0x5c0 + GBB@0x1000 0x4000 + COREBOOT(CBFS)@0x5000 0x07B000 + } + } + } +} From c681a82657185996053deae28555d1871d227912 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 16 Nov 2020 17:19:17 -0700 Subject: [PATCH 063/107] cpu/amd/pi: Remove unused cpu code 00660F01 Remove the processor directory and references to the Kconfig symbol. Signed-off-by: Martin Roth Change-Id: I403a453362fd76d6ef2a5b75728a362efa4f2491 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47652 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/amd/pi/00660F01/Kconfig | 13 --- src/cpu/amd/pi/00660F01/Makefile.inc | 14 --- src/cpu/amd/pi/00660F01/acpi/cpu.asl | 48 --------- src/cpu/amd/pi/00660F01/chip_name.c | 7 -- src/cpu/amd/pi/00660F01/fixme.c | 55 ---------- src/cpu/amd/pi/00660F01/model_15_init.c | 119 --------------------- src/cpu/amd/pi/Kconfig | 2 - src/cpu/amd/pi/Makefile.inc | 1 - src/northbridge/amd/agesa/state_machine.h | 3 - src/southbridge/amd/pi/hudson/Kconfig | 3 +- src/southbridge/amd/pi/hudson/Makefile.inc | 12 --- src/vendorcode/amd/pi/Kconfig | 4 +- src/vendorcode/amd/pi/Makefile.inc | 11 +- 13 files changed, 3 insertions(+), 289 deletions(-) delete mode 100644 src/cpu/amd/pi/00660F01/Kconfig delete mode 100644 src/cpu/amd/pi/00660F01/Makefile.inc delete mode 100644 src/cpu/amd/pi/00660F01/acpi/cpu.asl delete mode 100644 src/cpu/amd/pi/00660F01/chip_name.c delete mode 100644 src/cpu/amd/pi/00660F01/fixme.c delete mode 100644 src/cpu/amd/pi/00660F01/model_15_init.c diff --git a/src/cpu/amd/pi/00660F01/Kconfig b/src/cpu/amd/pi/00660F01/Kconfig deleted file mode 100644 index 1cdfb1d7be..0000000000 --- a/src/cpu/amd/pi/00660F01/Kconfig +++ /dev/null @@ -1,13 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config CPU_AMD_PI_00660F01 - bool - select X86_AMD_FIXED_MTRRS - -if CPU_AMD_PI_00660F01 - -config CPU_ADDR_BITS - int - default 48 - -endif diff --git a/src/cpu/amd/pi/00660F01/Makefile.inc b/src/cpu/amd/pi/00660F01/Makefile.inc deleted file mode 100644 index 69635fc1f2..0000000000 --- a/src/cpu/amd/pi/00660F01/Makefile.inc +++ /dev/null @@ -1,14 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -romstage-y += fixme.c -ramstage-y += fixme.c -ramstage-y += chip_name.c -ramstage-y += model_15_init.c - -subdirs-y += ../../mtrr -subdirs-y += ../../../x86/tsc -subdirs-y += ../../../x86/lapic -subdirs-y += ../../../x86/cache -subdirs-y += ../../../x86/mtrr -subdirs-y += ../../../x86/pae -subdirs-y += ../../../x86/smm diff --git a/src/cpu/amd/pi/00660F01/acpi/cpu.asl b/src/cpu/amd/pi/00660F01/acpi/cpu.asl deleted file mode 100644 index ede5021e03..0000000000 --- a/src/cpu/amd/pi/00660F01/acpi/cpu.asl +++ /dev/null @@ -1,48 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* - * Processor Object - * - */ -Scope (\_SB) { /* define processor scope */ - - Device (P000) { - Name(_HID, "ACPI0007") - Name(_UID, 0) - } - - Device (P001) { - Name(_HID, "ACPI0007") - Name(_UID, 1) - } - - Device (P002) { - Name(_HID, "ACPI0007") - Name(_UID, 2) - } - - Device (P003) { - Name(_HID, "ACPI0007") - Name(_UID, 3) - } - - Device (P004) { - Name(_HID, "ACPI0007") - Name(_UID, 4) - } - - Device (P005) { - Name(_HID, "ACPI0007") - Name(_UID, 5) - } - - Device (P006) { - Name(_HID, "ACPI0007") - Name(_UID, 6) - } - - Device (P007) { - Name(_HID, "ACPI0007") - Name(_UID, 7) - } -} /* End _SB scope */ diff --git a/src/cpu/amd/pi/00660F01/chip_name.c b/src/cpu/amd/pi/00660F01/chip_name.c deleted file mode 100644 index 06fa4442ec..0000000000 --- a/src/cpu/amd/pi/00660F01/chip_name.c +++ /dev/null @@ -1,7 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include - -struct chip_operations cpu_amd_pi_00660F01_ops = { - CHIP_NAME("AMD CPU Family 15h Model 60h-6Fh") -}; diff --git a/src/cpu/amd/pi/00660F01/fixme.c b/src/cpu/amd/pi/00660F01/fixme.c deleted file mode 100644 index 9b208ecc4c..0000000000 --- a/src/cpu/amd/pi/00660F01/fixme.c +++ /dev/null @@ -1,55 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include - -void amd_initcpuio(void) -{ - UINT64 MsrReg; - UINT32 PciData; - PCI_ADDR PciAddress; - AMD_CONFIG_PARAMS StdHeader; - - /* Enable legacy video routing: D18F1xF4 VGA Enable */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xF4); - PciData = 1; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* The platform BIOS needs to ensure the memory ranges of SB800 legacy - * devices (TPM, HPET, BIOS RAM, Watchdog Timer, I/O APIC and ACPI) are - * set to non-posted regions. - */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x84); - /* last address before processor local APIC at FEE00000 */ - PciData = 0x00FEDF00; - /* set NP (non-posted) bit */ - PciData |= 1 << 7; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x80); - /* lowest NP address is HPET at FED00000 */ - PciData = (0xFED00000 >> 8) | 3; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Map the remaining PCI hole as posted MMIO */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x8C); - PciData = 0x00FECF00; /* last address before non-posted range */ - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - LibAmdMsrRead(TOP_MEM, &MsrReg, &StdHeader); - MsrReg = (MsrReg >> 8) | 3; - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0x88); - PciData = (UINT32)MsrReg; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - - /* Send all IO (0000-FFFF) to southbridge. */ - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC4); - PciData = 0x0000F000; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); - PciAddress.AddressValue = MAKE_SBDFO(0, 0, 0x18, 1, 0xC0); - PciData = 0x00000003; - LibAmdPciWrite(AccessWidth32, PciAddress, &PciData, &StdHeader); -} diff --git a/src/cpu/amd/pi/00660F01/model_15_init.c b/src/cpu/amd/pi/00660F01/model_15_init.c deleted file mode 100644 index 4bb289622c..0000000000 --- a/src/cpu/amd/pi/00660F01/model_15_init.c +++ /dev/null @@ -1,119 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#include -#include - -void PSPProgBar3Msr(void *Buffer); - -void PSPProgBar3Msr(void *Buffer) -{ - u32 Bar3Addr; - u64 Tmp64; - /* Get Bar3 Addr */ - Bar3Addr = PspLibPciReadPspConfig(0x20); - Tmp64 = Bar3Addr; - printk(BIOS_DEBUG, "Bar3=%llx\n", Tmp64); - LibAmdMsrWrite(0xC00110A2, &Tmp64, NULL); - LibAmdMsrRead(0xC00110A2, &Tmp64, NULL); -} - -static void model_15_init(struct device *dev) -{ - printk(BIOS_DEBUG, "Model 15 Init.\n"); - - u8 i; - msr_t msr; - int num_banks; - int msrno; -#if CONFIG(LOGICAL_CPUS) - u32 siblings; -#endif - - disable_cache(); - /* Enable access to AMD RdDram and WrDram extension bits */ - msr = rdmsr(SYSCFG_MSR); - msr.lo |= SYSCFG_MSR_MtrrFixDramModEn; - msr.lo &= ~SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - // BSP: make a0000-bffff UC, c0000-fffff WB - msr.lo = msr.hi = 0; - wrmsr(MTRR_FIX_16K_A0000, msr); - msr.lo = msr.hi = 0x1e1e1e1e; - wrmsr(MTRR_FIX_64K_00000, msr); - wrmsr(MTRR_FIX_16K_80000, msr); - for (msrno = MTRR_FIX_4K_C0000; msrno <= MTRR_FIX_4K_F8000; msrno++) - wrmsr(msrno, msr); - - msr = rdmsr(SYSCFG_MSR); - msr.lo &= ~SYSCFG_MSR_MtrrFixDramModEn; - msr.lo |= SYSCFG_MSR_MtrrFixDramEn; - wrmsr(SYSCFG_MSR, msr); - - x86_mtrr_check(); - x86_enable_cache(); - - /* zero the machine check error status registers */ - msr = rdmsr(IA32_MCG_CAP); - num_banks = msr.lo & MCA_BANKS_MASK; - msr.lo = 0; - msr.hi = 0; - for (i = 0; i < num_banks; i++) - wrmsr(IA32_MC0_STATUS + (i * 4), msr); - - /* Enable the local CPU APICs */ - setup_lapic(); - -#if CONFIG(LOGICAL_CPUS) - siblings = cpuid_ecx(0x80000008) & 0xff; - - if (siblings > 0) { - msr = rdmsr_amd(CPU_ID_FEATURES_MSR); - msr.lo |= 1 << 28; - wrmsr_amd(CPU_ID_FEATURES_MSR, msr); - - msr = rdmsr_amd(CPU_ID_EXT_FEATURES_MSR); - msr.hi |= 1 << (33 - 32); - wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr); - } - printk(BIOS_DEBUG, "siblings = %02d, ", siblings); -#endif - PSPProgBar3Msr(NULL); - - /* DisableCf8ExtCfg */ - msr = rdmsr(NB_CFG_MSR); - msr.hi &= ~(1 << (46 - 32)); - wrmsr(NB_CFG_MSR, msr); - - /* Write protect SMM space with SMMLOCK. */ - msr = rdmsr(HWCR_MSR); - msr.lo |= (1 << 0); - wrmsr(HWCR_MSR, msr); -} - -static struct device_operations cpu_dev_ops = { - .init = model_15_init, -}; - -static const struct cpu_device_id cpu_table[] = { - { X86_VENDOR_AMD, 0x660f00 }, - { X86_VENDOR_AMD, 0x660f01 }, - { 0, 0 }, -}; - -static const struct cpu_driver model_15 __cpu_driver = { - .ops = &cpu_dev_ops, - .id_table = cpu_table, -}; diff --git a/src/cpu/amd/pi/Kconfig b/src/cpu/amd/pi/Kconfig index e626ef1c74..dff896f016 100644 --- a/src/cpu/amd/pi/Kconfig +++ b/src/cpu/amd/pi/Kconfig @@ -4,7 +4,6 @@ config CPU_AMD_PI bool default y if CPU_AMD_PI_00630F01 default y if CPU_AMD_PI_00730F01 - default y if CPU_AMD_PI_00660F01 default n select ARCH_ALL_STAGES_X86_32 select DRIVERS_AMD_PI @@ -46,4 +45,3 @@ endif # CPU_AMD_PI source "src/cpu/amd/pi/00630F01/Kconfig" source "src/cpu/amd/pi/00730F01/Kconfig" -source "src/cpu/amd/pi/00660F01/Kconfig" diff --git a/src/cpu/amd/pi/Makefile.inc b/src/cpu/amd/pi/Makefile.inc index 969434700e..dc9fd6b2bd 100644 --- a/src/cpu/amd/pi/Makefile.inc +++ b/src/cpu/amd/pi/Makefile.inc @@ -2,4 +2,3 @@ subdirs-$(CONFIG_CPU_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_CPU_AMD_PI_00730F01) += 00730F01 -subdirs-$(CONFIG_CPU_AMD_PI_00660F01) += 00660F01 diff --git a/src/northbridge/amd/agesa/state_machine.h b/src/northbridge/amd/agesa/state_machine.h index 93a70cd53f..a857727a0a 100644 --- a/src/northbridge/amd/agesa/state_machine.h +++ b/src/northbridge/amd/agesa/state_machine.h @@ -83,9 +83,6 @@ void platform_AfterInitResume(struct sysinfo *cb, AMD_RESUME_PARAMS *Resume); void platform_BeforeS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); void platform_AfterS3LateRestore(struct sysinfo *cb, AMD_S3LATE_PARAMS *S3Late); -#if CONFIG(CPU_AMD_PI_00660F01) -typedef void AMD_S3SAVE_PARAMS; -#endif void platform_AfterS3Save(struct sysinfo *cb, AMD_S3SAVE_PARAMS *S3Save); /* FCH callouts, not used with CIMx. */ diff --git a/src/southbridge/amd/pi/hudson/Kconfig b/src/southbridge/amd/pi/hudson/Kconfig index 6a1a9c848b..89dcad6086 100644 --- a/src/southbridge/amd/pi/hudson/Kconfig +++ b/src/southbridge/amd/pi/hudson/Kconfig @@ -60,7 +60,7 @@ config HUDSON_GEC_FWM config HUDSON_PSP bool - default y if CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 + default y if CPU_AMD_PI_00730F01 config AMDFW_CONFIG_FILE string "AMD PSP Firmware config file" @@ -88,7 +88,6 @@ config AMD_PUBKEY_FILE depends on HUDSON_PSP string "AMD public Key" default "3rdparty/blobs/southbridge/amd/avalon/PSP/AmdPubKey.bin" if CPU_AMD_PI_00730F01 - default "3rdparty/blobs/southbridge/amd/kern/PSP/AmdPubKeyCZ.bin" if CPU_AMD_PI_00660F01 config HUDSON_SATA_MODE int "SATA Mode" diff --git a/src/southbridge/amd/pi/hudson/Makefile.inc b/src/southbridge/amd/pi/hudson/Makefile.inc index 94c759ee3e..215a5a12bd 100644 --- a/src/southbridge/amd/pi/hudson/Makefile.inc +++ b/src/southbridge/amd/pi/hudson/Makefile.inc @@ -83,18 +83,6 @@ FIRMWARE_TYPE= endif -ifeq ($(CONFIG_CPU_AMD_PI_00660F01), y) -FIRMWARE_LOCATION=$(dir $(call strip_quotes, $(CONFIG_AMD_PUBKEY_FILE))) -FIRMWARE_TYPE=CZ - -PSPBTLDR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspBootLoader_prod_CZ.sbin -PSPRCVR_FILE=$(top)/$(FIRMWARE_LOCATION)/PspRecoveryBootLoader_prod_CZ.sbin -PSPSECUREOS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureOs_prod_CZ.csbin -PSPTRUSTLETS_FILE=$(top)/$(FIRMWARE_LOCATION)/PspTrustlets_prod_CZ.cbin -TRUSTLETKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/TrustletKey_prod_CZ.sbin -SMUFIRMWARE2_FILE=$(top)/$(FIRMWARE_LOCATION)/SmuFirmware2_prod_CZ.sbin -endif - #PUBSIGNEDKEY_FILE=$(top)/$(FIRMWARE_LOCATION)/RtmPubSigned$(FIRMWARE_TYPE).key #PSPNVRAM_FILE=$(top)/$(FIRMWARE_LOCATION)/PspNvram$(FIRMWARE_TYPE).bin #PSPSECUREDEBUG_FILE=$(top)/$(FIRMWARE_LOCATION)/PspSecureDebug$(FIRMWARE_TYPE).Key diff --git a/src/vendorcode/amd/pi/Kconfig b/src/vendorcode/amd/pi/Kconfig index 15d2ab270d..fb4935bbb0 100644 --- a/src/vendorcode/amd/pi/Kconfig +++ b/src/vendorcode/amd/pi/Kconfig @@ -26,7 +26,7 @@ # SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. # -if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || CPU_AMD_PI_00660F01 || SOC_AMD_STONEYRIDGE +if CPU_AMD_PI_00630F01 || CPU_AMD_PI_00730F01 || SOC_AMD_STONEYRIDGE config AGESA_BINARY_PI_VENDORCODE_PATH string "AGESA PI directory path" @@ -34,7 +34,6 @@ config AGESA_BINARY_PI_VENDORCODE_PATH default "src/vendorcode/amd/pi/00730F01" if CPU_AMD_PI_00730F01 default "src/vendorcode/amd/pi/00670F00" if AMD_APU_MERLINFALCON default "src/vendorcode/amd/pi/00670F00" if AMD_APU_STONEYRIDGE || AMD_APU_PRAIRIEFALCON - default "src/vendorcode/amd/pi/00660F01" if CPU_AMD_PI_00660F01 help Specify where to find the AGESA header files for AMD platform initialization. @@ -46,7 +45,6 @@ config AGESA_BINARY_PI_FILE default "3rdparty/amd_blobs/stoneyridge/pi/CZ/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_MERLINFALCON && USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/pi/ST/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_PRAIRIEFALCON && USE_AMD_BLOBS default "3rdparty/amd_blobs/stoneyridge/pi/ST/\$(CONFIG_AMD_SOC_PACKAGE)/AGESA.bin" if AMD_APU_STONEYRIDGE && USE_AMD_BLOBS - default "3rdparty/blobs/pi/amd/00660F01/FP4/AGESA.bin" if CPU_AMD_PI_00660F01 help Specify the binary file to use for AMD platform initialization. diff --git a/src/vendorcode/amd/pi/Makefile.inc b/src/vendorcode/amd/pi/Makefile.inc index 8f27d64f20..25e3652751 100644 --- a/src/vendorcode/amd/pi/Makefile.inc +++ b/src/vendorcode/amd/pi/Makefile.inc @@ -30,7 +30,7 @@ subdirs-y += 00670F00 -ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01)$(CONFIG_CPU_AMD_PI_00660F01),y) +ifeq ($(CONFIG_CPU_AMD_PI_00630F01)$(CONFIG_CPU_AMD_PI_00730F01),y) # AGESA V5 Files AGESA_ROOT = $(call strip_quotes,$(CONFIG_AGESA_BINARY_PI_VENDORCODE_PATH)) @@ -52,10 +52,6 @@ AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Common -ifeq ($(CONFIG_CPU_AMD_PI_00660F01),y) -AGESA_INC += -I$(AGESA_ROOT)/Proc/Fch/Kern -AGESA_INC += -I$(AGESA_ROOT)/Proc/Psp/PspBaseLib -endif ifeq ($(CONFIG_CPU_AMD_PI_00630F01),y) AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS endif @@ -111,11 +107,6 @@ endef agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/*.[cS]) -ifeq ($(CONFIG_CPU_AMD_PI_00660F01),y) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Kern/KernImc/*.[cS]) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Fch/Common/*.[cS]) -agesa_raw_files += $(wildcard $(AGESA_ROOT)/Proc/Psp/PspBaseLib/*.[cS]) -endif ifeq ($(CONFIG_HUDSON_IMC_FWM),y) agesa_raw_files += $(wildcard $(src)/vendorcode/amd/pi/Lib/imc/*.c) endif From d3a156060937189801ee94e46c131014517d8088 Mon Sep 17 00:00:00 2001 From: David Wu Date: Tue, 17 Nov 2020 17:23:35 +0800 Subject: [PATCH 064/107] mb/google/volteer/var/voema: Update gpio and devicetree settings Based on latest schematic and gpio table of voema, update gpio and devicetree settings for voema Proto. BUG=b:169356808 TEST=FW_NAME=voema emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu Change-Id: I719a9948ed0d60e1de5368e096ff60c2345803b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47667 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks Reviewed-by: Caveh Jalali Reviewed-by: Tim Wawrzynczak --- .../volteer/variants/voema/Makefile.inc | 4 + .../google/volteer/variants/voema/gpio.c | 222 ++++++++++++++++++ .../variants/voema/include/variant/gpio.h | 9 +- .../volteer/variants/voema/overridetree.cb | 159 ++++++++++++- 4 files changed, 387 insertions(+), 7 deletions(-) create mode 100644 src/mainboard/google/volteer/variants/voema/gpio.c diff --git a/src/mainboard/google/volteer/variants/voema/Makefile.inc b/src/mainboard/google/volteer/variants/voema/Makefile.inc index 9064208bff..b0bfc567ff 100644 --- a/src/mainboard/google/volteer/variants/voema/Makefile.inc +++ b/src/mainboard/google/volteer/variants/voema/Makefile.inc @@ -1,3 +1,7 @@ # SPDX-License-Identifier: GPL-2.0-only +bootblock-y += gpio.c + romstage-y += memory.c + +ramstage-y += gpio.c diff --git a/src/mainboard/google/volteer/variants/voema/gpio.c b/src/mainboard/google/volteer/variants/voema/gpio.c new file mode 100644 index 0000000000..267ce1010b --- /dev/null +++ b/src/mainboard/google/volteer/variants/voema/gpio.c @@ -0,0 +1,222 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +/* Pad configuration in ramstage */ +static const struct pad_config override_gpio_table[] = { + /* A7 : I2S2_SCLK ==> I2S1_SPKR_SCLK */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), + /* A8 : I2S2_SFRM ==> I2S1_SPKR_SFRM */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + /* A9 : I2S2_TXD ==> I2S1_PCH_TX_SPKR_RX */ + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + /* A10 : I2S2_RXD ==> I2S1_PCH_RX_SPKR */ + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), + /* A13 : PMC_I2C_SCL ==> BT_DISABLE_L */ + PAD_CFG_GPO(GPP_A13, 1, DEEP), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A16 : USB_OC3# ==> USB_C0_OC_ODL */ + PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1), + /* A18 : DDSP_HPDB ==> HDMI_HPD */ + PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1), + /* A21 : DDPC_CTRCLK ==> EN_FP_PWR */ + PAD_CFG_GPO(GPP_A21, 1, DEEP), + /* A22 : DDPC_CTRLDATA ==> EN_HDMI_PWR */ + PAD_CFG_GPO(GPP_A22, 1, DEEP), + + /* B2 : VRALERT# ==> EN_PP3300_SSD */ + PAD_CFG_GPO(GPP_B2, 1, DEEP), + /* B7 : ISH_12C1_SDA ==> ISH_I2C1_SENSOR_SDA */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), + /* B8 : ISH_I2C1_SCL ==> ISH_I2C1_SENSOR_SCL */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), + /* B9 : I2C5_SDA ==> PCH_I2C5_TRACKPAD_SDA */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + /* B10 : I2C5_SCL ==> PCH_I2C5_TRACKPAD_SCL */ + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + /* B19 : GSPI1_CS0# ==> PCH_GSPI1_FPMCU_CS_L */ + PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1), + /* B20 : GSPI1_CLK ==> PCH_GSPI1_FPMCU_CLK */ + PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1), + /* B21 : GSPI1_MISO ==> PCH_GSPI1_FPMCU_MISO */ + PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1), + /* B23 : SML1ALERT# ==> GPP_B23_STRAP # */ + PAD_NC(GPP_B23, DN_20K), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, DN_20K), + /* C5 : SML0ALERT# ==> USB_SMB_INT_L_BOOT_STRAP0 */ + PAD_NC(GPP_C5, DN_20K), + /* C7 : SML1DATA ==> EN_USI_CHARGE */ + PAD_CFG_GPO(GPP_C7, 1, DEEP), + /* C10 : UART0_RTS# ==> USI_RST_L */ + PAD_CFG_GPO(GPP_C10, 1, DEEP), + /* C13 : UART1_TXD ==> PCH_FPMCU_BOOT1 */ + PAD_CFG_GPO(GPP_C13, 0, DEEP), + /* C16 : I2C0_SDA ==> PCH_I2C0_1V8_AUDIO_SDA */ + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), + /* C17 : I2C0_SCL ==> PCH_I2C0_1V8_AUDIO_SCL */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), + /* C18 : I2C1_SDA ==> PCH_I2C1_TOUCH_USI_SDA */ + PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), + /* C19 : I2C1_SCL ==> PCH_I2C1_TOUCH_USI_SCL */ + PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), + /* C20 : UART2_RXD ==> FPMCU_INT_L */ + PAD_CFG_GPI_INT(GPP_C20, NONE, PLTRST, LEVEL), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + /* C23 : UART2_CTS# ==> FPMCU_RST_ODL */ + PAD_CFG_GPO(GPP_C23, 1, DEEP), + + /* D0 : ISH_GP0 ==> ISH_IMU_INT_L */ + PAD_CFG_GPI(GPP_D0, NONE, DEEP), + /* D1 : ISH_GP1 ==> ISH_ACCEL_INT_L */ + PAD_CFG_GPI(GPP_D1, NONE, DEEP), + /* D2 : ISH_GP2 ==> ISH_LID_OPEN */ + PAD_CFG_GPI(GPP_D2, NONE, DEEP), + /* D3 : ISH_GP3 ==> CAM_DET_L */ + PAD_CFG_GPI(GPP_D3, NONE, DEEP), + /* D4 : IMGCLKOUT0 ==> CAM_RST_L */ + PAD_CFG_GPO(GPP_D4, 0, PLTRST), + /* D10 : ISH_SPI_CLK ==> PCH_GSPI2_CVF_CLK_STRAP */ + PAD_CFG_NF(GPP_D10, DN_20K, DEEP, NF7), + /* D12 : ISH_SPI_MOSI ==> PCH_GSPI2_CVF_MISO_STRAP */ + PAD_CFG_NF(GPP_D12, DN_20K, DEEP, NF7), + /* D13 : ISH_UART0_RXD ==> UART_ISH_RX_DEBUG_TX */ + PAD_CFG_NF(GPP_D13, NONE, DEEP, NF1), + /* D14 : ISH_UART0_TXD ==> UART_ISH_TX_DEBUG_RX */ + PAD_CFG_NF(GPP_D14, NONE, DEEP, NF1), + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + /* D17 : ISH_GP4 ==> CAM_SEN_EN */ + PAD_CFG_GPO(GPP_D17, 0, DEEP), + + /* E0 : SATAXPCIE0 ==> NC */ + PAD_NC(GPP_E0, NONE), + /* E3 : CPU_GP0 ==> USI_REPORT_EN */ + PAD_CFG_GPO(GPP_E3, 1, DEEP), + /* E7 : CPU_GP1 ==> USI_INT */ + PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE), + /* E15 : ISH_GP6 ==> TRACKPAD_INT_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_E15, NONE, DEEP, LEVEL, INVERT), + /* E18 : DDP1_CTRLCLK ==> NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> USB0_C0_LSX_SOC_RX_STRAP */ + PAD_CFG_NF(GPP_E19, DN_20K, DEEP, NF4), + /* E20 : DDP2_CTRLCLK ==> NC */ + PAD_NC(GPP_E20, NONE), + + /* F7 : GPPF7_STRAP */ + PAD_NC(GPP_F7, DN_20K), + /* F11 : THC1_SPI2_CLK ==> NC */ + PAD_NC(GPP_F11, NONE), + /* F12 : GSXDOUT ==> EN_PP3300_TRACKPAD */ + PAD_CFG_GPO(GPP_F12, 1, DEEP), + /* F13 : GSXDOUT ==> WiFi_DISABLE_L */ + PAD_CFG_GPO(GPP_F13, 1, DEEP), + /* F16 : GSXCLK ==> EN_PP3300_TOUCHSCREEN */ + PAD_CFG_GPO(GPP_F16, 1, DEEP), + /* F17 : WWAN_RF_DISABLE_ODL ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F17, NONE, DEEP), + /* F18 : THC1_SPI2_INT# ==> EN_SPKR_PA */ + PAD_CFG_GPO(GPP_F18, 1, DEEP), + + /* H0 : GPPH0_BOOT_STRAP1 */ + PAD_NC(GPP_H0, DN_20K), + /* H1 : GPPH1_BOOT_STRAP2 */ + PAD_NC(GPP_H1, DN_20K), + /* H2 : GPPH2_BOOT_STRAP3 */ + PAD_NC(GPP_H2, DN_20K), + /* H3 : SX_EXIT_HOLDOFF# ==> SD_PERST_L */ + PAD_CFG_GPO(GPP_H3, 1, DEEP), + /* H10 : SRCCLKREQ4# ==> USB_C_MIX_RT_FORCE_PWR */ + PAD_CFG_GPO(GPP_H10, 1, DEEP), + /* H13 : M2_SKT2_CFG1 # ==> SPKR_INT_L */ + PAD_CFG_GPI(GPP_H13, NONE, DEEP), + /* H16 : DDPB_CTRLCLK ==> DDPB_HDMI_CTRLCLK */ + PAD_CFG_NF(GPP_H16, NONE, DEEP, NF1), + /* H17 : DDPB_CTRLDATA ==> DDPB_HDMI_CTRLDATA */ + PAD_CFG_NF(GPP_H17, NONE, DEEP, NF1), + /* H19 : TIME_SYNC0 ==> USER_PRES_FP_ODL_R */ + PAD_CFG_GPI(GPP_H19, NONE, DEEP), + + /* R0 : HDA_BCLK ==> I2S0_HP_SCLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF2), + /* R1 : HDA_SYNC ==> I2S0_HP_SFRM */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF2), + /* R2 : HDA_SDO ==> I2S0_PCH_TX_HP_RX_STRAP */ + PAD_CFG_NF(GPP_R2, DN_20K, DEEP, NF2), + /* R3 : HDA_SDIO ==> I2S0_PCH_RX_HP_TX */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF2), + /* R5 : HDA_SDI1 ==> HP_INT_L */ + PAD_CFG_GPI_INT(GPP_R5, NONE, PLTRST, EDGE_BOTH), + + /* S0 : SNDW0_CLK ==> SNDW0_HP_CLK */ + PAD_CFG_NF(GPP_S0, NONE, DEEP, NF1), + /* S1 : SNDW0_DATA ==> SNDW0_HP_DATA */ + PAD_CFG_NF(GPP_S1, NONE, DEEP, NF1), + /* S2 : SNDW1_CLK ==> SNDW1_SPKR_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF1), + /* S3 : SNDW1_DATA ==> SNDW1_SPKR_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF1), + /* S6 : SNDW3_CLK ==> DMIC_CLK0 */ + PAD_CFG_NF(GPP_S6, NONE, DEEP, NF2), + /* S7 : SNDW3_DATA ==> DMIC_DATA0 */ + PAD_CFG_NF(GPP_S7, NONE, DEEP, NF2), + + /* GPD6: SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD9: SLP_WLAN# ==> SLP_WLAN_L */ + PAD_CFG_NF(GPD9, NONE, DEEP, NF1), +}; + +const struct pad_config *variant_override_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(override_gpio_table); + return override_gpio_table; +} + +/* Early pad configuration in bootblock */ +static const struct pad_config early_gpio_table[] = { + /* A12 : SATAXPCIE1 ==> M2_SSD_PEDET */ + PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), + /* A17 : DDSP_HPDC ==> MEM_CH_SEL */ + PAD_CFG_GPI(GPP_A17, NONE, DEEP), + + /* B11 : PMCALERT# ==> PCH_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_B11, NONE, DEEP), + /* B15 : GSPI0_CS0# ==> PCH_GSPI0_H1_TPM_CS_L */ + PAD_CFG_NF(GPP_B15, NONE, DEEP, NF1), + /* B16 : GSPI0_CLK ==> PCH_GSPI0_H1_TPM_CLK */ + PAD_CFG_NF(GPP_B16, NONE, DEEP, NF1), + /* B17 : GSPI0_MISO ==> PCH_GSPI0_H1_TPM_MISO */ + PAD_CFG_NF(GPP_B17, NONE, DEEP, NF1), + /* B18 : GSPI0_MOSI ==> PCH_GSPI0_H1_TPM_MOSI_STRAP */ + PAD_CFG_NF(GPP_B18, DN_20K, DEEP, NF1), + + /* C0 : SMBCLK ==> EN_PP3300_WLAN */ + PAD_CFG_GPO(GPP_C0, 1, DEEP), + /* C21 : UART2_TXD ==> H1_PCH_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_C21, NONE, PLTRST, LEVEL, INVERT), + /* C22 : UART2_RTS# ==> PCH_FPMCU_BOOT0 */ + PAD_CFG_GPO(GPP_C22, 0, DEEP), + + /* D16 : ISH_UART0_CTS# ==> EN_PP3300_SD */ + PAD_CFG_GPO(GPP_D16, 1, DEEP), + + /* E12 : SPI1_MISO_IO1 ==> PEN_ALERT_ODL */ + PAD_CFG_GPI(GPP_E12, NONE, DEEP), +}; + +const struct pad_config *variant_early_gpio_table(size_t *num) +{ + *num = ARRAY_SIZE(early_gpio_table); + return early_gpio_table; +} diff --git a/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h index b5fa8c5485..166c06ce08 100644 --- a/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h +++ b/src/mainboard/google/volteer/variants/voema/include/variant/gpio.h @@ -5,11 +5,8 @@ #include -/* Memory configuration board straps */ -/* Copied from baseboard and may need to change for the new variant. */ -#define GPIO_MEM_CONFIG_0 GPP_C12 -#define GPIO_MEM_CONFIG_1 GPP_C15 -#define GPIO_MEM_CONFIG_2 GPP_C14 -#define GPIO_MEM_CONFIG_3 GPP_D15 +#undef GPIO_EC_IN_RW +/* EC in RW */ +#define GPIO_EC_IN_RW GPP_F17 #endif diff --git a/src/mainboard/google/volteer/variants/voema/overridetree.cb b/src/mainboard/google/volteer/variants/voema/overridetree.cb index 32204c58e7..9efcdb22f3 100644 --- a/src/mainboard/google/volteer/variants/voema/overridetree.cb +++ b/src/mainboard/google/volteer/variants/voema/overridetree.cb @@ -1,6 +1,163 @@ chip soc/intel/tigerlake + # BitMask where bits [3:0] are Controller 0 Channel [3:0] and + # bits [7:4] are Controller 1 Channel [3:0]. + # Enable Command Mirroring for controller 0 channel 0 and 1, + # and controller 1 channel 0 and 1. + register "CmdMirror" = "0x00000033" + + # Disable SRCCLKREQ1# and SRCCLKREQ3# + register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED" + register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED" device domain 0 on + device ref i2c0 on + chip drivers/i2c/generic + register "hid" = ""10EC5682"" + register "name" = ""RT58"" + register "desc" = ""Headset Codec"" + register "irq_gpio" = "ACPI_GPIO_IRQ_EDGE_BOTH(GPP_R5)" + # Set the jd_src to RT5668_JD1 for jack detection + register "property_count" = "1" + register "property_list[0].type" = "ACPI_DP_TYPE_INTEGER" + register "property_list[0].name" = ""realtek,jd-src"" + register "property_list[0].integer" = "1" + device i2c 1a on + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "0" + register "imon_slot_no" = "1" + register "uid" = "0" + register "desc" = ""Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 31 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + chip drivers/i2c/max98373 + register "vmon_slot_no" = "2" + register "imon_slot_no" = "3" + register "uid" = "1" + register "desc" = ""Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 32 on + probe AUDIO MAX98373_ALC5682I_I2S_UP4 + end + end + end + device ref i2c1 on + chip drivers/i2c/hid + register "generic.hid" = ""ELAN9004"" + register "generic.desc" = ""ELAN Touchscreen"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" + register "generic.probed" = "1" + register "generic.reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" + register "generic.reset_delay_ms" = "20" + register "generic.reset_off_delay_ms" = "2" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_F16)" + register "generic.enable_delay_ms" = "10" + register "generic.stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E3)" + register "generic.stop_delay_ms" = "300" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "hid_desc_reg_offset" = "0x01" + device i2c 10 on end + end + end + device ref i2c5 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E15_IRQ)" + register "wake" = "GPE0_DW2_15" + register "probed" = "1" + device i2c 15 on end + end + end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end + device ref pmc hidden + # The pmc_mux chip driver is a placeholder for the + # PMC.MUX device in the ACPI hierarchy. + chip drivers/intel/pmc_mux + device generic 0 on + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "5" + register "usb3_port_number" = "1" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 0 alias conn0 on end + end + chip drivers/intel/pmc_mux/conn + register "usb2_port_number" = "3" + register "usb3_port_number" = "2" + # SBU is fixed, HSL follows CC + register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" + device generic 1 alias conn1 on end + end + end + end + end + device ref north_xhci on + chip drivers/usb/acpi + device ref tcss_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 2)" + device ref tcss_usb3_port1 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 2)" + device ref tcss_usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end + device ref south_xhci on + chip drivers/usb/acpi + device ref xhci_root_hub on + chip drivers/usb/acpi + register "desc" = ""USB2 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_A" + register "group" = "ACPI_PLD_GROUP(1, 1)" + device ref usb2_port2 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(2, 1)" + device ref usb2_port3 on + probe DB_USB USB3_ACTIVE + end + end + chip drivers/usb/acpi + register "desc" = ""USB2 Type-C Port C0 (MLB)"" + register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" + register "group" = "ACPI_PLD_GROUP(3, 1)" + device ref usb2_port5 on end + end + chip drivers/usb/acpi + register "desc" = ""USB3 Type-A Port A1 (DB)"" + register "type" = "UPC_TYPE_USB3_A" + register "group" = "ACPI_PLD_GROUP(1, 2)" + device ref usb3_port2 on + probe DB_USB USB3_ACTIVE + end + end + end + end + end end - end From e49856dfa8e1dc1ee6c0b9eb9257ed4d8d95c7af Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 9 Oct 2020 15:04:49 +0200 Subject: [PATCH 065/107] soc/intel/denverton_ns: Convert to ASL 2.0 syntax MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I261add8142c3192ab944845e8e1a362a3aca00c8 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/46240 Tested-by: build bot (Jenkins) Reviewed-by: Mariusz Szafrański --- src/soc/intel/denverton_ns/acpi/globalnvs.asl | 16 ++-- src/soc/intel/denverton_ns/acpi/irqlinks.asl | 96 +++++++++---------- .../intel/denverton_ns/acpi/northcluster.asl | 16 ++-- .../intel/denverton_ns/acpi/southcluster.asl | 4 +- 4 files changed, 66 insertions(+), 66 deletions(-) diff --git a/src/soc/intel/denverton_ns/acpi/globalnvs.asl b/src/soc/intel/denverton_ns/acpi/globalnvs.asl index f858cdf0d5..7ce6c7a913 100644 --- a/src/soc/intel/denverton_ns/acpi/globalnvs.asl +++ b/src/soc/intel/denverton_ns/acpi/globalnvs.asl @@ -62,27 +62,27 @@ Field (GNVS, ByteAcc, NoLock, Preserve) /* Set flag to enable USB charging in S3 */ Method (S3UE) { - Store (One, \S3U0) - Store (One, \S3U1) + \S3U0 = 1 + \S3U1 = 1 } /* Set flag to disable USB charging in S3 */ Method (S3UD) { - Store (Zero, \S3U0) - Store (Zero, \S3U1) + \S3U0 = 0 + \S3U1 = 0 } /* Set flag to enable USB charging in S5 */ Method (S5UE) { - Store (One, \S5U0) - Store (One, \S5U1) + \S5U0 = 1 + \S5U1 = 1 } /* Set flag to disable USB charging in S5 */ Method (S5UD) { - Store (Zero, \S5U0) - Store (Zero, \S5U1) + \S5U0 = 0 + \S5U1 = 0 } diff --git a/src/soc/intel/denverton_ns/acpi/irqlinks.asl b/src/soc/intel/denverton_ns/acpi/irqlinks.asl index e62d84dd36..ef076bc54b 100644 --- a/src/soc/intel/denverton_ns/acpi/irqlinks.asl +++ b/src/soc/intel/denverton_ns/acpi/irqlinks.asl @@ -8,7 +8,7 @@ Device (LNKA) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTA) + PRTA = 0x80 } // Possible Resource Settings for this Link @@ -28,10 +28,10 @@ Device (LNKA) CreateWordField(RTLA, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTA - ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + IRQ0 = 1 << (PRTA & 0x0f) Return (RTLA) } @@ -44,14 +44,14 @@ Device (LNKA) // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTA) + Local0-- + PRTA = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTA, 0x80)) { + If (PRTA & 0x80) { Return (0x9) } Else { Return (0xb) @@ -67,7 +67,7 @@ Device (LNKB) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTB) + PRTB = 0x80 } // Possible Resource Settings for this Link @@ -87,10 +87,10 @@ Device (LNKB) CreateWordField(RTLB, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTB - ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + IRQ0 = 1 << (PRTB & 0x0f) Return (RTLB) } @@ -103,14 +103,14 @@ Device (LNKB) // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTB) + Local0-- + PRTB = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTB, 0x80)) { + If (PRTB & 0x80) { Return (0x9) } Else { Return (0xb) @@ -126,7 +126,7 @@ Device (LNKC) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTC) + PRTC = 0x80 } // Possible Resource Settings for this Link @@ -146,10 +146,10 @@ Device (LNKC) CreateWordField(RTLC, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTC - ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + IRQ0 = 1 << (PRTC & 0x0f) Return (RTLC) } @@ -162,14 +162,14 @@ Device (LNKC) // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTC) + Local0-- + PRTC = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTC, 0x80)) { + If (PRTC & 0x80) { Return (0x9) } Else { Return (0xb) @@ -185,7 +185,7 @@ Device (LNKD) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTD) + PRTD = 0x80 } // Possible Resource Settings for this Link @@ -205,10 +205,10 @@ Device (LNKD) CreateWordField(RTLD, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTD - ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + IRQ0 = 1 << (PRTD & 0x0f) Return (RTLD) } @@ -221,14 +221,14 @@ Device (LNKD) // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTD) + Local0-- + PRTD = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTD, 0x80)) { + If (PRTD & 0x80) { Return (0x9) } Else { Return (0xb) @@ -244,7 +244,7 @@ Device (LNKE) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTE) + PRTE = 0x80 } // Possible Resource Settings for this Link @@ -264,10 +264,10 @@ Device (LNKE) CreateWordField(RTLE, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTE - ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + IRQ0 = 1 << (PRTE & 0x0f) Return (RTLE) } @@ -280,14 +280,14 @@ Device (LNKE) // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTE) + Local0-- + PRTE = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTE, 0x80)) { + If (PRTE & 0x80) { Return (0x9) } Else { Return (0xb) @@ -303,7 +303,7 @@ Device (LNKF) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTF) + PRTF = 0x80 } // Possible Resource Settings for this Link @@ -323,10 +323,10 @@ Device (LNKF) CreateWordField(RTLF, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTF - ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + IRQ0 = 1 << (PRTF & 0x0f) Return (RTLF) } @@ -339,14 +339,14 @@ Device (LNKF) // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTF) + Local0-- + PRTF = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTF, 0x80)) { + If (PRTF & 0x80) { Return (0x9) } Else { Return (0xb) @@ -362,7 +362,7 @@ Device (LNKG) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTG) + PRTG = 0x80 } // Possible Resource Settings for this Link @@ -382,10 +382,10 @@ Device (LNKG) CreateWordField(RTLG, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTG - ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + IRQ0 = 1 << (PRTG & 0x0f) Return (RTLG) } @@ -398,14 +398,14 @@ Device (LNKG) // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTG) + Local0-- + PRTG = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTG, 0x80)) { + If (PRTG & 0x80) { Return (0x9) } Else { Return (0xb) @@ -421,7 +421,7 @@ Device (LNKH) // Disable method Method (_DIS, 0, Serialized) { - Store (0x80, PRTH) + PRTH = 0x80 } // Possible Resource Settings for this Link @@ -441,10 +441,10 @@ Device (LNKH) CreateWordField(RTLH, 1, IRQ0) // Clear the WordField - Store (Zero, IRQ0) + IRQ0 = 0 // Set the bit from PRTH - ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + IRQ0 = 1 << (PRTH & 0x0f) Return (RTLH) } @@ -457,14 +457,14 @@ Device (LNKH) // Which bit is set? FindSetRightBit(IRQ0, Local0) - Decrement(Local0) - Store(Local0, PRTH) + Local0-- + PRTH = Local0 } // Status Method (_STA, 0, Serialized) { - If(And(PRTH, 0x80)) { + If (PRTH & 0x80) { Return (0x9) } Else { Return (0xb) diff --git a/src/soc/intel/denverton_ns/acpi/northcluster.asl b/src/soc/intel/denverton_ns/acpi/northcluster.asl index e1d1e40bc4..40d745ef62 100644 --- a/src/soc/intel/denverton_ns/acpi/northcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/northcluster.asl @@ -97,9 +97,9 @@ Method (_CRS, 0, Serialized) CreateDwordField(MCRS, ^PM01._LEN, PLEN) // MMIO Low is saved in NVS - Store (\MMOB, PMIN) - Store (\MMOL, PMAX) - Add (Subtract (PMAX, PMIN), 1, PLEN) + PMIN = \MMOB + PMAX = \MMOL + PLEN = PMAX - PMIN + 1 // Find PCI resource area in MCRS CreateQWordField(MCRS, ^PM02._MIN, P2MN) @@ -107,9 +107,9 @@ Method (_CRS, 0, Serialized) CreateQWordField(MCRS, ^PM02._LEN, P2LN) // MMIO High is saved in NVS - Store(\MMHB, P2MN) - Store(\MMHL, P2MX) - Add(Subtract(P2MX,P2MN),1,P2LN) + P2MN = \MMHB + P2MX = \MMHL + P2LN = P2MX - P2MN +1 Return (MCRS) } // End _CRS @@ -132,9 +132,9 @@ Device (PDRC) { // Fix up 32-bit TSEG CreateDWordField(PDRS, ^TSMB._BAS, TSMN) - Store(\TSGB, TSMN) + TSMN = \TSGB CreateDWordField(PDRS, ^TSMB._LEN, TSLN) - Store(\TSSZ, TSLN) + TSLN = \TSSZ Return(PDRS) } } diff --git a/src/soc/intel/denverton_ns/acpi/southcluster.asl b/src/soc/intel/denverton_ns/acpi/southcluster.asl index 68f55f295b..72e12bd299 100644 --- a/src/soc/intel/denverton_ns/acpi/southcluster.asl +++ b/src/soc/intel/denverton_ns/acpi/southcluster.asl @@ -128,7 +128,7 @@ Device (P2SB) Method (_OSC, 4) { /* Check for proper GUID */ - If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) + If (Arg0 == ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")) { /* Let OS control everything */ Return (Arg3) @@ -137,7 +137,7 @@ Method (_OSC, 4) { /* Unrecognized UUID */ CreateDWordField (Arg3, 0, CDW1) - Or (CDW1, 4, CDW1) + CDW1 |= 4 Return (Arg3) } } From 778c4f8c96110d2d00ff1396faba2650b64da507 Mon Sep 17 00:00:00 2001 From: Mariusz Szafranski Date: Thu, 19 Nov 2020 13:05:32 +0100 Subject: [PATCH 066/107] MAINTAINERS: update maintainers of Intel Denverton-NS SoC Change-Id: Ifdb24f9566b53af6c23b4cd4adba0c1876e4fc9d Signed-off-by: Mariusz Szafranski Reviewed-on: https://review.coreboot.org/c/coreboot/+/47753 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: David Guckian Reviewed-by: Christian Walter Reviewed-by: Paul Menzel --- MAINTAINERS | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index 6a1f500de7..1972c885b4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -506,9 +506,11 @@ F: src/drivers/intel/ F: src/include/cpu/intel/ INTEL FSP DENVERTON-NS SOC & HARCUVAR CRB +M: Suresh Bellampalli M: Vanessa Eusebio -M: David Guckian -S: Odd Fixes +M: Michal Motyl +M: Mariusz Szafranski +S: Maintained F: src/mainboard/intel/harcuvar/ F: src/soc/intel/denverton_ns/ From 08c646c06011303dea0aeb2f96e13fe05928dd8b Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 19 Nov 2020 13:56:41 +0100 Subject: [PATCH 067/107] soc/intel/block/pmc: Move pmc_set_acpi_mode() to pmc_lib.c pmc.c mostly contains a PCI driver, while this function just calls into SMM. Change-Id: I9a93a5079b526da5d0f95f773f2860e43b327edf Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47755 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/common/block/include/intelblocks/pmc.h | 3 --- src/soc/intel/common/block/include/intelblocks/pmclib.h | 3 +++ src/soc/intel/common/block/pmc/pmc.c | 8 -------- src/soc/intel/common/block/pmc/pmclib.c | 8 ++++++++ 4 files changed, 11 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/common/block/include/intelblocks/pmc.h b/src/soc/intel/common/block/include/intelblocks/pmc.h index 329bbe9bd7..f62ec2fe24 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmc.h +++ b/src/soc/intel/common/block/include/intelblocks/pmc.h @@ -48,7 +48,4 @@ void pmc_soc_init(struct device *dev); */ int pmc_soc_get_resources(struct pmc_resource_config *cfg); -/* API to set ACPI mode */ -void pmc_set_acpi_mode(void); - #endif /* SOC_INTEL_COMMON_BLOCK_PMC_H */ diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index 2acc275b2f..ecc8166fb8 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -232,4 +232,7 @@ uint8_t get_pm_pwr_cyc_dur(uint8_t slp_s4_min_assert, uint8_t slp_s3_min_assert, /* Disabling ACPI PM timer to ensure switches off TCO and necessary of XTAL OSC shutdown */ void pmc_disable_acpi_timer(void); +/* API to set ACPI mode */ +void pmc_set_acpi_mode(void); + #endif /* SOC_INTEL_COMMON_BLOCK_PMCLIB_H */ diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index 5bfad71909..d153bc7188 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include @@ -90,13 +89,6 @@ static void pch_pmc_read_resources(struct device *dev) pch_pmc_add_io_resources(dev, config); } -void pmc_set_acpi_mode(void) -{ - if (!acpi_is_wakeup_s3()) { - apm_control(APM_CNT_ACPI_DISABLE); - } -} - static struct device_operations device_ops = { .read_resources = pch_pmc_read_resources, .set_resources = pci_dev_set_resources, diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index a5dff2d75b..02ca6de496 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -709,3 +710,10 @@ void pmc_disable_acpi_timer(void) setbits8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, ACPI_TIM_DIS); } #endif /* PMC_LOW_POWER_MODE_PROGRAM */ + +void pmc_set_acpi_mode(void) +{ + if (!acpi_is_wakeup_s3()) { + apm_control(APM_CNT_ACPI_DISABLE); + } +} From 1ae8cd1064ce8bf4892bd486a1ba60c6a3a8d4af Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 19 Nov 2020 13:59:53 +0100 Subject: [PATCH 068/107] soc/intel/block/pmc: Only include the PCI driver when it is not hidden On more recent Intel platforms FSP-S hides the PMC PCI device and the driver is broken for those devices so don't include it at all. Change-Id: I784be250698ec1c1e9b3b766cf1bcca55730c021 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47756 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/common/block/pmc/Kconfig | 6 ++++++ src/soc/intel/common/block/pmc/Makefile.inc | 2 +- src/soc/intel/skylake/Kconfig | 1 + 4 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index 3917feaf79..4f762a9cd0 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -78,6 +78,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_PCR select SOC_INTEL_COMMON_BLOCK_P2SB select SOC_INTEL_COMMON_BLOCK_PMC + select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SRAM select SOC_INTEL_COMMON_BLOCK_RTC select SOC_INTEL_COMMON_BLOCK_SA diff --git a/src/soc/intel/common/block/pmc/Kconfig b/src/soc/intel/common/block/pmc/Kconfig index b420865c92..8cd26350b7 100644 --- a/src/soc/intel/common/block/pmc/Kconfig +++ b/src/soc/intel/common/block/pmc/Kconfig @@ -13,6 +13,12 @@ if SOC_INTEL_COMMON_BLOCK_PMC config POWER_STATE_DEFAULT_ON_AFTER_FAILURE default y +config SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE + bool + help + Select this on platforms where the PMC device is discoverable + when scanning busses. + endif # SOC_INTEL_COMMON_BLOCK_PMC config PMC_INVALID_READ_AFTER_WRITE diff --git a/src/soc/intel/common/block/pmc/Makefile.inc b/src/soc/intel/common/block/pmc/Makefile.inc index 49a0902847..de69b63b4e 100644 --- a/src/soc/intel/common/block/pmc/Makefile.inc +++ b/src/soc/intel/common/block/pmc/Makefile.inc @@ -1,7 +1,7 @@ ifeq ($(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC),y) bootblock-y += pmclib.c romstage-y += pmclib.c -ramstage-y += pmc.c +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE) += pmc.c ramstage-y += pmclib.c pmc_ipc.c smm-y += pmclib.c verstage-y += pmclib.c diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index ce46d06b03..ed81e2470b 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -55,6 +55,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL select SOC_INTEL_COMMON_BLOCK_GSPI select SOC_INTEL_COMMON_BLOCK_HDA + select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE select SOC_INTEL_COMMON_BLOCK_SA select SOC_INTEL_COMMON_BLOCK_SCS select SOC_INTEL_COMMON_BLOCK_SGX From f2baae3735b86ff14a13728a845bd484aa4caf70 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 19 Nov 2020 13:09:56 +0100 Subject: [PATCH 069/107] soc/intel/common/pmc.c Don't implement a weak function that dies Buildtime failures are better than runtime failures. Change-Id: I5fe4c86a13dbabb839977010f129419e337e8281 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47752 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/common/block/pmc/pmc.c | 16 ---------------- 1 file changed, 16 deletions(-) diff --git a/src/soc/intel/common/block/pmc/pmc.c b/src/soc/intel/common/block/pmc/pmc.c index d153bc7188..fe4dca6fa4 100644 --- a/src/soc/intel/common/block/pmc/pmc.c +++ b/src/soc/intel/common/block/pmc/pmc.c @@ -8,22 +8,6 @@ #include #include -/* SoC overrides */ - -/* Fill up PMC resource structure inside SoC directory */ -__weak int pmc_soc_get_resources( - struct pmc_resource_config *cfg) -{ - /* no-op */ - return -1; -} - -/* SoC override PMC initialization */ -__weak void pmc_soc_init(struct device *dev) -{ - /* no-op */ -} - static void pch_pmc_add_new_resource(struct device *dev, uint8_t offset, uintptr_t base, size_t size, unsigned long flags) From 8461cec76c7323103cb1f61bae077d9a2b1d252e Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Thu, 19 Nov 2020 14:22:24 +0100 Subject: [PATCH 070/107] soc/intel/block/pmclib.c: Properly guard apm_control() This function is only properly implemented with SMM support. Change-Id: I9e0fc7433a9226825f5ae4903c0ff2e0162d86ac Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47757 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/common/block/pmc/pmclib.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index 02ca6de496..09af749073 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -713,7 +713,7 @@ void pmc_disable_acpi_timer(void) void pmc_set_acpi_mode(void) { - if (!acpi_is_wakeup_s3()) { + if (!CONFIG(NO_SMM) && !acpi_is_wakeup_s3()) { apm_control(APM_CNT_ACPI_DISABLE); } } From b54212109e71e649cd8c494926d705d1c1657a06 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 18 Nov 2020 16:36:07 +0100 Subject: [PATCH 071/107] cpu/amd/microcode: Remove dead Makefile Change-Id: If9d1e28ac50b8ca227b2c09dbbfdd3c9b60aca6a Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47718 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/cpu/amd/microcode/Makefile.inc | 2 -- 1 file changed, 2 deletions(-) delete mode 100644 src/cpu/amd/microcode/Makefile.inc diff --git a/src/cpu/amd/microcode/Makefile.inc b/src/cpu/amd/microcode/Makefile.inc deleted file mode 100644 index f409d1f158..0000000000 --- a/src/cpu/amd/microcode/Makefile.inc +++ /dev/null @@ -1,2 +0,0 @@ -ramstage-y += microcode.c -romstage-y += microcode.c From 832dd4388a8f8a56acd70da5c1cdfa97deb3bf5d Mon Sep 17 00:00:00 2001 From: Sheng-Liang Pan Date: Wed, 18 Nov 2020 18:52:57 +0800 Subject: [PATCH 072/107] mb/google/octopus: fix droid lte sku load specific wifi sar value This CL add droid lte sku 37 38 39 40 to load wifi_sar-droid.hex. BUG=none BRANCH=octopus TEST=emerge-octopus coreboot Signed-off-by: Pan Sheng-Liang Change-Id: I55dda85b8f3e664d97834b712a2c6a48d1434010 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47697 Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/octopus/variants/bobba/variant.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/src/mainboard/google/octopus/variants/bobba/variant.c b/src/mainboard/google/octopus/variants/bobba/variant.c index 96806a0b24..2d09270148 100644 --- a/src/mainboard/google/octopus/variants/bobba/variant.c +++ b/src/mainboard/google/octopus/variants/bobba/variant.c @@ -21,8 +21,7 @@ const char *get_wifi_sar_cbfs_filename(void) const char *filename = NULL; uint32_t sku_id = google_chromeec_get_board_sku(); - if (sku_id == 33 || sku_id == 34 || sku_id == 35 || sku_id == 36 || sku_id == 41 || - sku_id == 42 || sku_id == 43 || sku_id == 44) + if (sku_id >= 33 && sku_id <= 44) filename = "wifi_sar-droid.hex"; return filename; From 02dec12629824174e788658f40b79bdd5337ffa7 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 18 Nov 2020 12:27:28 +0100 Subject: [PATCH 073/107] soc/intel/xeon_sp: Work around FSP-T not respecting its own API The CPX FSP-T does not respect the FSP2.x spec and uses registers where coreboot has its initial timestamp stored. If the initial timestamp is later than some other timestamps this messes up the timestamps 'cbmem -t' reports as it thinks they are a result from a timestamp overflow (reporting that it took 100k years to boot). TEST: The ocp/deltalake boots within the span of a lifetime. Change-Id: I4ba15decec22cd473e63149ec399d82c5e3fd214 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/47738 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/bootblock.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 5adda44d93..baf5ab5ad9 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -33,11 +33,20 @@ const FSPT_UPD temp_ram_init_params = { .UpdTerminator = 0x55AA, }; +static uint64_t assembly_timestamp; +static uint64_t bootblock_timestamp; + asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { + /* + * FSP-T does not respect its own API and trashes registers + * coreboot uses to store its initial timestamp. + */ + assembly_timestamp = base_timestamp; + bootblock_timestamp = timestamp_get(); fast_spi_cache_bios_region(); - bootblock_main_with_basetime(base_timestamp); + bootblock_main_with_basetime(MIN(assembly_timestamp, bootblock_timestamp)); } void bootblock_soc_early_init(void) @@ -55,6 +64,10 @@ void bootblock_soc_init(void) { if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + + if (assembly_timestamp > bootblock_timestamp) + printk(BIOS_WARNING, "Invalid initial timestamp detected\n"); + if (CONFIG(FSP_CAR)) report_fspt_output(); bootblock_pch_init(); From ac7f461d8d592cc3cbad0be491f15fe4238e1348 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 8 Oct 2020 15:36:08 +0200 Subject: [PATCH 074/107] mb/facebook/fbg1701/Kconfig: Add dependency VENDORCODE_ELTAN items are only used when USE_VENDORCODE_ELTAN is enabled. Add dependency of USE_VENDORCODE_ELTAN. Change-Id: Ibcc40014930c90e29904661f5ffa41bc688d368b Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/46218 Tested-by: build bot (Jenkins) Reviewed-by: Wim Vervoorn Reviewed-by: Angel Pons Reviewed-by: Arthur Heymans --- src/mainboard/facebook/fbg1701/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/facebook/fbg1701/Kconfig b/src/mainboard/facebook/fbg1701/Kconfig index 411033754a..eda65ee1fc 100644 --- a/src/mainboard/facebook/fbg1701/Kconfig +++ b/src/mainboard/facebook/fbg1701/Kconfig @@ -77,6 +77,7 @@ config FSP_LOC default 0xfff9c000 config VENDORCODE_ELTAN_OEM_MANIFEST_LOC + depends on USE_VENDORCODE_ELTAN hex default 0xFFFE9000 @@ -97,14 +98,17 @@ config C_ENV_BOOTBLOCK_SIZE default 0x4000 config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST + depends on USE_VENDORCODE_ELTAN bool default y config VENDORCODE_ELTAN_VBOOT_MANIFEST + depends on USE_VENDORCODE_ELTAN string default "mainboard/facebook/fbg1701/manifest.h" config VENDORCODE_ELTAN_VBOOT_KEY_LOCATION + depends on USE_VENDORCODE_ELTAN hex default 0xFFFF9C00 From d8d8be1a6a008d061727ddd07bd39bd435c4aaf0 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Mon, 21 Sep 2020 09:48:53 +0200 Subject: [PATCH 075/107] drivers/tpm: Move PPI stub As preparation to a full PPI implementation move the acpi code out of the pc80/tpm/tis driver into the generic tpm driver folder. This doesn't change any functionality. Change-Id: I7818d0344d4a08926195bd4804565502717c48fa Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/45567 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/drivers/pc80/tpm/tis.c | 126 ++------------------------------- src/drivers/tpm/Makefile.inc | 2 + src/drivers/tpm/ppi_stub.c | 133 +++++++++++++++++++++++++++++++++++ src/drivers/tpm/tpm_ppi.h | 58 +++++++++++++++ 4 files changed, 198 insertions(+), 121 deletions(-) create mode 100644 src/drivers/tpm/ppi_stub.c create mode 100644 src/drivers/tpm/tpm_ppi.h diff --git a/src/drivers/pc80/tpm/tis.c b/src/drivers/pc80/tpm/tis.c index 27d238ce75..48e529ad9f 100644 --- a/src/drivers/pc80/tpm/tis.c +++ b/src/drivers/pc80/tpm/tis.c @@ -21,13 +21,11 @@ #include #include #include +#include #include "chip.h" #define PREFIX "lpc_tpm: " -/* TCG Physical Presence Interface */ -#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653" -/* TCG Memory Clear Interface */ -#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" + /* coreboot wrapper for TPM driver (start) */ #define TPM_DEBUG(fmt, args...) \ if (CONFIG(DEBUG_TPM)) { \ @@ -777,104 +775,9 @@ static void lpc_tpm_set_resources(struct device *dev) } #if CONFIG(HAVE_ACPI_TABLES) - -static void tpm_ppi_func0_cb(void *arg) -{ - /* Functions 1-8. */ - u8 buf[] = {0xff, 0x01}; - acpigen_write_return_byte_buffer(buf, 2); -} - -static void tpm_ppi_func1_cb(void *arg) -{ - if (CONFIG(TPM2)) - /* Interface version: 2.0 */ - acpigen_write_return_string("2.0"); - else - /* Interface version: 1.2 */ - acpigen_write_return_string("1.2"); -} - -static void tpm_ppi_func2_cb(void *arg) -{ - /* Submit operations: drop on the floor and return success. */ - acpigen_write_return_byte(0); -} - -static void tpm_ppi_func3_cb(void *arg) -{ - /* Pending operation: none. */ - acpigen_emit_byte(RETURN_OP); - acpigen_write_package(2); - acpigen_write_byte(0); - acpigen_write_byte(0); - acpigen_pop_len(); -} -static void tpm_ppi_func4_cb(void *arg) -{ - /* Pre-OS transition method: reboot. */ - acpigen_write_return_byte(2); -} -static void tpm_ppi_func5_cb(void *arg) -{ - /* Operation response: no operation executed. */ - acpigen_emit_byte(RETURN_OP); - acpigen_write_package(3); - acpigen_write_byte(0); - acpigen_write_byte(0); - acpigen_write_byte(0); - acpigen_pop_len(); -} -static void tpm_ppi_func6_cb(void *arg) -{ - /* - * Set preferred user language: deprecated and must return 3 aka - * "not implemented". - */ - acpigen_write_return_byte(3); -} -static void tpm_ppi_func7_cb(void *arg) -{ - /* Submit operations: deny. */ - acpigen_write_return_byte(3); -} -static void tpm_ppi_func8_cb(void *arg) -{ - /* All actions are forbidden. */ - acpigen_write_return_byte(1); -} -static void (*tpm_ppi_callbacks[])(void *) = { - tpm_ppi_func0_cb, - tpm_ppi_func1_cb, - tpm_ppi_func2_cb, - tpm_ppi_func3_cb, - tpm_ppi_func4_cb, - tpm_ppi_func5_cb, - tpm_ppi_func6_cb, - tpm_ppi_func7_cb, - tpm_ppi_func8_cb, -}; - -static void tpm_mci_func0_cb(void *arg) -{ - /* Function 1. */ - acpigen_write_return_singleton_buffer(0x3); -} -static void tpm_mci_func1_cb(void *arg) -{ - /* Just return success. */ - acpigen_write_return_byte(0); -} - -static void (*tpm_mci_callbacks[])(void *) = { - tpm_mci_func0_cb, - tpm_mci_func1_cb, -}; - static void lpc_tpm_fill_ssdt(const struct device *dev) { const char *path = acpi_device_path(dev->bus->dev); - u32 arg; if (!path) { path = "\\_SB_.PCI0.LPCB"; @@ -938,31 +841,12 @@ static void lpc_tpm_fill_ssdt(const struct device *dev) acpi_device_write_interrupt(&tpm_irq); } + acpigen_write_resourcetemplate_footer(); - if (!CONFIG(CHROMEOS)) { - /* - * _DSM method - */ - struct dsm_uuid ids[] = { - /* Physical presence interface. - * This is used to submit commands like "Clear TPM" to - * be run at next reboot provided that user confirms - * them. Spec allows user to cancel all commands and/or - * configure BIOS to reject commands. So we pretend that - * user did just this: cancelled everything. If user - * really wants to clear TPM the only option now is to - * do it manually in payload. - */ - DSM_UUID(TPM_PPI_UUID, &tpm_ppi_callbacks[0], - ARRAY_SIZE(tpm_ppi_callbacks), (void *) &arg), - /* Memory clearing on boot: just a dummy. */ - DSM_UUID(TPM_MCI_UUID, &tpm_mci_callbacks[0], - ARRAY_SIZE(tpm_mci_callbacks), (void *) &arg), - }; + if (!CONFIG(CHROMEOS)) + tpm_ppi_acpi_fill_ssdt(dev); - acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); - } acpigen_pop_len(); /* Device */ acpigen_pop_len(); /* Scope */ diff --git a/src/drivers/tpm/Makefile.inc b/src/drivers/tpm/Makefile.inc index 4e80600ddf..5fc4632912 100644 --- a/src/drivers/tpm/Makefile.inc +++ b/src/drivers/tpm/Makefile.inc @@ -1 +1,3 @@ ramstage-$(CONFIG_TPM_INIT) += tpm.c + +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += ppi_stub.c diff --git a/src/drivers/tpm/ppi_stub.c b/src/drivers/tpm/ppi_stub.c new file mode 100644 index 0000000000..11bd07e10a --- /dev/null +++ b/src/drivers/tpm/ppi_stub.c @@ -0,0 +1,133 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include + +#include "tpm_ppi.h" + +static void tpm_ppi_func0_cb(void *arg) +{ + /* Functions 1-8. */ + u8 buf[] = {0xff, 0x01}; + acpigen_write_return_byte_buffer(buf, sizeof(buf)); +} + +static void tpm_ppi_func1_cb(void *arg) +{ + if (CONFIG(TPM2)) + /* Interface version: 2.0 */ + acpigen_write_return_string("2.0"); + else + /* Interface version: 1.2 */ + acpigen_write_return_string("1.2"); +} + +static void tpm_ppi_func2_cb(void *arg) +{ + /* Submit operations: drop on the floor and return success. */ + acpigen_write_return_byte(PPI2_RET_SUCCESS); +} + +static void tpm_ppi_func3_cb(void *arg) +{ + /* Pending operation: none. */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(2); + acpigen_write_byte(0); + acpigen_write_byte(0); + acpigen_pop_len(); +} + +static void tpm_ppi_func4_cb(void *arg) +{ + /* Pre-OS transition method: reboot. */ + acpigen_write_return_byte(2); +} + +static void tpm_ppi_func5_cb(void *arg) +{ + /* Operation response: no operation executed. */ + acpigen_emit_byte(RETURN_OP); + acpigen_write_package(3); + acpigen_write_byte(0); + acpigen_write_byte(0); + acpigen_write_byte(0); + acpigen_pop_len(); +} + +static void tpm_ppi_func6_cb(void *arg) +{ + /* + * Set preferred user language: deprecated and must return 3 AKA + * "not implemented". + */ + acpigen_write_return_byte(PPI6_RET_NOT_IMPLEMENTED); +} + +static void tpm_ppi_func7_cb(void *arg) +{ + /* Submit operations: deny. */ + acpigen_write_return_byte(PPI7_RET_BLOCKED_BY_FIRMWARE); +} + +static void tpm_ppi_func8_cb(void *arg) +{ + /* All actions are forbidden. */ + acpigen_write_return_byte(PPI8_RET_FIRMWARE_ONLY); +} + +static void (*tpm_ppi_callbacks[])(void *) = { + tpm_ppi_func0_cb, + tpm_ppi_func1_cb, + tpm_ppi_func2_cb, + tpm_ppi_func3_cb, + tpm_ppi_func4_cb, + tpm_ppi_func5_cb, + tpm_ppi_func6_cb, + tpm_ppi_func7_cb, + tpm_ppi_func8_cb, +}; + +static void tpm_mci_func0_cb(void *arg) +{ + /* Function 1. */ + acpigen_write_return_singleton_buffer(0x3); +} +static void tpm_mci_func1_cb(void *arg) +{ + /* Just return success. */ + acpigen_write_return_byte(0); +} + +static void (*tpm_mci_callbacks[])(void *) = { + tpm_mci_func0_cb, + tpm_mci_func1_cb, +}; + +void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ + /* + * _DSM method + */ + struct dsm_uuid ids[] = { + /* Physical presence interface. + * This is used to submit commands like "Clear TPM" to + * be run at next reboot provided that user confirms + * them. Spec allows user to cancel all commands and/or + * configure BIOS to reject commands. So we pretend that + * user did just this: cancelled everything. If user + * really wants to clear TPM the only option now is to + * do it manually in payload. + */ + DSM_UUID(TPM_PPI_UUID, tpm_ppi_callbacks, + ARRAY_SIZE(tpm_ppi_callbacks), NULL), + /* Memory clearing on boot: just a dummy. */ + DSM_UUID(TPM_MCI_UUID, tpm_mci_callbacks, + ARRAY_SIZE(tpm_mci_callbacks), NULL), + }; + + acpigen_write_dsm_uuid_arr(ids, ARRAY_SIZE(ids)); +} diff --git a/src/drivers/tpm/tpm_ppi.h b/src/drivers/tpm/tpm_ppi.h new file mode 100644 index 0000000000..7662386575 --- /dev/null +++ b/src/drivers/tpm/tpm_ppi.h @@ -0,0 +1,58 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _TPM_PPI_H_ +#define _TPM_PPI_H_ + +#include + +#if CONFIG(HAVE_ACPI_TABLES) +void tpm_ppi_acpi_fill_ssdt(const struct device *dev); +#else +static inline void tpm_ppi_acpi_fill_ssdt(const struct device *dev) +{ +} +#endif + + +/* Return codes */ +/* Function 2 */ +#define PPI2_RET_SUCCESS 0 +#define PPI2_RET_NOT_SUPPORTED 1 +#define PPI2_RET_GENERAL_FAILURE 2 + +/* Function 3 */ +#define PPI3_RET_SUCCESS 0 +#define PPI3_RET_GENERAL_FAILURE 1 + +/* Function 4 */ +#define PPI4_RET_NONE 0 +#define PPI4_RET_SHUTDOWN 1 +#define PPI4_RET_REBOOT 2 +#define PPI4_RET_OS_VENDOR_SPECIFIC 3 + +/* Function 5 */ +#define PPI5_RET_SUCCESS 0 +#define PPI5_RET_GENERAL_FAILURE 1 + +/* Function 6 */ +#define PPI6_RET_NOT_IMPLEMENTED 3 + +/* Function 7 */ +#define PPI7_RET_SUCCESS 0 +#define PPI7_RET_NOT_IMPLEMENTED 1 +#define PPI7_RET_GENERAL_FAILURE 2 +#define PPI7_RET_BLOCKED_BY_FIRMWARE 3 + +/* Function 8 */ +#define PPI8_RET_NOT_IMPLEMENTED 0 +#define PPI8_RET_FIRMWARE_ONLY 1 +#define PPI8_RET_BLOCKED_FOR_OS_BY_FW 2 +#define PPI8_RET_ALLOWED_WITH_PP 3 +#define PPI8_RET_ALLOWED 4 + +/* TCG Physical Presence Interface */ +#define TPM_PPI_UUID "3dddfaa6-361b-4eb4-a424-8d10089d1653" +/* TCG Memory Clear Interface */ +#define TPM_MCI_UUID "376054ed-cc13-4675-901c-4756d7f2d45d" + +#endif /* _TPM_PPI_H_ */ From c248382d5200c15bcb97176c0fd6a8f4ef66343d Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Thu, 19 Nov 2020 08:54:28 +0100 Subject: [PATCH 076/107] vendorcode/eltan/security: Add dependency for menu items Subitem for VENDORCODE_ELTAN_VBOOT and VENDORCODE_ELTAN_MBOOT are always displayed. Add dependency and display these items when feature is enabled only. Tested on Facebook FBG1701. Change-Id: I51e47efddbcf51d87439bec33b85432da56fa4c6 Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/47740 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/vendorcode/eltan/security/mboot/Kconfig | 3 +++ src/vendorcode/eltan/security/verified_boot/Kconfig | 3 +++ 2 files changed, 6 insertions(+) diff --git a/src/vendorcode/eltan/security/mboot/Kconfig b/src/vendorcode/eltan/security/mboot/Kconfig index 91898fc401..540b7b22eb 100644 --- a/src/vendorcode/eltan/security/mboot/Kconfig +++ b/src/vendorcode/eltan/security/mboot/Kconfig @@ -10,8 +10,11 @@ config VENDORCODE_ELTAN_MBOOT Enabling MBOOT will use mboot to measure the components of the firmware (stages, payload, etc). +if VENDORCODE_ELTAN_MBOOT + config VENDORCODE_ELTAN_CRTM_VERSION_STRING string "default CRTM version" default "default CRTM version" +endif # VENDORCODE_ELTAN_MBOOT endmenu # Measured Boot (mboot) diff --git a/src/vendorcode/eltan/security/verified_boot/Kconfig b/src/vendorcode/eltan/security/verified_boot/Kconfig index b4d1378d47..7741782650 100644 --- a/src/vendorcode/eltan/security/verified_boot/Kconfig +++ b/src/vendorcode/eltan/security/verified_boot/Kconfig @@ -8,6 +8,8 @@ config VENDORCODE_ELTAN_VBOOT default n select VBOOT_LIB +if VENDORCODE_ELTAN_VBOOT + config VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST bool "Enable Signed Manifest" depends on VENDORCODE_ELTAN_VBOOT @@ -52,4 +54,5 @@ config VENDORCODE_ELTAN_VBOOT_KEY_SIZE int default 552 +endif # VENDORCODE_ELTAN_VBOOT endmenu # Verified Boot (verified_boot) From 274c3faf093317b835ef3622dff994754209da89 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 2 Oct 2020 08:23:01 +0200 Subject: [PATCH 077/107] crossgcc: Upgrade IASL to version 20200925 This release added support for SMBus predefined names: _SBA, _SBI, _SBR, _SBT and _SBW. CB:44507 and CB:41735 needs this version. Change log: https://acpica.org/node/184 Change-Id: I3559e5bd884db4dccdaa5ac7edba4faf57da7930 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/45750 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer Reviewed-by: Maxim Polyakov --- util/crossgcc/buildgcc | 2 +- ...patch => acpica-unix2-20200925_iasl.patch} | 23 ++++++++++--------- .../sum/acpica-unix2-20200925.tar.gz.cksum | 1 + 3 files changed, 14 insertions(+), 12 deletions(-) rename util/crossgcc/patches/{acpica-unix2-20200717_iasl.patch => acpica-unix2-20200925_iasl.patch} (64%) create mode 100644 util/crossgcc/sum/acpica-unix2-20200925.tar.gz.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index d5cca6cd6e..375e49d88c 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -40,7 +40,7 @@ GCC_VERSION=8.3.0 GCC_AUTOCONF_VERSION=2.69 BINUTILS_VERSION=2.35 GDB_VERSION=9.2 -IASL_VERSION=20200717 +IASL_VERSION=20200925 PYTHON_VERSION=3.8.5 EXPAT_VERSION=2.2.9 # CLANG version number diff --git a/util/crossgcc/patches/acpica-unix2-20200717_iasl.patch b/util/crossgcc/patches/acpica-unix2-20200925_iasl.patch similarity index 64% rename from util/crossgcc/patches/acpica-unix2-20200717_iasl.patch rename to util/crossgcc/patches/acpica-unix2-20200925_iasl.patch index 01dec7c4f3..55adb83af2 100644 --- a/util/crossgcc/patches/acpica-unix2-20200717_iasl.patch +++ b/util/crossgcc/patches/acpica-unix2-20200925_iasl.patch @@ -1,27 +1,28 @@ -diff -Naur acpica-unix2-20200717_/source/compiler/asloptions.c acpica-unix2-20200717/source/compiler/asloptions.c > acpica-unix2-20200717_iasl.patch ---- acpica-unix2-20200717_/source/compiler/asloptions.c -+++ acpica-unix2-20200717/source/compiler/asloptions.c -@@ -126,6 +126,7 @@ - if (Gbl_DoSignon) +diff --git a/source/compiler/asloptions.c b/source/compiler/asloptions.c +index 4bf9465ba..14c61a122 100644 +--- a/source/compiler/asloptions.c ++++ b/source/compiler/asloptions.c +@@ -234,6 +234,7 @@ AslCommandLine ( + if (AslGbl_DoSignon) { printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); + printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); if (AslGbl_IgnoreErrors) { printf ("Ignoring all errors, forcing AML file generation\n\n"); -@@ -753,6 +754,7 @@ +@@ -866,6 +867,7 @@ AslDoOptions ( case '^': - + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); + printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); exit (0); - + case 'a': -@@ -766,6 +768,7 @@ - +@@ -879,6 +881,7 @@ AslDoOptions ( + printf (ACPI_COMMON_SIGNON (ASL_COMPILER_NAME)); printf (ACPI_COMMON_BUILD_TIME); + printf ("%s\n", COREBOOT_TOOLCHAIN_VERSION); exit (0); - + case 'e': diff --git a/util/crossgcc/sum/acpica-unix2-20200925.tar.gz.cksum b/util/crossgcc/sum/acpica-unix2-20200925.tar.gz.cksum new file mode 100644 index 0000000000..fe1665e50d --- /dev/null +++ b/util/crossgcc/sum/acpica-unix2-20200925.tar.gz.cksum @@ -0,0 +1 @@ +3d5fd9725e0229eb009685f4d356ffda488edc02 tarballs/acpica-unix2-20200925.tar.gz From 1ba663ce0ac30f233148345d7e1da4f799fa6e63 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 23 Aug 2020 07:50:32 +0200 Subject: [PATCH 078/107] crossgcc: Upgrade nasm to version 2.15.05 Changes (https://nasm.us/doc/nasmdocc.html): Version 2.15.05: Correct %ifid $ and %ifid $$ being treated as true. Add --reproducible option to suppress NASM version numbers and timestamps in output files. Version 2.15.04: Correct the encoding of the ENQCMDS and TILELOADT1 instructions. Fix case where the COFF backend (the coff, win32 and win64 output formats) would add padding bytes in the middle of a section if a SECTION/SEGMENT directive was provided which repeated an ALIGN= attribute. This neither matched legacy behavior, other backends, or user expectations. Fix SSE instructions not being recognized with an explicit memory operation size (e.g. movsd qword [eax],xmm0). Change-Id: I3f9aa8e743f2dc50fce1ce68718c0ae17209a509 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/44694 Reviewed-by: Stefan Reinauer Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- util/crossgcc/buildgcc | 2 +- util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum | 1 - util/crossgcc/sum/nasm-2.15.05.tar.bz2.cksum | 1 + 3 files changed, 2 insertions(+), 2 deletions(-) delete mode 100644 util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum create mode 100644 util/crossgcc/sum/nasm-2.15.05.tar.bz2.cksum diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 375e49d88c..958a5415ca 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -46,7 +46,7 @@ EXPAT_VERSION=2.2.9 # CLANG version number CLANG_VERSION=10.0.1 CMAKE_VERSION=3.18.1 -NASM_VERSION=2.15.03 +NASM_VERSION=2.15.05 # GCC toolchain archive locations # These are sanitized by the jenkins toolchain test builder, so if diff --git a/util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum deleted file mode 100644 index 6033faeff4..0000000000 --- a/util/crossgcc/sum/nasm-2.15.03.tar.bz2.cksum +++ /dev/null @@ -1 +0,0 @@ -513ac3b800377f10833a02bc7f3fa8b84ca4f2b6 tarballs/nasm-2.15.03.tar.bz2 diff --git a/util/crossgcc/sum/nasm-2.15.05.tar.bz2.cksum b/util/crossgcc/sum/nasm-2.15.05.tar.bz2.cksum new file mode 100644 index 0000000000..4ee4fec61c --- /dev/null +++ b/util/crossgcc/sum/nasm-2.15.05.tar.bz2.cksum @@ -0,0 +1 @@ +c0869e9ac854140bf99c989a711102ce6367243f tarballs/nasm-2.15.05.tar.bz2 From 6be3352e98287959a5bfaf47398fb8bf4de06540 Mon Sep 17 00:00:00 2001 From: David Wu Date: Wed, 18 Nov 2020 13:00:14 +0800 Subject: [PATCH 079/107] mb/google/volteer: Remove unused devices for terrador and todor Remove the following devices - Goodix Touchscreen - SAR0 Proximity Sensor BUG=b:173480406 TEST=FW_NAME=terrador emerge-volteer coreboot chromeos-bootimage Signed-off-by: David Wu Change-Id: I6b56ca136533b53ff7e003a665be67fbe12c1ade Reviewed-on: https://review.coreboot.org/c/coreboot/+/47690 Reviewed-by: Caveh Jalali Reviewed-by: Paul Fagerburg Tested-by: build bot (Jenkins) --- .../volteer/variants/terrador/overridetree.cb | 47 ------------------- .../volteer/variants/todor/overridetree.cb | 47 ------------------- 2 files changed, 94 deletions(-) diff --git a/src/mainboard/google/volteer/variants/terrador/overridetree.cb b/src/mainboard/google/volteer/variants/terrador/overridetree.cb index 2a5b98d891..45f1033910 100644 --- a/src/mainboard/google/volteer/variants/terrador/overridetree.cb +++ b/src/mainboard/google/volteer/variants/terrador/overridetree.cb @@ -100,21 +100,6 @@ chip soc/intel/tigerlake end end device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 14 on end - end chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" @@ -129,38 +114,6 @@ chip soc/intel/tigerlake device i2c 10 on end end end - device ref i2c2 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR0 Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "0" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end device ref i2c5 on chip drivers/i2c/hid register "generic.hid" = ""ELAN2700"" diff --git a/src/mainboard/google/volteer/variants/todor/overridetree.cb b/src/mainboard/google/volteer/variants/todor/overridetree.cb index 6956848790..bbfc016c62 100644 --- a/src/mainboard/google/volteer/variants/todor/overridetree.cb +++ b/src/mainboard/google/volteer/variants/todor/overridetree.cb @@ -102,21 +102,6 @@ chip soc/intel/tigerlake end end device ref i2c1 on - chip drivers/i2c/hid - register "generic.hid" = ""GDIX0000"" - register "generic.desc" = ""Goodix Touchscreen"" - register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_E7_IRQ)" - register "generic.probed" = "1" - register "generic.reset_gpio" = - "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)" - register "generic.reset_delay_ms" = "120" - register "generic.reset_off_delay_ms" = "3" - register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)" - register "generic.enable_delay_ms" = "12" - register "generic.has_power_resource" = "1" - register "hid_desc_reg_offset" = "0x01" - device i2c 14 on end - end chip drivers/i2c/hid register "generic.hid" = ""ELAN90FC"" register "generic.desc" = ""ELAN Touchscreen"" @@ -131,38 +116,6 @@ chip soc/intel/tigerlake device i2c 10 on end end end - device ref i2c2 on - chip drivers/i2c/sx9310 - register "desc" = ""SAR0 Proximity Sensor"" - register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_F14_IRQ)" - register "speed" = "I2C_SPEED_FAST" - register "uid" = "0" - register "reg_prox_ctrl0" = "0x10" - register "reg_prox_ctrl1" = "0x00" - register "reg_prox_ctrl2" = "0x84" - register "reg_prox_ctrl3" = "0x0e" - register "reg_prox_ctrl4" = "0x07" - register "reg_prox_ctrl5" = "0xc6" - register "reg_prox_ctrl6" = "0x20" - register "reg_prox_ctrl7" = "0x0d" - register "reg_prox_ctrl8" = "0x8d" - register "reg_prox_ctrl9" = "0x43" - register "reg_prox_ctrl10" = "0x1f" - register "reg_prox_ctrl11" = "0x00" - register "reg_prox_ctrl12" = "0x00" - register "reg_prox_ctrl13" = "0x00" - register "reg_prox_ctrl14" = "0x00" - register "reg_prox_ctrl15" = "0x00" - register "reg_prox_ctrl16" = "0x00" - register "reg_prox_ctrl17" = "0x00" - register "reg_prox_ctrl18" = "0x00" - register "reg_prox_ctrl19" = "0x00" - register "reg_sar_ctrl0" = "0x50" - register "reg_sar_ctrl1" = "0x8a" - register "reg_sar_ctrl2" = "0x3c" - device i2c 28 on end - end - end device ref i2c5 on chip drivers/i2c/hid register "generic.hid" = ""ELAN2700"" From 08b862ef47bb5f4401b9d4dea4f77cba14bdbd5e Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Mon, 16 Nov 2020 16:31:23 -0700 Subject: [PATCH 080/107] nb/amd/pi: Remove 00660F01 directory & files These files are not used by any platform, so remove them. Signed-off-by: Martin Roth Change-Id: I75651d2cc53fc5a3cb3233686ad66881d129312d Reviewed-on: https://review.coreboot.org/c/coreboot/+/47649 Tested-by: build bot (Jenkins) Reviewed-by: Marshall Dawson Reviewed-by: Angel Pons --- src/northbridge/amd/pi/00660F01/Kconfig | 32 - src/northbridge/amd/pi/00660F01/Makefile.inc | 5 - .../amd/pi/00660F01/acpi/northbridge.asl | 154 --- src/northbridge/amd/pi/00660F01/chip.h | 11 - src/northbridge/amd/pi/00660F01/dimmSpd.c | 39 - src/northbridge/amd/pi/00660F01/northbridge.c | 945 ------------------ src/northbridge/amd/pi/Makefile.inc | 1 - 7 files changed, 1187 deletions(-) delete mode 100644 src/northbridge/amd/pi/00660F01/Kconfig delete mode 100644 src/northbridge/amd/pi/00660F01/Makefile.inc delete mode 100644 src/northbridge/amd/pi/00660F01/acpi/northbridge.asl delete mode 100644 src/northbridge/amd/pi/00660F01/chip.h delete mode 100644 src/northbridge/amd/pi/00660F01/dimmSpd.c delete mode 100644 src/northbridge/amd/pi/00660F01/northbridge.c diff --git a/src/northbridge/amd/pi/00660F01/Kconfig b/src/northbridge/amd/pi/00660F01/Kconfig deleted file mode 100644 index e42ba80f0d..0000000000 --- a/src/northbridge/amd/pi/00660F01/Kconfig +++ /dev/null @@ -1,32 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -config NORTHBRIDGE_AMD_PI_00660F01 - bool - select RESOURCE_ALLOCATOR_V3 - -if NORTHBRIDGE_AMD_PI_00660F01 - -config HW_MEM_HOLE_SIZEK - hex - default 0x100000 - -config MMCONF_BASE_ADDRESS - hex - default 0xF8000000 - -config MMCONF_BUS_NUMBER - int - default 64 - -config VGA_BIOS_ID - string - default "1002,9870" - help - The default VGA BIOS PCI vendor/device ID should be set to the - result of the map_oprom_vendev() function in northbridge.c. - -config VGA_BIOS_FILE - string - default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin" - -endif diff --git a/src/northbridge/amd/pi/00660F01/Makefile.inc b/src/northbridge/amd/pi/00660F01/Makefile.inc deleted file mode 100644 index 7fd37f2611..0000000000 --- a/src/northbridge/amd/pi/00660F01/Makefile.inc +++ /dev/null @@ -1,5 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -romstage-y += dimmSpd.c - -ramstage-y += northbridge.c diff --git a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl b/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl deleted file mode 100644 index ada775dcf5..0000000000 --- a/src/northbridge/amd/pi/00660F01/acpi/northbridge.asl +++ /dev/null @@ -1,154 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -/* Note: Only need HID on Primary Bus */ -External (TOM1) -External (TOM2) -Name(_HID, EISAID("PNP0A08")) /* PCI Express Root Bridge */ -Name(_CID, EISAID("PNP0A03")) /* PCI Root Bridge */ - -/* Describe the Northbridge devices */ - -Method(_BBN, 0, NotSerialized) /* Bus number = 0 */ -{ - Return(Zero) -} - -Method(_STA, 0, NotSerialized) -{ - Return(0x0B) /* Status is visible */ -} - -Method(_PRT,0, NotSerialized) -{ - If(PMOD) - { - Return(APR0) /* APIC mode */ - } - Return (PR0) /* PIC Mode */ -} - -Device(AMRT) { - Name(_ADR, 0x00000000) -} /* end AMRT */ - -/* Gpp 0 */ -Device(PBR4) { - Name(_ADR, 0x00020001) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS4) } /* APIC mode */ - Return (PS4) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR4 */ - -/* Gpp 1 */ -Device(PBR5) { - Name(_ADR, 0x00020002) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS5) } /* APIC mode */ - Return (PS5) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR5 */ - -/* Gpp 2 */ -Device(PBR6) { - Name(_ADR, 0x00020003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS6) } /* APIC mode */ - Return (PS6) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR6 */ - -/* Gpp 3 */ -Device(PBR7) { - Name(_ADR, 0x00020004) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS7) } /* APIC mode */ - Return (PS7) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR7 */ - -/* Gpp 4 */ -Device(PBR8) { - Name(_ADR, 0x00020005) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APS8) } /* APIC mode */ - Return (PS8) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 1 */ -Device(PBR9) { - Name(_ADR, 0x00030002) -} /* end PBR8 */ - -/* GFX 2 */ -Device(PBRA) { - Name(_ADR, 0x00030003) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APSA) } /* APIC mode */ - Return (PSA) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 3 */ -Device(PBRB) { - Name(_ADR, 0x00030004) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APSB) } /* APIC mode */ - Return (PSB) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -/* GFX 4 */ -Device(PBRC) { - Name(_ADR, 0x00030005) - Name(_PRW, Package() {0x18, 4}) - Method(_PRT,0) { - If(PMOD) { Return(APSC) } /* APIC mode */ - Return (PSC) /* PIC Mode */ - } /* end _PRT */ -} /* end PBR8 */ - -Device(AZHD) { /* 0:9.2 - HD Audio */ - Name(_ADR, 0x00090002) - OperationRegion(AZPD, PCI_Config, 0x00, 0x100) - Field(AZPD, AnyAcc, NoLock, Preserve) { - offset (0x42), - NSDI, 1, - NSDO, 1, - NSEN, 1, - offset (0x44), - IPCR, 4, - offset (0x54), - PWST, 2, - , 6, - PMEB, 1, - , 6, - PMST, 1, - offset (0x62), - MMCR, 1, - offset (0x64), - MMLA, 32, - offset (0x68), - MMHA, 32, - offset (0x6C), - MMDT, 16, - } - - Method (_INI, 0, NotSerialized) - { - If (LEqual (OSVR, 0x03)) - { - Store (Zero, NSEN) - Store (One, NSDO) - Store (One, NSDI) - } - } -} /* end AZHD */ diff --git a/src/northbridge/amd/pi/00660F01/chip.h b/src/northbridge/amd/pi/00660F01/chip.h deleted file mode 100644 index 1cc7f69ae3..0000000000 --- a/src/northbridge/amd/pi/00660F01/chip.h +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef _PI_FAM15CZ_CHIP_H_ -#define _PI_FAM15CZ_CHIP_H_ - -struct northbridge_amd_pi_00660F01_config -{ - u8 spdAddrLookup[2][2][4]; -}; - -#endif diff --git a/src/northbridge/amd/pi/00660F01/dimmSpd.c b/src/northbridge/amd/pi/00660F01/dimmSpd.c deleted file mode 100644 index 0a1281fbb0..0000000000 --- a/src/northbridge/amd/pi/00660F01/dimmSpd.c +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -/* warning: Porting.h includes an open #pragma pack(1) */ -#include -#include -#include "chip.h" -#include - -AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINTN unused2, AGESA_READ_SPD_PARAMS *info) -{ - int spdAddress; - DEVTREE_CONST struct device *dev = pcidev_on_root(0x18, 2); - - if (dev == NULL) - return AGESA_ERROR; - - DEVTREE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info; - - if (config == NULL) - return AGESA_ERROR; - - if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup)) - return AGESA_ERROR; - if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0])) - return AGESA_ERROR; - if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0])) - return AGESA_ERROR; - spdAddress = config->spdAddrLookup - [info->SocketId] [info->MemChannelId] [info->DimmId]; - if (spdAddress == 0) - return AGESA_ERROR; - int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128); - if (err) - return AGESA_ERROR; - return AGESA_SUCCESS; -} diff --git a/src/northbridge/amd/pi/00660F01/northbridge.c b/src/northbridge/amd/pi/00660F01/northbridge.c deleted file mode 100644 index 09bdd82e9f..0000000000 --- a/src/northbridge/amd/pi/00660F01/northbridge.c +++ /dev/null @@ -1,945 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include -#include - -#define MAX_NODE_NUMS MAX_NODES - -typedef struct dram_base_mask { - u32 base; //[47:27] at [28:8] - u32 mask; //[47:27] at [28:8] and enable at bit 0 -} dram_base_mask_t; - -static unsigned int node_nums; -static unsigned int sblink; -static struct device *__f0_dev[MAX_NODE_NUMS]; -static struct device *__f1_dev[MAX_NODE_NUMS]; -static struct device *__f2_dev[MAX_NODE_NUMS]; -static struct device *__f4_dev[MAX_NODE_NUMS]; -static unsigned int fx_devs = 0; - -static dram_base_mask_t get_dram_base_mask(u32 nodeid) -{ - struct device *dev; - dram_base_mask_t d; - dev = __f1_dev[0]; - u32 temp; - temp = pci_read_config32(dev, 0x44 + (nodeid << 3)); //[39:24] at [31:16] - d.mask = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramMask [26:24] too - temp = pci_read_config32(dev, 0x144 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] - d.mask |= temp << 21; - temp = pci_read_config32(dev, 0x40 + (nodeid << 3)); //[39:24] at [31:16] - d.mask |= (temp & 1); // enable bit - d.base = ((temp & 0xfff80000) >> (8 + 3)); // mask out DramBase [26:24) too - temp = pci_read_config32(dev, 0x140 + (nodeid << 3)) & 0xff; //[47:40] at [7:0] - d.base |= temp << 21; - return d; -} - -static void set_io_addr_reg(struct device *dev, u32 nodeid, u32 linkn, u32 reg, - u32 io_min, u32 io_max) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid & 0xf) | ((nodeid & 0x30) << (8 - 4)) | (linkn << 4) | ((io_max & 0xf0)<<(12 - 4)); //limit - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg + 4, tempreg); - tempreg = 3 | ((io_min & 0xf0) << (12 - 4)); //base :ISA and VGA ? - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static void set_mmio_addr_reg(u32 nodeid, u32 linkn, u32 reg, u32 index, u32 mmio_min, u32 mmio_max, u32 nodes) -{ - u32 i; - u32 tempreg; - /* io range allocation */ - tempreg = (nodeid&0xf) | (linkn<<4) | (mmio_max&0xffffff00); //limit - for (i = 0; i < nodes; i++) - pci_write_config32(__f1_dev[i], reg+4, tempreg); - tempreg = 3 | (nodeid & 0x30) | (mmio_min&0xffffff00); - for (i = 0; i < node_nums; i++) - pci_write_config32(__f1_dev[i], reg, tempreg); -} - -static struct device *get_node_pci(u32 nodeid, u32 fn) -{ - return pcidev_on_root(DEV_CDB + nodeid, fn); -} - -static void get_fx_devs(void) -{ - int i; - for (i = 0; i < MAX_NODE_NUMS; i++) { - __f0_dev[i] = get_node_pci(i, 0); - __f1_dev[i] = get_node_pci(i, 1); - __f2_dev[i] = get_node_pci(i, 2); - __f4_dev[i] = get_node_pci(i, 4); - if (__f0_dev[i] != NULL && __f1_dev[i] != NULL) - fx_devs = i+1; - } - if (__f1_dev[0] == NULL || __f0_dev[0] == NULL || fx_devs == 0) { - die("Cannot find 0:0x18.[0|1]\n"); - } - printk(BIOS_DEBUG, "fx_devs = 0x%x\n", fx_devs); -} - -static u32 f1_read_config32(unsigned int reg) -{ - if (fx_devs == 0) - get_fx_devs(); - return pci_read_config32(__f1_dev[0], reg); -} - -static void f1_write_config32(unsigned int reg, u32 value) -{ - int i; - if (fx_devs == 0) - get_fx_devs(); - for (i = 0; i < fx_devs; i++) { - struct device *dev; - dev = __f1_dev[i]; - if (dev && dev->enabled) { - pci_write_config32(dev, reg, value); - } - } -} - -static u32 amdfam15_nodeid(struct device *dev) -{ - return (dev->path.pci.devfn >> 3) - DEV_CDB; -} - -static void set_vga_enable_reg(u32 nodeid, u32 linkn) -{ - u32 val; - - val = 1 | (nodeid << 4) | (linkn<<12); - /* it will routing - * (1)mmio 0xa0000:0xbffff - * (2)io 0x3b0:0x3bb, 0x3c0:0x3df - */ - f1_write_config32(0xf4, val); - -} - -/** - * @return - * @retval 2 resource does not exist, usable - * @retval 0 resource exists, not usable - * @retval 1 resource exist, resource has been allocated before - */ -static int reg_useable(unsigned int reg, struct device *goal_dev, unsigned int goal_nodeid, - unsigned int goal_link) -{ - struct resource *res; - unsigned int nodeid, link = 0; - int result; - res = 0; - for (nodeid = 0; !res && (nodeid < fx_devs); nodeid++) { - struct device *dev; - dev = __f0_dev[nodeid]; - if (!dev) - continue; - for (link = 0; !res && (link < 8); link++) - res = probe_resource(dev, IOINDEX(0x1000 + reg, link)); - } - - if (!res) - result = 2; - else if ((goal_link == (link - 1)) && - (goal_nodeid == (nodeid - 1)) && - (res->flags <= 1)) { - result = 1; - } - else - result = 0; - - return result; -} - -static struct resource *amdfam15_find_iopair(struct device *dev, unsigned int nodeid, unsigned int link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0xc0; reg <= 0xd8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result >= 1) { - free_reg = reg; - } - if (result == 1) { - /* resource allocated */ - break; - } - } - resource = new_resource(dev, IOINDEX(0x1000 + free_reg, link)); - return resource; -} - -static struct resource *amdfam15_find_mempair(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - u32 free_reg, reg; - resource = 0; - free_reg = 0; - for (reg = 0x80; reg <= 0xb8; reg += 0x8) { - int result; - result = reg_useable(reg, dev, nodeid, link); - if (result >= 1) { - free_reg = reg; - } - if (result == 1) { - /* I have been allocated this one */ - break; - } - } - resource = new_resource(dev, IOINDEX(0x1000 + free_reg, link)); - return resource; -} - -static void amdfam15_link_read_bases(struct device *dev, u32 nodeid, u32 link) -{ - struct resource *resource; - - /* Initialize the io space constraints on the current bus */ - resource = amdfam15_find_iopair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_IO_HOST_ALIGN); - resource->gran = log2(HT_IO_HOST_ALIGN); - resource->limit = 0xffffUL; - resource->flags = IORESOURCE_IO | IORESOURCE_BRIDGE; - } - - /* Initialize the prefetchable memory constraints on the current bus */ - resource = amdfam15_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_PREFETCH; - resource->flags |= IORESOURCE_BRIDGE; - } - - /* Initialize the memory constraints on the current bus */ - resource = amdfam15_find_mempair(dev, nodeid, link); - if (resource) { - resource->base = 0; - resource->size = 0; - resource->align = log2(HT_MEM_HOST_ALIGN); - resource->gran = log2(HT_MEM_HOST_ALIGN); - resource->limit = 0xffffffffffULL; - resource->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE; - } - -} - -static void read_resources(struct device *dev) -{ - u32 nodeid; - struct bus *link; - - nodeid = amdfam15_nodeid(dev); - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - amdfam15_link_read_bases(dev, nodeid, link->link_num); - } - } - - /* - * This MMCONF resource must be reserved in the PCI domain. - * It is not honored by the coreboot resource allocator if it is in - * the CPU_CLUSTER. - */ - mmconf_resource(dev, MMIO_CONF_BASE); -} - -static void set_resource(struct device *dev, struct resource *resource, u32 nodeid) -{ - resource_t rbase, rend; - unsigned int reg, link_num; - char buf[50]; - - /* Make certain the resource has actually been set */ - if (!(resource->flags & IORESOURCE_ASSIGNED)) - return; - - /* If I have already stored this resource don't worry about it */ - if (resource->flags & IORESOURCE_STORED) - return; - - /* Only handle PCI memory and IO resources */ - if (!(resource->flags & (IORESOURCE_MEM | IORESOURCE_IO))) - return; - - /* Ensure I am actually looking at a resource of function 1 */ - if ((resource->index & 0xffff) < 0x1000) - return; - - /* Get the base address */ - rbase = resource->base; - - /* Get the limit (rounded up) */ - rend = resource_end(resource); - - /* Get the register and link */ - reg = resource->index & 0xfff; // 4k - link_num = IOINDEX_LINK(resource->index); - - if (resource->flags & IORESOURCE_IO) { - set_io_addr_reg(dev, nodeid, link_num, reg, rbase>>8, rend>>8); - } - else if (resource->flags & IORESOURCE_MEM) { - set_mmio_addr_reg(nodeid, link_num, reg, (resource->index >>24), rbase>>8, rend>>8, node_nums); // [39:8] - } - resource->flags |= IORESOURCE_STORED; - snprintf(buf, sizeof(buf), " ", - nodeid, link_num); - report_resource_stored(dev, resource, buf); -} - -/** - * I tried to reuse the resource allocation code in set_resource() - * but it is too difficult to deal with the resource allocation magic. - */ - -static void create_vga_resource(struct device *dev, unsigned int nodeid) -{ - struct bus *link; - - /* find out which link the VGA card is connected, - * we only deal with the 'first' vga card */ - for (link = dev->link_list; link; link = link->next) { - if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) { -#if CONFIG(MULTIPLE_VGA_ADAPTERS) - extern struct device *vga_pri; // the primary vga device, defined in device.c - printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary, - link->secondary,link->subordinate); - /* We need to make sure the vga_pri is under the link */ - if ((vga_pri->bus->secondary >= link->secondary) && - (vga_pri->bus->secondary <= link->subordinate)) -#endif - break; - } - } - - /* no VGA card installed */ - if (link == NULL) - return; - - printk(BIOS_DEBUG, "VGA: %s (aka node %d) link %d has VGA device\n", dev_path(dev), nodeid, sblink); - set_vga_enable_reg(nodeid, sblink); -} - -static void set_resources(struct device *dev) -{ - unsigned int nodeid; - struct bus *bus; - struct resource *res; - - /* Find the nodeid */ - nodeid = amdfam15_nodeid(dev); - - /* do we need this? */ - create_vga_resource(dev, nodeid); - - /* Set each resource we have found */ - for (res = dev->resource_list; res; res = res->next) { - set_resource(dev, res, nodeid); - } - - for (bus = dev->link_list; bus; bus = bus->next) { - if (bus->children) { - assign_resources(bus); - } - } -} - -static void northbridge_init(struct device *dev) -{ -} - -static unsigned long acpi_fill_hest(acpi_hest_t *hest) -{ - void *addr, *current; - - /* Skip the HEST header. */ - current = (void *)(hest + 1); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_MCE); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 0, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); - - addr = agesawrapper_getlateinitptr(PICK_WHEA_CMC); - if (addr != NULL) - current += acpi_create_hest_error_source(hest, current, 1, (void *)((u32)addr + 2), *(UINT16 *)addr - 2); - - return (unsigned long)current; -} - -static void northbridge_fill_ssdt_generator(const struct device *device) -{ - msr_t msr; - char pscope[] = "\\_SB.PCI0"; - - acpigen_write_scope(pscope); - msr = rdmsr(TOP_MEM); - acpigen_write_name_dword("TOM1", msr.lo); - msr = rdmsr(TOP_MEM2); - /* - * Since XP only implements parts of ACPI 2.0, we can't use a qword - * here. - * See http://www.acpi.info/presentations/S01USMOBS169_OS%2520new.ppt - * slide 22ff. - * Shift value right by 20 bit to make it fit into 32bit, - * giving us 1MB granularity and a limit of almost 4Exabyte of memory. - */ - acpigen_write_name_dword("TOM2", (msr.hi << 12) | msr.lo >> 20); - acpigen_pop_len(); -} - -static void patch_ssdt_processor_scope(acpi_header_t *ssdt) -{ - unsigned int len = ssdt->length - sizeof(acpi_header_t); - unsigned int i; - - for (i = sizeof(acpi_header_t); i < len; i++) { - /* Search for _PR_ scope and replace it with _SB_ */ - if (*(uint32_t *)((unsigned long)ssdt + i) == 0x5f52505f) - *(uint32_t *)((unsigned long)ssdt + i) = 0x5f42535f; - } - /* Recalculate checksum */ - ssdt->checksum = 0; - ssdt->checksum = acpi_checksum((void *)ssdt, ssdt->length); -} - -static unsigned long agesa_write_acpi_tables(const struct device *device, - unsigned long current, - acpi_rsdp_t *rsdp) -{ - acpi_srat_t *srat; - acpi_slit_t *slit; - acpi_header_t *ssdt; - acpi_header_t *alib; - acpi_header_t *ivrs; - acpi_hest_t *hest; - - /* HEST */ - current = ALIGN(current, 8); - hest = (acpi_hest_t *)current; - acpi_write_hest((void *)current, acpi_fill_hest); - acpi_add_table(rsdp, (void *)current); - current += ((acpi_header_t *)current)->length; - - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * IVRS at %lx\n", current); - ivrs = agesawrapper_getlateinitptr(PICK_IVRS); - if (ivrs != NULL) { - memcpy((void *)current, ivrs, ivrs->length); - ivrs = (acpi_header_t *) current; - current += ivrs->length; - acpi_add_table(rsdp, ivrs); - } else { - printk(BIOS_DEBUG, " AGESA IVRS table NULL. Skipping.\n"); - } - - /* SRAT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SRAT at %lx\n", current); - srat = (acpi_srat_t *) agesawrapper_getlateinitptr (PICK_SRAT); - if (srat != NULL) { - memcpy((void *)current, srat, srat->header.length); - srat = (acpi_srat_t *) current; - current += srat->header.length; - acpi_add_table(rsdp, srat); - } else { - printk(BIOS_DEBUG, " AGESA SRAT table NULL. Skipping.\n"); - } - - /* SLIT */ - current = ALIGN(current, 8); - printk(BIOS_DEBUG, "ACPI: * SLIT at %lx\n", current); - slit = (acpi_slit_t *) agesawrapper_getlateinitptr (PICK_SLIT); - if (slit != NULL) { - memcpy((void *)current, slit, slit->header.length); - slit = (acpi_slit_t *) current; - current += slit->header.length; - acpi_add_table(rsdp, slit); - } else { - printk(BIOS_DEBUG, " AGESA SLIT table NULL. Skipping.\n"); - } - - /* ALIB */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * AGESA ALIB SSDT at %lx\n", current); - alib = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_ALIB); - if (alib != NULL) { - memcpy((void *)current, alib, alib->length); - alib = (acpi_header_t *) current; - current += alib->length; - acpi_add_table(rsdp, (void *)alib); - } - else { - printk(BIOS_DEBUG, " AGESA ALIB SSDT table NULL. Skipping.\n"); - } - - /* this pstate ssdt may cause Blue Screen: Fixed: Keep this comment for a while. */ - /* SSDT */ - current = ALIGN(current, 16); - printk(BIOS_DEBUG, "ACPI: * SSDT at %lx\n", current); - ssdt = (acpi_header_t *)agesawrapper_getlateinitptr (PICK_PSTATE); - if (ssdt != NULL) { - patch_ssdt_processor_scope(ssdt); - memcpy((void *)current, ssdt, ssdt->length); - ssdt = (acpi_header_t *) current; - current += ssdt->length; - } - else { - printk(BIOS_DEBUG, " AGESA PState table NULL. Skipping.\n"); - } - acpi_add_table(rsdp,ssdt); - - printk(BIOS_DEBUG, "ACPI: * SSDT for PState at %lx\n", current); - return current; -} - -static struct device_operations northbridge_operations = { - .read_resources = read_resources, - .set_resources = set_resources, - .enable_resources = pci_dev_enable_resources, - .init = northbridge_init, - .acpi_fill_ssdt = northbridge_fill_ssdt_generator, - .write_acpi_tables = agesa_write_acpi_tables, -}; - -static const struct pci_driver family15_northbridge __pci_driver = { - .ops = &northbridge_operations, - .vendor = PCI_VENDOR_ID_AMD, - .device = PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT, -}; - -static void fam15_finalize(void *chip_info) -{ - struct device *dev; - u32 value; - dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ - pci_write_config32(dev, 0xF8, 0); - pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ - - /* disable No Snoop */ - dev = pcidev_on_root(1, 1); - if (dev != NULL) { - value = pci_read_config32(dev, 0x60); - value &= ~(1 << 11); - pci_write_config32(dev, 0x60, value); - } -} - -struct chip_operations northbridge_amd_pi_00660F01_ops = { - CHIP_NAME("AMD FAM15 Northbridge") - .enable_dev = 0, - .final = fam15_finalize, -}; - -static void domain_read_resources(struct device *dev) -{ - unsigned int reg; - - /* Find the already assigned resource pairs */ - get_fx_devs(); - for (reg = 0x80; reg <= 0xd8; reg += 0x08) { - u32 base, limit; - base = f1_read_config32(reg); - limit = f1_read_config32(reg + 0x04); - /* Is this register allocated? */ - if ((base & 3) != 0) { - unsigned int nodeid, reg_link; - struct device *reg_dev; - if (reg < 0xc0) { // mmio - nodeid = (limit & 0xf) + (base & 0x30); - } else { // io - nodeid = (limit & 0xf) + ((base >> 4) & 0x30); - } - reg_link = (limit >> 4) & 7; - reg_dev = __f0_dev[nodeid]; - if (reg_dev) { - /* Reserve the resource */ - struct resource *res; - res = new_resource(reg_dev, IOINDEX(0x1000 + reg, reg_link)); - if (res) { - res->flags = 1; - } - } - } - } - /* FIXME: do we need to check extend conf space? - I don't believe that much preset value */ - - pci_domain_read_resources(dev); -} - -static void domain_enable_resources(struct device *dev) -{ -} - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 -struct hw_mem_hole_info { - unsigned int hole_startk; - int node_id; -}; -static struct hw_mem_hole_info get_hw_mem_hole_info(void) -{ - struct hw_mem_hole_info mem_hole; - int i; - mem_hole.hole_startk = CONFIG_HW_MEM_HOLE_SIZEK; - mem_hole.node_id = -1; - for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; - u32 hole; - d = get_dram_base_mask(i); - if (!(d.mask & 1)) continue; // no memory on this node - hole = pci_read_config32(__f1_dev[i], 0xf0); - if (hole & 2) { - /* we find the hole */ - mem_hole.hole_startk = (hole & (0xff<<24)) >> 10; - mem_hole.node_id = i; // record the node No with hole - break; // only one hole - } - } - - /* We need to double check if there is special set on base reg and limit reg - * are not continuous instead of hole, it will find out its hole_startk. - */ - if (mem_hole.node_id == -1) { - resource_t limitk_pri = 0; - for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; - resource_t base_k, limit_k; - d = get_dram_base_mask(i); - if (!(d.base & 1)) - continue; - base_k = ((resource_t)(d.base & 0x1fffff00)) <<9; - if (base_k > 4 *1024 * 1024) break; // don't need to go to check - if (limitk_pri != base_k) { // we find the hole - mem_hole.hole_startk = (unsigned int)limitk_pri; // must be below 4G - mem_hole.node_id = i; - break; //only one hole - } - limit_k = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; - limitk_pri = limit_k; - } - } - return mem_hole; -} -#endif - -static void domain_set_resources(struct device *dev) -{ - unsigned long mmio_basek; - u32 pci_tolm; - int i, idx; - struct bus *link; -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - struct hw_mem_hole_info mem_hole; -#endif - - pci_tolm = 0xffffffffUL; - for (link = dev->link_list; link; link = link->next) { - pci_tolm = find_pci_tolm(link); - } - - mmio_basek = pci_tolm >> 10; - /* Round mmio_basek to something the processor can support */ - mmio_basek &= ~((1 << 6) -1); - - /* FIXME improve mtrr.c so we don't use up all of the mtrrs with a 64M - * MMIO hole. If you fix this here, please fix amdk8, too. - */ - /* Round the mmio hole to 64M */ - mmio_basek &= ~((64*1024) - 1); - -#if CONFIG_HW_MEM_HOLE_SIZEK != 0 - /* if the hw mem hole is already set in raminit stage, here we will compare - * mmio_basek and hole_basek. if mmio_basek is bigger that hole_basek and will - * use hole_basek as mmio_basek and we don't need to reset hole. - * otherwise We reset the hole to the mmio_basek - */ - - mem_hole = get_hw_mem_hole_info(); - - /* Use hole_basek as mmio_basek, and we don't need to reset hole anymore */ - if ((mem_hole.node_id != -1) && (mmio_basek > mem_hole.hole_startk)) { - mmio_basek = mem_hole.hole_startk; - } -#endif - - idx = 0x10; - for (i = 0; i < node_nums; i++) { - dram_base_mask_t d; - resource_t basek, limitk, sizek; // 4 1T - - d = get_dram_base_mask(i); - - if (!(d.mask & 1)) - continue; - basek = ((resource_t)(d.base & 0x1fffff00)) << 9; // could overflow, we may lost 6 bit here - limitk = ((resource_t)(((d.mask & ~1) + 0x000FF) & 0x1fffff00)) << 9; - - sizek = limitk - basek; - - /* see if we need a hole from 0xa0000 to 0xbffff */ - if ((basek < ((8*64)+(8*16))) && (sizek > ((8*64)+(16*16)))) { - ram_resource(dev, (idx | i), basek, ((8*64)+(8*16)) - basek); - idx += 0x10; - basek = (8*64)+(16*16); - sizek = limitk - ((8*64)+(16*16)); - - } - - /* split the region to accommodate pci memory space */ - if ((basek < 4*1024*1024) && (limitk > mmio_basek)) { - if (basek <= mmio_basek) { - unsigned int pre_sizek; - pre_sizek = mmio_basek - basek; - if (pre_sizek > 0) { - ram_resource(dev, (idx | i), basek, pre_sizek); - idx += 0x10; - sizek -= pre_sizek; - } - basek = mmio_basek; - } - if ((basek + sizek) <= 4*1024*1024) { - sizek = 0; - } - else { - uint64_t topmem2 = bsp_topmem2(); - basek = 4*1024*1024; - sizek = topmem2/1024 - basek; - } - } - - ram_resource(dev, (idx | i), basek, sizek); - idx += 0x10; - printk(BIOS_DEBUG, "node %d: mmio_basek=%08lx, basek=%08llx, limitk=%08llx\n", - i, mmio_basek, basek, limitk); - } - - add_uma_resource_below_tolm(dev, 7); - - for (link = dev->link_list; link; link = link->next) { - if (link->children) { - assign_resources(link); - } - } -} - -static const char *domain_acpi_name(const struct device *dev) -{ - if (dev->path.type == DEVICE_PATH_DOMAIN) - return "PCI0"; - - return NULL; -} - -static struct device_operations pci_domain_ops = { - .read_resources = domain_read_resources, - .set_resources = domain_set_resources, - .enable_resources = domain_enable_resources, - .scan_bus = pci_domain_scan_bus, - .acpi_name = domain_acpi_name, -}; - -static void sysconf_init(struct device *dev) // first node -{ - sblink = (pci_read_config32(dev, 0x64)>>8) & 7; // don't forget sublink1 - node_nums = ((pci_read_config32(dev, 0x60)>>4) & 7) + 1; // NodeCnt[2:0] -} - -static void cpu_bus_scan(struct device *dev) -{ - struct bus *cpu_bus; - struct device *dev_mc; - int i,j; - int coreid_bits; - int core_max = 0; - unsigned int ApicIdCoreIdSize; - unsigned int core_nums; - int siblings = 0; - unsigned int family; - u32 modules = 0; - int ioapic_count = 0; - - /* For binaryPI there is no multiprocessor configuration, the number of - * modules will always be 1. */ - modules = 1; - ioapic_count = CONFIG_NUM_OF_IOAPICS; - - dev_mc = pcidev_on_root(DEV_CDB, 0); - if (!dev_mc) { - printk(BIOS_ERR, "0:%02x.0 not found", DEV_CDB); - die(""); - } - sysconf_init(dev_mc); - - /* Get Max Number of cores(MNC) */ - coreid_bits = (cpuid_ecx(0x80000008) & 0x0000F000) >> 12; - core_max = 1 << (coreid_bits & 0x000F); //mnc - - ApicIdCoreIdSize = ((cpuid_ecx(0x80000008)>>12) & 0xF); - if (ApicIdCoreIdSize) { - core_nums = (1 << ApicIdCoreIdSize) - 1; - } else { - core_nums = 3; //quad core - } - - /* Find which cpus are present */ - cpu_bus = dev->link_list; - for (i = 0; i < node_nums; i++) { - struct device *cdb_dev; - unsigned int devn; - struct bus *pbus; - - devn = DEV_CDB + i; - pbus = dev_mc->bus; - - /* Find the cpu's pci device */ - cdb_dev = pcidev_on_root(devn, 0); - if (!cdb_dev) { - /* If I am probing things in a weird order - * ensure all of the cpu's pci devices are found. - */ - int fn; - for (fn = 0; fn <= 5; fn++) { //FBDIMM? - cdb_dev = pci_probe_dev(NULL, pbus, - PCI_DEVFN(devn, fn)); - } - cdb_dev = pcidev_on_root(devn, 0); - } else { - /* Ok, We need to set the links for that device. - * otherwise the device under it will not be scanned - */ - add_more_links(cdb_dev, 4); - } - - family = cpuid_eax(1); - family = (family >> 20) & 0xFF; - if (family == 6 || family == 7) { - /* f15 and f16 */ - cdb_dev = pcidev_on_root(devn, 5); - if (cdb_dev && cdb_dev->enabled) { - siblings = pci_read_config32(cdb_dev, 0x84); - siblings &= 0xFF; - } - } else { - /* default one core */ - siblings = 0; - } - int enable_node = cdb_dev && cdb_dev->enabled; - printk(BIOS_SPEW, "%s family%xh, core_max = 0x%x, core_nums = 0x%x, siblings = 0x%x\n", - dev_path(cdb_dev), 0x0f + family, core_max, core_nums, siblings); - - for (j = 0; j <= siblings; j++) { - u32 lapicid_start = 0; - - /* - * APIC ID calculation is tightly coupled with AGESA v5 code. - * This calculation MUST match the assignment calculation done - * in LocalApicInitializationAtEarly() function. - * And reference GetLocalApicIdForCore() - * - * Apply APIC enumeration rules - * For systems with >= 16 APICs, put the IO-APICs at 0..n and - * put the local-APICs at m..z - * - * This is needed because many IO-APIC devices only have 4 bits - * for their APIC id and therefore must reside at 0..15 - */ - if ((node_nums * core_max) + ioapic_count >= 0x10) { - lapicid_start = (ioapic_count - 1) / core_max; - lapicid_start = (lapicid_start + 1) * core_max; - printk(BIOS_SPEW, "lpaicid_start = 0x%x ", lapicid_start); - } - u32 apic_id = (lapicid_start * (i/modules + 1)) + ((i % modules) ? (j + (siblings + 1)) : j); - printk(BIOS_SPEW, "node 0x%x core 0x%x apicid = 0x%x\n", - i, j, apic_id); - - struct device *cpu = add_cpu_device(cpu_bus, apic_id, enable_node); - if (cpu) - amd_cpu_topology(cpu, i, j); - } //j - } -} - -static void cpu_bus_init(struct device *dev) -{ - initialize_cpus(dev->link_list); -} - -static struct device_operations cpu_bus_ops = { - .read_resources = noop_read_resources, - .set_resources = noop_set_resources, - .init = cpu_bus_init, - .scan_bus = cpu_bus_scan, -}; - -static void root_complex_enable_dev(struct device *dev) -{ - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - - /* Set the operations if it is a special bus type */ - if (dev->path.type == DEVICE_PATH_DOMAIN) { - dev->ops = &pci_domain_ops; - } else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) { - dev->ops = &cpu_bus_ops; - } -} - -struct chip_operations northbridge_amd_pi_00660F01_root_complex_ops = { - CHIP_NAME("AMD FAM16 Root Complex") - .enable_dev = root_complex_enable_dev, -}; - -/********************************************************************* - * Change the vendor / device IDs to match the generic VBIOS header. * - *********************************************************************/ -u32 map_oprom_vendev(u32 vendev) -{ - u32 new_vendev; - new_vendev = - ((0x10029870 <= vendev) && (vendev <= 0x1002987F)) ? 0x10029870 : vendev; - - if (vendev != new_vendev) - printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n", vendev, new_vendev); - - return new_vendev; -} diff --git a/src/northbridge/amd/pi/Makefile.inc b/src/northbridge/amd/pi/Makefile.inc index 7c66b56168..0cdf326c83 100644 --- a/src/northbridge/amd/pi/Makefile.inc +++ b/src/northbridge/amd/pi/Makefile.inc @@ -4,6 +4,5 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y) subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01 -subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01 endif From b37f2e9902ec94a0e9e647ce7774f9db57656121 Mon Sep 17 00:00:00 2001 From: Tony Huang Date: Tue, 17 Nov 2020 19:09:47 +0800 Subject: [PATCH 081/107] mb/google/puff/var/dooly: update USB2 type-c strength Based on USB DB report. BRANCH=puff BUG=b:163561808 TEST=build and measure by EE team. Change-Id: I379987b6d6d2a7aef33d4c42e589dc52d40205a3 Signed-off-by: Tony Huang Reviewed-on: https://review.coreboot.org/c/coreboot/+/47687 Tested-by: build bot (Jenkins) Reviewed-by: Sam McNally --- .../hatch/variants/dooly/overridetree.cb | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/hatch/variants/dooly/overridetree.cb b/src/mainboard/google/hatch/variants/dooly/overridetree.cb index 6e23448747..efa7d719a4 100644 --- a/src/mainboard/google/hatch/variants/dooly/overridetree.cb +++ b/src/mainboard/google/hatch/variants/dooly/overridetree.cb @@ -27,7 +27,14 @@ chip soc/intel/cannonlake .pre_emp_bias = USB2_BIAS_11P25MV, .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 0 - register "usb2_ports[1]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 0 + register "usb2_ports[1]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 0 register "usb2_ports[2]" = "{ .enable = 1, .ocpin = OC3, @@ -37,7 +44,14 @@ chip soc/intel/cannonlake .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, }" # Type-A Port 1 register "usb2_ports[3]" = "USB2_PORT_EMPTY" - register "usb2_ports[4]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C Port 1 + register "usb2_ports[4]" = "{ + .enable = 1, + .ocpin = OC_SKIP, + .tx_bias = USB2_BIAS_0MV, + .tx_emp_enable = USB2_PRE_EMP_ON, + .pre_emp_bias = USB2_BIAS_28P15MV, + .pre_emp_bit = USB2_HALF_BIT_PRE_EMP, + }" # Type-C Port 1 register "usb2_ports[5]" = "USB2_PORT_LONG(OC_SKIP)" # USB cam register "usb2_ports[6]" = "USB2_PORT_EMPTY" register "usb2_ports[7]" = "USB2_PORT_EMPTY" From 82a30a134c50bd44f050e0a37653111444a8e6e4 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 7 Nov 2020 15:17:45 -0700 Subject: [PATCH 082/107] util/crossgcc: Retry package downloads on failure For whatever reason, I've had buildgcc fail to download packages a number of times. Adding 2 additional retries before failing helps with that problem. Signed-off-by: Martin Roth Change-Id: I060eaa5a0da955436169e2199c1c62044dcfd5ea Reviewed-on: https://review.coreboot.org/c/coreboot/+/47338 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/crossgcc/buildgcc | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 958a5415ca..bba8ac71a3 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -1057,7 +1057,7 @@ if searchtool wget "GNU" nofail > /dev/null; then download_showing_percentage() { url=$1 printf "... ${red} 0%%" - wget "$url" 2>&1 | while read -r line; do + wget --tries=3 "$url" 2>&1 | while read -r line; do echo "$line" | grep -o "[0-9]\+%" | awk '{printf("\b\b\b\b%4s", $1)}' done printf "${NC}... " @@ -1066,7 +1066,7 @@ elif searchtool curl "^curl " > /dev/null; then download_showing_percentage() { url=$1 echo - curl -#OL "$url" + curl --progress-bar --location --retry 3 "$url" } fi From 44cfde02d5d694a6f0eced12333d2350acb498d1 Mon Sep 17 00:00:00 2001 From: Martin Roth Date: Sat, 7 Nov 2020 15:52:56 -0700 Subject: [PATCH 083/107] util/docker: Minor Makefile updates - Update url for docker install instructions. - Update docker-cleanall target to require verification. - Update docker-jenkins-attach target to check for docker and use docker variable. - Update spaces to tabs in the docs targets. Signed-off-by: Martin Roth Change-Id: Ic1e1a545024fe1fdc37d7d8c7e6f54f124d1697b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47342 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/docker/Makefile | 29 +++++++++++++++++------------ 1 file changed, 17 insertions(+), 12 deletions(-) diff --git a/util/docker/Makefile b/util/docker/Makefile index eaa26e1760..8b1d0efb8d 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -31,8 +31,8 @@ GID ?= $(shell id -g) test-docker: $(if $(DOCKER),,\ - $(warning Docker command not found. Please install docker) \ - $(warning https://docs.docker.com/engine/installation ) \ + $(warning Error: Docker command not found. Please install docker) \ + $(warning Instructions: https://docs.docker.com/engine/install/ ) \ $(error halting)) test-docker-login: test-docker @@ -82,14 +82,19 @@ clean-coreboot-images: docker-killall docker-clean: clean-coreboot-containers @$(MAKE) clean-coreboot-images -docker-cleanall: +docker-cleanall: test-docker +ifeq($(Y),1) @if [ -n "$$($(DOCKER) ps -a | grep -v "CONTAINER")" ]; then \ - $(DOCKER) kill $$($(DOCKER) ps -a | grep -v "CONTAINER" | sed 's|\s.*$$||'); \ + $(DOCKER) kill $$($(DOCKER) ps | grep -v "CONTAINER" | sed 's|\s.*$$||') ; \ $(DOCKER) rm $$($(DOCKER) ps -a | grep -v "CONTAINER" | sed 's|\s.*$$||'); \ fi @if [ -n "$$($(DOCKER) images | grep -v "REPOSITORY")" ]; then \ $(DOCKER) rmi $$($(DOCKER) images | grep -v "REPOSITORY" | tr -s ' ' | cut -f3 -d ' '); \ fi +else + echo "This will remove *ALL* docker containers from your machine." + echo "If this is what you want, run 'make docker-cleanall Y=1'" +endif $(DOCKER_CCACHE): @mkdir -p $@ @@ -153,8 +158,8 @@ docker-shell: test-docker /bin/bash -l docker-jenkins-attach: USER=root -docker-jenkins-attach: - docker exec --user $(USER) \ +docker-jenkins-attach: test-docker + $(DOCKER) exec --user $(USER) \ -e COLUMNS=$(shell tput cols) -e LINES=$(shell tput lines) -e TERM=$(TERM) \ -it "$$(docker ps | grep coreboot-jenkins-node | cut -f1 -d' ')" \ /bin/bash -l @@ -162,16 +167,16 @@ docker-jenkins-attach: docker-build-docs: test-docker docker-build-docs: $(DOCKER) run -it --rm \ - --user $(UID):$(GID) \ - -v "$(top)/:/data-in/:ro" \ - -v "$(top)/Documentation/_build/:/data-out/" \ - doc.coreboot.org + --user $(UID):$(GID) \ + -v "$(top)/:/data-in/:ro" \ + -v "$(top)/Documentation/_build/:/data-out/" \ + doc.coreboot.org docker-livehtml-docs: test-docker docker-livehtml-docs: $(DOCKER) run -it --rm \ - --net=host -v "$(top)/:/data-in/:ro" \ - doc.coreboot.org livehtml + --net=host -v "$(top)/:/data-in/:ro" \ + doc.coreboot.org livehtml help: @echo "Commands for working with docker images:" From b01ac7e26453677318776885d4ab870f59553ae6 Mon Sep 17 00:00:00 2001 From: Patrick Rudolph Date: Sun, 26 Jul 2020 14:23:37 +0200 Subject: [PATCH 084/107] cpu/intel/common: Fill cpu voltage in SMBIOS tables Introduce a weak function to let the platform code provide the processor voltage in 100mV units. Implement the function on Intel platforms using the MSR_PERF_STATUS msr. On other platforms the processor voltage still reads as unknown. Tested on Intel CFL. The CPU voltage is correctly advertised. Change-Id: I31a7efcbeede50d986a1c096a4a59a316e09f825 Signed-off-by: Patrick Rudolph Reviewed-on: https://review.coreboot.org/c/coreboot/+/43904 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Jonathan Zhang Reviewed-by: Nico Huber --- src/arch/x86/smbios.c | 10 ++++++++++ src/cpu/intel/common/Kconfig | 3 +++ src/cpu/intel/common/Makefile.inc | 1 + src/cpu/intel/common/voltage.c | 12 ++++++++++++ src/cpu/intel/haswell/Kconfig | 1 + src/include/smbios.h | 1 + 6 files changed, 28 insertions(+) create mode 100644 src/cpu/intel/common/voltage.c diff --git a/src/arch/x86/smbios.c b/src/arch/x86/smbios.c index dc676cf141..da77284d37 100644 --- a/src/arch/x86/smbios.c +++ b/src/arch/x86/smbios.c @@ -493,6 +493,12 @@ unsigned int __weak smbios_cache_conf_operation_mode(u8 level) return SMBIOS_CACHE_OP_MODE_UNKNOWN; /* Unknown */ } +/* Returns the processor voltage in 100mV units */ +unsigned int __weak smbios_cpu_get_voltage(void) +{ + return 0; /* Unknown */ +} + static size_t get_number_of_caches(struct cpuid_result res_deterministic_cache) { size_t max_logical_cpus_sharing_cache = 0; @@ -595,6 +601,7 @@ static int smbios_write_type3(unsigned long *current, int handle) static int smbios_write_type4(unsigned long *current, int handle) { + unsigned int cpu_voltage; struct cpuid_result res; struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); @@ -686,6 +693,9 @@ static int smbios_write_type4(unsigned long *current, int handle) } } t->processor_characteristics = characteristics | smbios_processor_characteristics(); + cpu_voltage = smbios_cpu_get_voltage(); + if (cpu_voltage > 0) + t->voltage = 0x80 | cpu_voltage; *current += len; return len; diff --git a/src/cpu/intel/common/Kconfig b/src/cpu/intel/common/Kconfig index 01f2721b59..7f9033cf65 100644 --- a/src/cpu/intel/common/Kconfig +++ b/src/cpu/intel/common/Kconfig @@ -32,6 +32,9 @@ config CPU_INTEL_COMMON_TIMEBASE endif +config CPU_INTEL_COMMON_VOLTAGE + bool + config CPU_INTEL_COMMON_SMM bool default y if CPU_INTEL_COMMON diff --git a/src/cpu/intel/common/Makefile.inc b/src/cpu/intel/common/Makefile.inc index 8b81a121d3..530ecee009 100644 --- a/src/cpu/intel/common/Makefile.inc +++ b/src/cpu/intel/common/Makefile.inc @@ -1,5 +1,6 @@ ramstage-$(CONFIG_CPU_INTEL_COMMON) += common_init.c ramstage-$(CONFIG_CPU_INTEL_COMMON) += hyperthreading.c +ramstage-$(CONFIG_CPU_INTEL_COMMON_VOLTAGE) += voltage.c ifeq ($(CONFIG_CPU_INTEL_COMMON_TIMEBASE),y) bootblock-y += fsb.c diff --git a/src/cpu/intel/common/voltage.c b/src/cpu/intel/common/voltage.c new file mode 100644 index 0000000000..38951a06db --- /dev/null +++ b/src/cpu/intel/common/voltage.c @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +/* This is not an architectural MSR. */ +#define MSR_PERF_STATUS 0x198 + +unsigned int smbios_cpu_get_voltage(void) +{ + return (rdmsr(MSR_PERF_STATUS).hi & 0xffff) * 10 / 8192; +} diff --git a/src/cpu/intel/haswell/Kconfig b/src/cpu/intel/haswell/Kconfig index fbfa71456b..0d3d132006 100644 --- a/src/cpu/intel/haswell/Kconfig +++ b/src/cpu/intel/haswell/Kconfig @@ -20,6 +20,7 @@ config CPU_SPECIFIC_OPTIONS select CPU_INTEL_COMMON select CPU_INTEL_COMMON_TIMEBASE select HAVE_ASAN_IN_ROMSTAGE + select CPU_INTEL_COMMON_VOLTAGE config SMM_TSEG_SIZE hex diff --git a/src/include/smbios.h b/src/include/smbios.h index 6a19655b31..4ddf4384dc 100644 --- a/src/include/smbios.h +++ b/src/include/smbios.h @@ -40,6 +40,7 @@ const char *smbios_system_sku(void); unsigned int smbios_cpu_get_max_speed_mhz(void); unsigned int smbios_cpu_get_current_speed_mhz(void); +unsigned int smbios_cpu_get_voltage(void); const char *smbios_mainboard_manufacturer(void); const char *smbios_mainboard_product_name(void); From be34afad6fe2660919f488402cfcf685fdd47300 Mon Sep 17 00:00:00 2001 From: Tim Chu Date: Fri, 13 Nov 2020 03:04:54 -0800 Subject: [PATCH 085/107] mb/ocp/deltalake: Override SMBIOS type 4 cpu voltage Override SMBIOS type 4 cpu voltage. For Delta Lake, 1.6V is expected. Tested=Execute "dmidecode -t 4" to check if cpu voltage is correct. Signed-off-by: Tim Chu Change-Id: I0ecbec8fb3dc79b8c3f3581d6193aade01bcd68e Reviewed-on: https://review.coreboot.org/c/coreboot/+/47562 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang --- src/mainboard/ocp/deltalake/ramstage.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/src/mainboard/ocp/deltalake/ramstage.c b/src/mainboard/ocp/deltalake/ramstage.c index 9d570900b1..52c55b89b0 100644 --- a/src/mainboard/ocp/deltalake/ramstage.c +++ b/src/mainboard/ocp/deltalake/ramstage.c @@ -59,6 +59,18 @@ const char *smbios_mainboard_location_in_chassis(void) return slot_id_str; } +/* + * Override SMBIOS type 4 cpu voltage. + * BIT7 will set to 1 after value return. If BIT7 is set to 1, the remaining seven + * bits of this field are set to contain the processor's current voltage times 10. + */ +unsigned int smbios_cpu_get_voltage(void) +{ + /* This will return 1.6V which is expected value for Delta Lake + 10h = (1.6 * 10) = 16 */ + return 0x10; +} + /* System Slot Socket, Stack, Type and Data bus width Information */ typedef struct { u8 stack; From b5353965e1b7eff860faaa3312728a935311a8c6 Mon Sep 17 00:00:00 2001 From: Sam Lewis Date: Mon, 3 Aug 2020 21:14:26 +1000 Subject: [PATCH 086/107] soc/ti/am335x: Enable MMU in bootblock Enables the MMU primarily to allow the unaligned word reads that the FMAP code requires. Without enabling this, the chip gets data access exceptions. Enabling the MMU also gives some advantages in allowing the icache and dcache to be enabled, so is probably worth doing regardless. Change-Id: Ic571570cc44b0696ea61cc76e3bce7167a3256cf Signed-off-by: Sam Lewis Reviewed-on: https://review.coreboot.org/c/coreboot/+/44382 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/soc/ti/am335x/bootblock.c | 22 +++++++++++++++++----- src/soc/ti/am335x/bootblock_media.c | 1 - src/soc/ti/am335x/memlayout.ld | 9 ++++----- 3 files changed, 21 insertions(+), 11 deletions(-) diff --git a/src/soc/ti/am335x/bootblock.c b/src/soc/ti/am335x/bootblock.c index 985e1a1a0b..11bc4593e1 100644 --- a/src/soc/ti/am335x/bootblock.c +++ b/src/soc/ti/am335x/bootblock.c @@ -4,13 +4,25 @@ #include #include +#include + +#define SRAM_START ((uintptr_t)_sram / MiB) +#define SRAM_END (DIV_ROUND_UP((uintptr_t)_esram, MiB)) + +#define DRAM_START ((uintptr_t)_dram / MiB) +#define DRAM_SIZE (CONFIG_DRAM_SIZE_MB) void bootblock_soc_init(void) { - uint32_t sctlr; + mmu_init(); - /* enable dcache */ - sctlr = read_sctlr(); - sctlr |= SCTLR_C; - write_sctlr(sctlr); + /* Map everything strongly ordered by default */ + mmu_config_range(0, 4096, DCACHE_OFF); + + mmu_config_range(SRAM_START, SRAM_END - SRAM_START, + DCACHE_WRITEBACK); + + mmu_config_range(DRAM_START, DRAM_SIZE, DCACHE_WRITEBACK); + + dcache_mmu_enable(); } diff --git a/src/soc/ti/am335x/bootblock_media.c b/src/soc/ti/am335x/bootblock_media.c index 1c65c38684..b7e49a6c47 100644 --- a/src/soc/ti/am335x/bootblock_media.c +++ b/src/soc/ti/am335x/bootblock_media.c @@ -3,7 +3,6 @@ #include #include -/* FIXME: No idea how big the internal SRAM actually is. */ static const struct mem_region_device boot_dev = MEM_REGION_DEV_RO_INIT(_sram, CONFIG_ROM_SIZE); diff --git a/src/soc/ti/am335x/memlayout.ld b/src/soc/ti/am335x/memlayout.ld index 991e4012a4..720da26d6f 100644 --- a/src/soc/ti/am335x/memlayout.ld +++ b/src/soc/ti/am335x/memlayout.ld @@ -8,17 +8,16 @@ SECTIONS { SRAM_START(0x402f0400) BOOTBLOCK(0x402f0400, 20K) - ROMSTAGE(0x402f5400, 88K) - FMAP_CACHE(0x4030b400, 2K) + FMAP_CACHE(0x402f0400+20K, 2K) + TTB(0x402F8000, 16K) + ROMSTAGE(0x402F8000+16K, 40K) + STACK(0x4030be00, 4K) SRAM_END(0x40310000) DRAM_START(0x80000000) RAMSTAGE(0x80200000, 192K) - /* TODO: Implement MMU support and move TTB to a better location. */ - TTB(0x81000000, 16K) - #ifdef OMAP_HEADER .header : { *(.header); From fde084bc490daf99da85292ef87d6dcf3446c212 Mon Sep 17 00:00:00 2001 From: Sam Lewis Date: Tue, 4 Aug 2020 19:47:50 +1000 Subject: [PATCH 087/107] soc/ti/am335x: Fix timer implementation Implements the monotonic timer using the am335x dmtimer peripheral. Change-Id: I4736b6d3b6e26370be9e8f369fc02285ad519223 Signed-off-by: Sam Lewis Reviewed-on: https://review.coreboot.org/c/coreboot/+/44383 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/ti/am335x/Makefile.inc | 9 +++---- src/soc/ti/am335x/dmtimer.c | 12 --------- src/soc/ti/am335x/dmtimer.h | 30 +++++++++++++++++++--- src/soc/ti/am335x/monotonic_timer.c | 40 ----------------------------- src/soc/ti/am335x/timer.c | 31 ++++++++++++++++++++++ 5 files changed, 61 insertions(+), 61 deletions(-) delete mode 100644 src/soc/ti/am335x/dmtimer.c delete mode 100644 src/soc/ti/am335x/monotonic_timer.c create mode 100644 src/soc/ti/am335x/timer.c diff --git a/src/soc/ti/am335x/Makefile.inc b/src/soc/ti/am335x/Makefile.inc index e744c72526..60e00fbbcc 100644 --- a/src/soc/ti/am335x/Makefile.inc +++ b/src/soc/ti/am335x/Makefile.inc @@ -1,18 +1,15 @@ ifeq ($(CONFIG_SOC_TI_AM335X),y) bootblock-y += bootblock.c bootblock-y += bootblock_media.c -bootblock-y += dmtimer.c +bootblock-y += timer.c bootblock-y += gpio.c bootblock-y += pinmux.c -bootblock-y += monotonic_timer.c romstage-y += nand.c romstage-y += cbmem.c -romstage-y += dmtimer.c -romstage-y += monotonic_timer.c +romstage-y += timer.c -ramstage-y += dmtimer.c -ramstage-y += monotonic_timer.c +ramstage-y += timer.c ramstage-y += nand.c ramstage-y += soc.c diff --git a/src/soc/ti/am335x/dmtimer.c b/src/soc/ti/am335x/dmtimer.c deleted file mode 100644 index b3aa7a18ba..0000000000 --- a/src/soc/ti/am335x/dmtimer.c +++ /dev/null @@ -1,12 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include "dmtimer.h" - -void dmtimer_start(int num) -{ -} - -uint64_t dmtimer_raw_value(int num) -{ - return 0; -} diff --git a/src/soc/ti/am335x/dmtimer.h b/src/soc/ti/am335x/dmtimer.h index ad8515fbba..56f3d0f011 100644 --- a/src/soc/ti/am335x/dmtimer.h +++ b/src/soc/ti/am335x/dmtimer.h @@ -5,9 +5,33 @@ #include -#define OSC_HZ 24000000 +#define M_OSC_MHZ (24) -void dmtimer_start(int num); -uint64_t dmtimer_raw_value(int num); +struct am335x_dmtimer { + uint32_t tidr; + uint8_t res1[12]; + uint32_t tiocp_cfg; + uint8_t res2[12]; + uint32_t irq_eoi; + uint32_t irqstatus_raw; + uint32_t irqstatus; + uint32_t irqenable_set; + uint32_t irqenable_clr; + uint32_t irqwakeen; + uint32_t tclr; + uint32_t tcrr; + uint32_t tldr; + uint32_t ttgr; + uint32_t twps; + uint32_t tmar; + uint32_t tcar1; + uint32_t tsicr; + uint32_t tcar2; +}; + +#define TCLR_ST (0x01 << 0) +#define TCLR_AR (0x01 << 1) + +#define DMTIMER_2 (0x48040000) #endif diff --git a/src/soc/ti/am335x/monotonic_timer.c b/src/soc/ti/am335x/monotonic_timer.c deleted file mode 100644 index b57258b6c8..0000000000 --- a/src/soc/ti/am335x/monotonic_timer.c +++ /dev/null @@ -1,40 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include -#include - -#include "dmtimer.h" - -static struct monotonic_counter { - int initialized; - struct mono_time time; - uint64_t last_value; -} mono_counter; - -static const uint32_t clocks_per_usec = OSC_HZ/1000000; - -void timer_monotonic_get(struct mono_time *mt) -{ - uint64_t current_tick; - uint64_t usecs_elapsed; - - if (!mono_counter.initialized) { - init_timer(); - mono_counter.last_value = dmtimer_raw_value(0); - mono_counter.initialized = 1; - } - - current_tick = dmtimer_raw_value(0); - usecs_elapsed = (current_tick - mono_counter.last_value) / - clocks_per_usec; - - /* Update current time and tick values only if a full tick occurred. */ - if (usecs_elapsed) { - mono_time_add_usecs(&mono_counter.time, usecs_elapsed); - mono_counter.last_value = current_tick; - } - - /* Save result. */ - *mt = mono_counter.time; -} diff --git a/src/soc/ti/am335x/timer.c b/src/soc/ti/am335x/timer.c new file mode 100644 index 0000000000..4ed98a3541 --- /dev/null +++ b/src/soc/ti/am335x/timer.c @@ -0,0 +1,31 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +#include "dmtimer.h" +#include "clock.h" + +struct am335x_dmtimer *dmtimer_2 = (struct am335x_dmtimer *)DMTIMER_2; + +#define CLKSEL_M_OSC (0x01 << 0) + +static uint32_t timer_raw_value(void) +{ + return read32(&dmtimer_2->tcrr); +} + +void timer_monotonic_get(struct mono_time *mt) +{ + mono_time_set_usecs(mt, timer_raw_value() / M_OSC_MHZ); +} + +void init_timer(void) +{ + write32(&am335x_cm_dpll->clksel_timer2_clk, CLKSEL_M_OSC); + + // Start the dmtimer in autoreload mode without any prescalers + // With M_OSC at 24MHz, this gives a few minutes before the timer overflows + write32(&dmtimer_2->tclr, TCLR_ST | TCLR_AR); +} From f9961fff31b3d91616e3526a4430733270fc109b Mon Sep 17 00:00:00 2001 From: Jakub Czapiga Date: Mon, 16 Nov 2020 15:25:34 +0100 Subject: [PATCH 088/107] tests: Add lib/cbmem_console-test test case Add test case executed twice, once for ROMSTAGE and once RAMSTAGE. Each test is named and visible in cmocka output with stage in its name. Signed-off-by: Jakub Czapiga Change-Id: I464eee61f538188427bec730d2e004c7b76cca67 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47642 Tested-by: build bot (Jenkins) Reviewed-by: Paul Fagerburg --- tests/lib/Makefile.inc | 9 +++ tests/lib/cbmem_console-test.c | 136 +++++++++++++++++++++++++++++++++ 2 files changed, 145 insertions(+) create mode 100644 tests/lib/cbmem_console-test.c diff --git a/tests/lib/Makefile.inc b/tests/lib/Makefile.inc index 219f7e7634..c49828962d 100644 --- a/tests/lib/Makefile.inc +++ b/tests/lib/Makefile.inc @@ -6,6 +6,8 @@ tests-y += hexstrtobin-test tests-y += imd-test tests-y += timestamp-test tests-y += edid-test +tests-y += cbmem_console-romstage-test +tests-y += cbmem_console-ramstage-test string-test-srcs += tests/lib/string-test.c string-test-srcs += src/lib/string.c @@ -30,3 +32,10 @@ edid-test-srcs += tests/lib/edid-test.c edid-test-srcs += src/lib/edid.c edid-test-srcs += tests/stubs/console.c +cbmem_console-romstage-test-stage := romstage +cbmem_console-romstage-test-srcs += tests/lib/cbmem_console-test.c +cbmem_console-romstage-test-srcs += tests/stubs/console.c + +cbmem_console-ramstage-test-stage := ramstage +cbmem_console-ramstage-test-srcs += tests/lib/cbmem_console-test.c +cbmem_console-ramstage-test-srcs += tests/stubs/console.c \ No newline at end of file diff --git a/tests/lib/cbmem_console-test.c b/tests/lib/cbmem_console-test.c new file mode 100644 index 0000000000..604ca7a77b --- /dev/null +++ b/tests/lib/cbmem_console-test.c @@ -0,0 +1,136 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include "../lib/cbmem_console.c" + +#include +#include +#include +#include + + +#if ENV_ROMSTAGE_OR_BEFORE +/* Weak references have to be here, so TEST_REGION macro will work properly */ +__weak extern u8 _preram_cbmem_console[]; +__weak extern u8 _epreram_cbmem_console[]; + +#define PRERAM_CBMEM_CONSOLE_SIZE (1 * KiB) +TEST_REGION(preram_cbmem_console, PRERAM_CBMEM_CONSOLE_SIZE); +#endif + +/* Disable init hooks. This test does not need them. */ +void cbmem_run_init_hooks(int is_recovery) +{ + (void)is_recovery; +} + +int setup_cbmemc(void **state) +{ + cbmemc_init(); + return 0; +} + +int teardown_cbmemc(void **state) +{ + current_console->size = 0; + return 0; +} + +void test_cbmemc_init(void **state) +{ + cbmemc_init(); + + /* Check if console structure was created. */ + assert_non_null(current_console); +} + +void test_cbmemc_tx_byte(void **state) +{ + int i; + u32 cursor; + const unsigned char data[] = "Random testing string\n" + "`1234567890-=~!@#$%^&*()_+\n" + "abcdefghijklmnopqrstuvwxyz\n" + "ABCDEFGHIJKLMNOPQRSTUVWXYZ\n"; + + for (i = 0; i < ARRAY_SIZE(data); ++i) + cbmemc_tx_byte(data[i]); + + cursor = current_console->cursor & CURSOR_MASK; + + assert_int_equal(ARRAY_SIZE(data), cursor); + + /* Check if all characters were added correctly. */ + assert_memory_equal(data, current_console->body, ARRAY_SIZE(data)); +} + +void test_cbmemc_tx_byte_overflow(void **state) +{ + int i; + u32 cursor; + u32 flags; + const uint32_t console_size = current_console->size; + const unsigned char data[] = "Another random string\n" + "abcdefghijklmnopqrstuvwxyz\n" + "ABCDEFGHIJKLMNOPQRSTUVWXYZ\n" + "`1234567890-=~!@#$%^&*()_+\n"; + const int data_size = ARRAY_SIZE(data) - 1; + const int data_stream_length = console_size + data_size; + const int overflow_bytes = data_stream_length % console_size; + unsigned char *check_buffer = + (unsigned char *)malloc(sizeof(unsigned char) * console_size); + + /* Fill console buffer */ + for (i = 0; i < console_size; ++i) + cbmemc_tx_byte(data[i % data_size]); + + /* Store buffer for checking */ + memcpy(check_buffer, current_console->body, console_size); + + assert_memory_equal(current_console->body, data, overflow_bytes); + + /* Add more data to console buffer to override older bytes */ + for (; i < data_stream_length; ++i) + cbmemc_tx_byte(data[i % data_size]); + + cursor = current_console->cursor & CURSOR_MASK; + flags = current_console->cursor & ~CURSOR_MASK; + + /* Check if there was a overflow in buffer */ + assert_int_equal(OVERFLOW, flags & OVERFLOW); + + /* Check if cursor got back to the beginning of a buffer */ + assert_int_equal(data_size, cursor); + + /* Check if overflow buffer was overwritten */ + assert_memory_not_equal(current_console->body, + data, + overflow_bytes); + + /* Check if rest of the buffer contents, that should not be overridden, + * is the same. + */ + assert_memory_equal(¤t_console->body[overflow_bytes], + check_buffer + overflow_bytes, + console_size - overflow_bytes); + + free(check_buffer); +} + +int main(void) +{ +#if ENV_ROMSTAGE_OR_BEFORE + const char *test_name = "cbmem_console-test-romstage"; +#else + const char *test_name = "cbmem_console-test-ramstage"; +#endif + + const struct CMUnitTest tests[] = { + cmocka_unit_test_teardown(test_cbmemc_init, teardown_cbmemc), + cmocka_unit_test_setup_teardown(test_cbmemc_tx_byte, + setup_cbmemc, teardown_cbmemc), + cmocka_unit_test_setup_teardown(test_cbmemc_tx_byte_overflow, + setup_cbmemc, teardown_cbmemc), + }; + + return cmocka_run_group_tests_name(test_name, tests, NULL, NULL); +} From c3c3e453ff4e6d73b52d88ab08a708610997f334 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Fri, 13 Nov 2020 21:35:19 -0800 Subject: [PATCH 089/107] soc/intel/tigerlake: Fix overlapping memory address used for early GSPI2 and UART bars BAR address used during early initilization of GPSI 2 is overlapping with UART bar. //For GSPI2 this is the address calculated GSPI_BUS_BASE(0xFE030000,2)=0xFE032000 GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB) //overlaps with CONSOLE_UART_BASE_ADDRESS -> 0xfe032000 Change-Id: Id9f2140a6dd21c2cb8d75823cc83cced0c660179 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47643 Tested-by: build bot (Jenkins) Reviewed-by: Anil Kumar K Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/soc/intel/tigerlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/tigerlake/Kconfig b/src/soc/intel/tigerlake/Kconfig index e962e4cccc..b97b92e46d 100644 --- a/src/soc/intel/tigerlake/Kconfig +++ b/src/soc/intel/tigerlake/Kconfig @@ -168,7 +168,7 @@ config SOC_INTEL_UART_DEV_MAX config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate From 2a70419e7c9523cc9c40303bd3355e24b01ea603 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Mon, 16 Nov 2020 11:23:48 -0800 Subject: [PATCH 090/107] soc/intel/alderlake: Fix overlapping memory address used for early GSPI2 and UART bars BAR address used during early initilization of GPSI 2 is overlapping with UART bar. //For GSPI2 this is the address calculated GSPI_BUS_BASE(0xFE030000,2)=0xFE032000 GSPI_BUS_BASE(bar, bus) ((bar) + (bus) * 4 * KiB) //overlaps with CONSOLE_UART_BASE_ADDRESS -> 0xfe032000 TEST=none Signed-off-by: Bora Guvendik Change-Id: I3249a91df8a2e319aff6303ef9400e74163afe93 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47644 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/soc/intel/alderlake/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index b10d88c5c1..0db8e1ceb2 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -159,7 +159,7 @@ config SOC_INTEL_UART_DEV_MAX config CONSOLE_UART_BASE_ADDRESS hex - default 0xfe032000 + default 0xfe03e000 depends on INTEL_LPSS_UART_FOR_CONSOLE # Clock divider parameters for 115200 baud rate From 8079a6a558526730d994aa56bf23139fbad2141c Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Tue, 1 Sep 2020 20:37:49 -0700 Subject: [PATCH 091/107] libpayload/usb: Fix printf format string mismatches in debug messages This fixes format string mismatch errors in the USB subsystem found by the compiler's format string checker. BUG=b:167517417 TEST=enabled all USB controllers on volteer and fixed resulting compiler errors when USB_DEBUG is enabled. Change-Id: I4dc70baefb3cd82fcc915cc2e7f68719cf6870cc Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/c/coreboot/+/45024 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- payloads/libpayload/drivers/usb/ehci.c | 17 ++++++++++------- payloads/libpayload/drivers/usb/ohci.c | 19 ++++++++++--------- payloads/libpayload/drivers/usb/uhci.c | 9 +++++---- payloads/libpayload/drivers/usb/usb.c | 3 ++- payloads/libpayload/drivers/usb/xhci.c | 12 ++++++------ 5 files changed, 33 insertions(+), 27 deletions(-) diff --git a/payloads/libpayload/drivers/usb/ehci.c b/payloads/libpayload/drivers/usb/ehci.c index 97caf202d9..58fc64eead 100644 --- a/payloads/libpayload/drivers/usb/ehci.c +++ b/payloads/libpayload/drivers/usb/ehci.c @@ -28,6 +28,7 @@ //#define USB_DEBUG +#include #include #include #include @@ -46,15 +47,15 @@ static void dump_td(u32 addr) usb_debug("|..[OUT]............................................|\n"); else usb_debug("|..[]...............................................|\n"); - usb_debug("|:|============ EHCI TD at [0x%08lx] ==========|:|\n", addr); - usb_debug("|:| ERRORS = [%ld] | TOKEN = [0x%08lx] | |:|\n", + usb_debug("|:|============ EHCI TD at [0x%08"PRIx32"] ==========|:|\n", addr); + usb_debug("|:| ERRORS = [%"PRId32"] | TOKEN = [0x%08"PRIx32"] | |:|\n", 3 - ((td->token & QTD_CERR_MASK) >> QTD_CERR_SHIFT), td->token); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Next qTD [0x%08lx] |:|\n", td->next_qtd); + usb_debug("|:| Next qTD [0x%08"PRIx32"] |:|\n", td->next_qtd); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Alt. Next qTD [0x%08lx] |:|\n", td->alt_next_qtd); + usb_debug("|:| Alt. Next qTD [0x%08"PRIx32"] |:|\n", td->alt_next_qtd); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| | Bytes to Transfer |[%05ld] |:|\n", (td->token & QTD_TOTAL_LEN_MASK) >> 16); + usb_debug("|:| | Bytes to Transfer |[%05"PRId32"] |:|\n", (td->token & QTD_TOTAL_LEN_MASK) >> 16); usb_debug("|:| | PID CODE: | [%ld] |:|\n", (td->token & (3UL << 8)) >> 8); usb_debug("|:| | Interrupt On Complete (IOC) | [%ld] |:|\n", (td->token & (1UL << 15)) >> 15); usb_debug("|:| | Status Active | [%ld] |:|\n", (td->token & (1UL << 7)) >> 7); @@ -277,9 +278,11 @@ static int wait_for_tds(qtd_t *head) if (cur->next_qtd & 1) { break; } - if (0) dump_td(virt_to_phys(cur)); + if (0) + dump_td(virt_to_phys(cur)); /* helps debugging the TD chain */ - if (0) usb_debug("\nmoving from %x to %x\n", cur, phys_to_virt(cur->next_qtd)); + if (0) + usb_debug("\nmoving from %p to %p\n", cur, phys_to_virt(cur->next_qtd)); cur = phys_to_virt(cur->next_qtd); } return result; diff --git a/payloads/libpayload/drivers/usb/ohci.c b/payloads/libpayload/drivers/usb/ohci.c index ec14144711..f35d1ff0e8 100644 --- a/payloads/libpayload/drivers/usb/ohci.c +++ b/payloads/libpayload/drivers/usb/ohci.c @@ -29,6 +29,7 @@ //#define USB_DEBUG #include +#include #include #include "ohci_private.h" #include "ohci.h" @@ -59,7 +60,7 @@ dump_td (td_t *cur) else usb_debug("|..[]...............................................|\n"); usb_debug("|:|============ OHCI TD at [0x%08lx] ==========|:|\n", virt_to_phys(cur)); - usb_debug("|:| ERRORS = [%ld] | CONFIG = [0x%08lx] | |:|\n", + usb_debug("|:| ERRORS = [%ld] | CONFIG = [0x%08"PRIx32"] | |:|\n", 3 - ((cur->config & (3UL << 26)) >> 26), cur->config); usb_debug("|:+-----------------------------------------------+:|\n"); usb_debug("|:| C | Condition Code | [%02ld] |:|\n", (cur->config & (0xFUL << 28)) >> 28); @@ -69,11 +70,11 @@ dump_td (td_t *cur) usb_debug("|:| I | Data Toggle | [%ld] |:|\n", (cur->config & (3UL << 24)) >> 24); usb_debug("|:| G | Error Count | [%ld] |:|\n", (cur->config & (3UL << 26)) >> 26); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Current Buffer Pointer [0x%08lx] |:|\n", cur->current_buffer_pointer); + usb_debug("|:| Current Buffer Pointer [0x%08"PRIx32"] |:|\n", cur->current_buffer_pointer); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Next TD [0x%08lx] |:|\n", cur->next_td); + usb_debug("|:| Next TD [0x%08"PRIx32"] |:|\n", cur->next_td); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Current Buffer End [0x%08lx] |:|\n", cur->buffer_end); + usb_debug("|:| Current Buffer End [0x%08"PRIx32"] |:|\n", cur->buffer_end); usb_debug("|:|-----------------------------------------------|:|\n"); usb_debug("|...................................................|\n"); usb_debug("+---------------------------------------------------+\n"); @@ -88,9 +89,9 @@ dump_ed (ed_t *cur) usb_debug("+---------------------------------------------------+\n"); usb_debug("| Next Endpoint Descriptor [0x%08lx] |\n", cur->next_ed & ~0xFUL); usb_debug("+---------------------------------------------------+\n"); - usb_debug("| | @ 0x%08lx : |\n", cur->config); + usb_debug("| | @ 0x%08"PRIx32" : |\n", cur->config); usb_debug("| C | Maximum Packet Length | [%04ld] |\n", ((cur->config & (0x3fffUL << 16)) >> 16)); - usb_debug("| O | Function Address | [%04ld] |\n", cur->config & 0x7F); + usb_debug("| O | Function Address | [%04"PRIx32"] |\n", cur->config & 0x7F); usb_debug("| N | Endpoint Number | [%02ld] |\n", (cur->config & (0xFUL << 7)) >> 7); usb_debug("| F | Endpoint Direction | [%ld] |\n", ((cur->config & (3UL << 11)) >> 11)); usb_debug("| I | Endpoint Speed | [%ld] |\n", ((cur->config & (1UL << 13)) >> 13)); @@ -468,7 +469,7 @@ ohci_control (usbdev_t *dev, direction_t dir, int drlen, void *setup, int dalen, head->tail_pointer = virt_to_phys(final_td); head->head_pointer = virt_to_phys(first_td); - usb_debug("ohci_control(): doing transfer with %x. first_td at %x\n", + usb_debug("%s(): doing transfer with %x. first_td at %"PRIxPTR"\n", __func__, head->config & ED_FUNC_MASK, virt_to_phys(first_td)); #ifdef USB_DEBUG dump_ed(head); @@ -506,7 +507,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize) td_t *cur, *next; int remaining = dalen; u8 *data = src; - usb_debug("bulk: %x bytes from %x, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize); + usb_debug("bulk: %x bytes from %p, finalize: %x, maxpacketsize: %x\n", dalen, src, finalize, ep->maxpacketsize); if (!dma_coherent(src)) { data = OHCI_INST(ep->dev->controller)->dma_buffer; @@ -596,7 +597,7 @@ ohci_bulk (endpoint_t *ep, int dalen, u8 *src, int finalize) head->tail_pointer = virt_to_phys(cur); head->head_pointer = virt_to_phys(first_td) | (ep->toggle?ED_TOGGLE:0); - usb_debug("doing bulk transfer with %x(%x). first_td at %x, last %x\n", + usb_debug("doing bulk transfer with %x(%x). first_td at %"PRIxPTR", last %"PRIxPTR"\n", head->config & ED_FUNC_MASK, (head->config & ED_EP_MASK) >> ED_EP_SHIFT, virt_to_phys(first_td), virt_to_phys(cur)); diff --git a/payloads/libpayload/drivers/usb/uhci.c b/payloads/libpayload/drivers/usb/uhci.c index c6a178703c..b87ec26965 100644 --- a/payloads/libpayload/drivers/usb/uhci.c +++ b/payloads/libpayload/drivers/usb/uhci.c @@ -29,6 +29,7 @@ //#define USB_DEBUG #include +#include #include #include "uhci.h" #include "uhci_private.h" @@ -79,14 +80,14 @@ static void td_dump(td_t *td) (td->ptr & (1UL << 2)) >> 2, (td->ptr & (1UL << 1)) >> 1, td->ptr & 1UL); usb_debug("|:+-----------------------------------------------+:|\n"); usb_debug("|:| T | Maximum Length | [%04lx] |:|\n", (td->token & (0x7FFUL << 21)) >> 21); - usb_debug("|:| O | PID CODE | [%04lx] |:|\n", td->token & 0xFF); - usb_debug("|:| K | Endpoint | [%04lx] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT); + usb_debug("|:| O | PID CODE | [%04"PRIx32"] |:|\n", td->token & 0xFF); + usb_debug("|:| K | Endpoint | [%04"PRIx32"] |:|\n", (td->token & TD_EP_MASK) >> TD_EP_SHIFT); usb_debug("|:| E | Device Address | [%04lx] |:|\n", (td->token & (0x7FUL << 8)) >> 8); usb_debug("|:| N | Data Toggle | [%lx] |:|\n", (td->token & (1UL << 19)) >> 19); usb_debug("|:+-----------------------------------------------+:|\n"); usb_debug("|:| C | Short Packet Detector | [%lx] |:|\n", (td->ctrlsts & (1UL << 29)) >> 29); usb_debug("|:| O | Error Counter | [%lx] |:|\n", - (td->ctrlsts & (3UL << TD_COUNTER_SHIFT)) >> TD_COUNTER_SHIFT); + (td->ctrlsts & (3UL << TD_COUNTER_SHIFT)) >> TD_COUNTER_SHIFT); usb_debug("|:| N | Low Speed Device | [%lx] |:|\n", (td->ctrlsts & (1UL << 26)) >> 26); usb_debug("|:| T | Isochronous Select | [%lx] |:|\n", (td->ctrlsts & (1UL << 25)) >> 25); usb_debug("|:| R | Interrupt on Complete (IOC) | [%lx] |:|\n", (td->ctrlsts & (1UL << 24)) >> 24); @@ -101,7 +102,7 @@ static void td_dump(td_t *td) usb_debug("|:| S ----------------------------------------|:|\n"); usb_debug("|:| | Actual Length | [%04lx] |:|\n", td->ctrlsts & 0x7FFUL); usb_debug("|:+-----------------------------------------------+:|\n"); - usb_debug("|:| Buffer pointer [0x%08lx] |:|\n", td->bufptr); + usb_debug("|:| Buffer pointer [0x%08"PRIx32"] |:|\n", td->bufptr); usb_debug("|:|-----------------------------------------------|:|\n"); usb_debug("|...................................................|\n"); usb_debug("+---------------------------------------------------+\n"); diff --git a/payloads/libpayload/drivers/usb/usb.c b/payloads/libpayload/drivers/usb/usb.c index ec49a5481e..ed33147c51 100644 --- a/payloads/libpayload/drivers/usb/usb.c +++ b/payloads/libpayload/drivers/usb/usb.c @@ -28,6 +28,7 @@ //#define USB_DEBUG +#include #include #include @@ -229,7 +230,7 @@ get_free_address (hci_t *controller) int i = controller->latest_address + 1; for (; i != controller->latest_address; i++) { if (i >= ARRAY_SIZE(controller->devices) || i < 1) { - usb_debug("WARNING: Device addresses for controller %#x" + usb_debug("WARNING: Device addresses for controller %#" PRIxPTR " wrapped around!\n", controller->reg_base); i = 0; continue; diff --git a/payloads/libpayload/drivers/usb/xhci.c b/payloads/libpayload/drivers/usb/xhci.c index 749ff0a066..c40e641c4c 100644 --- a/payloads/libpayload/drivers/usb/xhci.c +++ b/payloads/libpayload/drivers/usb/xhci.c @@ -194,7 +194,7 @@ xhci_init (unsigned long physical_bar) xhci->hcrreg = phys_to_virt(physical_bar) + xhci->capreg->rtsoff; xhci->dbreg = phys_to_virt(physical_bar) + xhci->capreg->dboff; - xhci_debug("regbase: 0x%"PRIx32"\n", physical_bar); + xhci_debug("regbase: 0x%"PRIxPTR"\n", physical_bar); xhci_debug("caplen: 0x%"PRIx32"\n", CAP_GET(CAPLEN, xhci->capreg)); xhci_debug("rtsoff: 0x%"PRIx32"\n", xhci->capreg->rtsoff); xhci_debug("dboff: 0x%"PRIx32"\n", xhci->capreg->dboff); @@ -208,8 +208,8 @@ xhci_init (unsigned long physical_bar) } xhci_debug("context size: %dB\n", CTXSIZE(xhci)); - xhci_debug("maxslots: 0x%02lx\n", CAP_GET(MAXSLOTS, xhci->capreg)); - xhci_debug("maxports: 0x%02lx\n", CAP_GET(MAXPORTS, xhci->capreg)); + xhci_debug("maxslots: 0x%02"PRIx32"\n", CAP_GET(MAXSLOTS, xhci->capreg)); + xhci_debug("maxports: 0x%02"PRIx32"\n", CAP_GET(MAXPORTS, xhci->capreg)); const unsigned pagesize = xhci->opreg->pagesize << 12; xhci_debug("pagesize: 0x%04x\n", pagesize); @@ -374,7 +374,7 @@ xhci_reinit (hci_t *controller) /* Initialize command ring */ xhci_init_cycle_ring(&xhci->cr, COMMAND_RING_SIZE); - xhci_debug("command ring @%p (0x%08x)\n", + xhci_debug("command ring @%p (0x%08"PRIxPTR")\n", xhci->cr.ring, virt_to_phys(xhci->cr.ring)); xhci->opreg->crcr_lo = virt_to_phys(xhci->cr.ring) | CRCR_RCS; xhci->opreg->crcr_hi = 0; @@ -384,9 +384,9 @@ xhci_reinit (hci_t *controller) /* Initialize event ring */ xhci_reset_event_ring(&xhci->er); - xhci_debug("event ring @%p (0x%08x)\n", + xhci_debug("event ring @%p (0x%08"PRIxPTR")\n", xhci->er.ring, virt_to_phys(xhci->er.ring)); - xhci_debug("ERST Max: 0x%lx -> 0x%lx entries\n", + xhci_debug("ERST Max: 0x%"PRIx32" -> 0x%x entries\n", CAP_GET(ERST_MAX, xhci->capreg), 1 << CAP_GET(ERST_MAX, xhci->capreg)); memset((void*)xhci->ev_ring_table, 0x00, sizeof(erst_entry_t)); From 6de5bf669850efb214fb30feb2bc07460baa5c91 Mon Sep 17 00:00:00 2001 From: Caveh Jalali Date: Fri, 28 Aug 2020 17:14:51 -0700 Subject: [PATCH 092/107] libpayload/usb: Add format string checking to usb_debug This turns on the compiler's printf style format string checker. BUG=b:167517417 TEST=enabled all USB controllers on volteer and fixed resulting compiler errors when USB_DEBUG is enabled. Change-Id: Ic94ebcbafdde8a5f79278b5635111b99af40f892 Signed-off-by: Caveh Jalali Reviewed-on: https://review.coreboot.org/c/coreboot/+/45025 Reviewed-by: Tim Wawrzynczak Tested-by: build bot (Jenkins) --- payloads/libpayload/include/usb/usb.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/payloads/libpayload/include/usb/usb.h b/payloads/libpayload/include/usb/usb.h index f79fc27711..43c7b4279d 100644 --- a/payloads/libpayload/include/usb/usb.h +++ b/payloads/libpayload/include/usb/usb.h @@ -334,7 +334,7 @@ int usb_interface_check(u16 vendor, u16 device); #define USB_QUIRK_TEST (1 << 31) #define USB_QUIRK_NONE 0 -static inline void usb_debug(const char *fmt, ...) +static inline void __attribute__((format(printf, 1, 2))) usb_debug(const char *fmt, ...) { #ifdef USB_DEBUG va_list ap; From 191bd827344302561c2aa900e5e5ecdd088c5888 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 21 Nov 2020 19:30:57 +0530 Subject: [PATCH 093/107] soc/intel/alderlake: Update DCACHE_BSP_STACK_SIZE and DCACHE_RAM_SIZE According to the latest Alderlake Platform FSP Integration Guide, the minimum amount of stack needed for FSP-M is 512KiB. Change DCACHE_RAM_SIZE and DCACHE_BSP_STACK_SIZE to reflect that (plus 1KB previously determined empirically). TEST=Able to pass FSP-M MRC training on LPDDR5 SKU without any hang. Change-Id: Ic831ca9110a15fdb48ad31a7db396740811bf0f2 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47837 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Angel Pons --- src/soc/intel/alderlake/Kconfig | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0db8e1ceb2..0aab3c582f 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -70,18 +70,18 @@ config DCACHE_RAM_BASE default 0xfef00000 config DCACHE_RAM_SIZE - default 0x80000 + default 0xc0000 help The size of the cache-as-ram region required during bootblock and/or romstage. config DCACHE_BSP_STACK_SIZE hex - default 0x40400 + default 0x80400 help The amount of anticipated stack usage in CAR by bootblock and other stages. In the case of FSP_USES_CB_STACK default value will be - sum of FSP-M stack requirement(256KiB) and CB romstage stack requirement + sum of FSP-M stack requirement(512KiB) and CB romstage stack requirement (~1KiB). config FSP_TEMP_RAM_SIZE From 8ed53ec8c06c7468a3c4ea1e8fb40012cc375d38 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sat, 21 Nov 2020 19:50:56 +0530 Subject: [PATCH 094/107] mb/intel/adlrvp: Enable pre-boot display over HDMI-B port List of changes: 1. Configure CTRLCLK and CTRLDATA for HDMI 2. Enable Ddc and HPD for Port-B 3. Disable dual eDP configuration for Port-A and B TEST=Able to see depthcharge pre-boot screens over HDMI-B port. Change-Id: I7509b981f35fc60a7885b2b07067cb0d35ec625f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47838 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/devicetree.cb | 4 +++- src/mainboard/intel/adlrvp/gpio.c | 5 +++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index ce55fa3914..80edb92003 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -90,7 +90,9 @@ chip soc/intel/alderlake # Enable EDP in PortA register "DdiPortAConfig" = "1" - register "DdiPortBConfig" = "1" + # Enable HDMI in Port B + register "DdiPortBDdc" = "1" + register "DdiPortBHpd" = "1" # TCSS USB3 register "TcssAuxOri" = "0" diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index a44d4ac43d..89e6f5826b 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -287,6 +287,11 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_H21, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H22, NONE, DEEP, NF1), PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), + + /* A21 : HDMI CRLS CTRLCLK */ + PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1), + /* A22 : HDMI CRLS CTRLDATA */ + PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1), }; void variant_configure_gpio_pads(void) From 447233ce8c25863c2236d0b208bff7f63cd738fb Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 22 Nov 2020 15:16:12 +0530 Subject: [PATCH 095/107] soc/intel/alderlake: Update UART0 GPIO as per latest schematics UART0_RX: C8 -> H10 UART0_TX: C9 -> H11 GPIO PIN Mode: NF1 -> NF2 Change-Id: I7a193b67e22258ff600679f27955a37480ed3f0d Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47847 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/soc/intel/alderlake/uart.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/alderlake/uart.c b/src/soc/intel/alderlake/uart.c index cdbf8ec123..a3bdc4a3ba 100644 --- a/src/soc/intel/alderlake/uart.c +++ b/src/soc/intel/alderlake/uart.c @@ -21,8 +21,8 @@ const struct uart_gpio_pad_config uart_gpio_pads[] = { { .console_index = 0, .gpios = { - PAD_CFG_NF(GPP_C8, NONE, DEEP, NF1), /* UART0 RX */ - PAD_CFG_NF(GPP_C9, NONE, DEEP, NF1), /* UART0 TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), /* UART0 RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), /* UART0 TX */ }, }, { From 2c0aa00d6e562b2e6dbe580e188e24ce5e4336e2 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 3 Nov 2020 00:03:32 +0100 Subject: [PATCH 096/107] mb/**/cmos.layout: Remove crusty comments Most of these comments have been copy-pasted or serve no purpose other than to eventually turn into misleading info. While the description of the first 120 bits of CMOS could be useful, it should instead be added to the documentation for the CMOS option infrastructure, or /dev/null. Moreover, trim down newlines to no more than two consecutive newlines. Change-Id: I119b248821221e68c4e31edba71ba83b7d2e14e9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47143 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/acer/g43t-am3/cmos.layout | 1 - src/mainboard/amd/inagua/cmos.layout | 3 -- src/mainboard/amd/olivehill/cmos.layout | 1 - src/mainboard/amd/parmer/cmos.layout | 1 - src/mainboard/amd/persimmon/cmos.layout | 3 -- src/mainboard/amd/south_station/cmos.layout | 3 -- src/mainboard/amd/thatcher/cmos.layout | 1 - src/mainboard/amd/union_station/cmos.layout | 3 -- src/mainboard/apple/macbook21/cmos.layout | 26 ---------- src/mainboard/apple/macbookair4_2/cmos.layout | 24 ---------- src/mainboard/asrock/b85m_pro4/cmos.layout | 2 - src/mainboard/asrock/e350m1/cmos.layout | 3 -- src/mainboard/asrock/g41c-gs/cmos.layout | 25 ---------- src/mainboard/asrock/h110m/cmos.layout | 47 ------------------ src/mainboard/asrock/h81m-hds/cmos.layout | 22 --------- src/mainboard/asrock/imb-a180/cmos.layout | 1 - src/mainboard/asus/a88xm-e/cmos.layout | 1 - src/mainboard/asus/am1i-a/cmos.layout | 1 - src/mainboard/asus/f2a85-m/cmos.layout | 1 - src/mainboard/asus/h61m-cs/cmos.layout | 27 ----------- .../asus/maximus_iv_gene-z/cmos.layout | 22 --------- src/mainboard/asus/p5gc-mx/cmos.layout | 7 --- src/mainboard/asus/p5qc/cmos.layout | 23 --------- src/mainboard/asus/p5ql-em/cmos.layout | 5 -- src/mainboard/asus/p5qpl-am/cmos.layout | 25 ---------- src/mainboard/asus/p8h61-m_lx/cmos.layout | 22 --------- src/mainboard/asus/p8h61-m_pro/cmos.layout | 27 ----------- src/mainboard/asus/p8z77-m_pro/cmos.layout | 22 --------- src/mainboard/bap/ode_e20XX/cmos.layout | 1 - src/mainboard/biostar/a68n_5200/cmos.layout | 1 - src/mainboard/biostar/am1ml/cmos.layout | 1 - src/mainboard/dell/optiplex_9010/cmos.layout | 20 -------- src/mainboard/elmex/pcm205400/cmos.layout | 3 -- src/mainboard/facebook/fbg1701/cmos.layout | 48 ------------------- src/mainboard/facebook/monolith/cmos.layout | 48 ------------------- src/mainboard/foxconn/d41s/cmos.layout | 6 --- src/mainboard/foxconn/g41s-k/cmos.layout | 25 ---------- src/mainboard/getac/p470/cmos.layout | 26 ---------- .../gigabyte/ga-945gcm-s2l/cmos.layout | 26 ---------- .../gigabyte/ga-b75m-d3h/cmos.layout | 27 ----------- .../gigabyte/ga-g41m-es2l/cmos.layout | 26 ---------- .../gigabyte/ga-h61m-series/cmos.layout | 27 ----------- src/mainboard/gizmosphere/gizmo/cmos.layout | 3 -- src/mainboard/gizmosphere/gizmo2/cmos.layout | 1 - src/mainboard/google/auron/cmos.layout | 27 ----------- src/mainboard/google/beltino/cmos.layout | 27 ----------- src/mainboard/google/butterfly/cmos.layout | 28 ----------- src/mainboard/google/cyan/cmos.layout | 47 ------------------ src/mainboard/google/glados/cmos.layout | 47 ------------------ src/mainboard/google/jecht/cmos.layout | 47 ------------------ src/mainboard/google/link/cmos.layout | 28 ----------- src/mainboard/google/parrot/cmos.layout | 28 ----------- src/mainboard/google/rambi/cmos.layout | 27 ----------- src/mainboard/google/slippy/cmos.layout | 27 ----------- src/mainboard/google/stout/cmos.layout | 28 ----------- src/mainboard/hp/abm/cmos.layout | 1 - .../hp/compaq_8200_elite_sff/cmos.layout | 27 ----------- src/mainboard/hp/snb_ivb_laptops/cmos.layout | 25 ---------- .../hp/z220_sff_workstation/cmos.layout | 27 ----------- src/mainboard/ibase/mb899/cmos.layout | 28 ----------- src/mainboard/intel/baskingridge/cmos.layout | 27 ----------- src/mainboard/intel/d510mo/cmos.layout | 6 --- src/mainboard/intel/d945gclf/cmos.layout | 26 ---------- src/mainboard/intel/dg41wv/cmos.layout | 25 ---------- src/mainboard/intel/dg43gt/cmos.layout | 24 ---------- src/mainboard/intel/emeraldlake2/cmos.layout | 28 ----------- src/mainboard/intel/kblrvp/cmos.layout | 47 ------------------ src/mainboard/intel/kunimitsu/cmos.layout | 47 ------------------ src/mainboard/intel/saddlebrook/cmos.layout | 46 ------------------ src/mainboard/intel/strago/cmos.layout | 47 ------------------ src/mainboard/intel/wtm2/cmos.layout | 27 ----------- src/mainboard/jetway/nf81-t56n-lf/cmos.layout | 3 -- src/mainboard/kontron/986lcd-m/cmos.layout | 28 ----------- src/mainboard/kontron/ktqm77/cmos.layout | 27 ----------- src/mainboard/lenovo/g505s/cmos.layout | 1 - src/mainboard/lenovo/l520/cmos.layout | 25 ---------- src/mainboard/lenovo/t400/cmos.layout | 25 ---------- src/mainboard/lenovo/t410/cmos.layout | 26 ---------- src/mainboard/lenovo/t420/cmos.layout | 25 ---------- src/mainboard/lenovo/t420s/cmos.layout | 25 ---------- src/mainboard/lenovo/t430/cmos.layout | 25 ---------- src/mainboard/lenovo/t430s/cmos.layout | 25 ---------- src/mainboard/lenovo/t440p/cmos.layout | 24 ---------- src/mainboard/lenovo/t520/cmos.layout | 25 ---------- src/mainboard/lenovo/t530/cmos.layout | 25 ---------- src/mainboard/lenovo/t60/cmos.layout | 27 ----------- .../lenovo/thinkcentre_a58/cmos.layout | 25 ---------- src/mainboard/lenovo/x131e/cmos.layout | 26 ---------- .../lenovo/x1_carbon_gen1/cmos.layout | 25 ---------- src/mainboard/lenovo/x200/cmos.layout | 25 ---------- src/mainboard/lenovo/x201/cmos.layout | 26 ---------- src/mainboard/lenovo/x220/cmos.layout | 26 ---------- src/mainboard/lenovo/x230/cmos.layout | 25 ---------- src/mainboard/lenovo/x60/cmos.layout | 27 ----------- .../lippert/frontrunner-af/cmos.layout | 3 -- src/mainboard/msi/ms7721/cmos.layout | 1 - src/mainboard/packardbell/ms2290/cmos.layout | 24 ---------- src/mainboard/pcengines/apu1/cmos.layout | 1 - src/mainboard/pcengines/apu2/cmos.layout | 1 - src/mainboard/portwell/m107/cmos.layout | 48 ------------------- src/mainboard/roda/rk886ex/cmos.layout | 27 ----------- src/mainboard/roda/rk9/cmos.layout | 28 ----------- src/mainboard/roda/rv11/cmos.layout | 30 ------------ src/mainboard/samsung/lumpy/cmos.layout | 28 ----------- src/mainboard/samsung/stumpy/cmos.layout | 27 ----------- .../sapphire/pureplatinumh61/cmos.layout | 27 ----------- src/mainboard/supermicro/x10slm-f/cmos.layout | 22 --------- 107 files changed, 2265 deletions(-) diff --git a/src/mainboard/acer/g43t-am3/cmos.layout b/src/mainboard/acer/g43t-am3/cmos.layout index 5f51bb8398..8377631659 100644 --- a/src/mainboard/acer/g43t-am3/cmos.layout +++ b/src/mainboard/acer/g43t-am3/cmos.layout @@ -25,7 +25,6 @@ entries # coreboot config options: northbridge 432 4 e 11 gfx_uma_size - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout index beedaa7930..18bac8ee34 100644 --- a/src/mainboard/amd/inagua/cmos.layout +++ b/src/mainboard/amd/inagua/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock @@ -24,8 +23,6 @@ entries # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/amd/olivehill/cmos.layout +++ b/src/mainboard/amd/olivehill/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/amd/parmer/cmos.layout +++ b/src/mainboard/amd/parmer/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout index beedaa7930..18bac8ee34 100644 --- a/src/mainboard/amd/persimmon/cmos.layout +++ b/src/mainboard/amd/persimmon/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock @@ -24,8 +23,6 @@ entries # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout index beedaa7930..18bac8ee34 100644 --- a/src/mainboard/amd/south_station/cmos.layout +++ b/src/mainboard/amd/south_station/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock @@ -24,8 +23,6 @@ entries # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/amd/thatcher/cmos.layout +++ b/src/mainboard/amd/thatcher/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout index beedaa7930..18bac8ee34 100644 --- a/src/mainboard/amd/union_station/cmos.layout +++ b/src/mainboard/amd/union_station/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock @@ -24,8 +23,6 @@ entries # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index 2df318f036..cbf1d466ec 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -3,43 +3,19 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -53,11 +29,9 @@ entries 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded 937 1 e 1 lpt -#938 46 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout index f4ecb1ecdf..3fffea5e9e 100644 --- a/src/mainboard/apple/macbookair4_2/cmos.layout +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -3,45 +3,21 @@ # ----------------------------------------------------------------- entries # ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 -# ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge #432 5 e 11 gfx_uma_size -#437 3 r 0 unused #440 8 h 0 volume # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/asrock/b85m_pro4/cmos.layout b/src/mainboard/asrock/b85m_pro4/cmos.layout index ed022330dd..efdc333fc2 100644 --- a/src/mainboard/asrock/b85m_pro4/cmos.layout +++ b/src/mainboard/asrock/b85m_pro4/cmos.layout @@ -14,7 +14,6 @@ 984 16 h 0 check_sum # ----------------------------------------------------------------- - # ----------------------------------------------------------------- enumerations # ----------------------------------------------------------------- @@ -41,7 +40,6 @@ 5 2 Keep # ----------------------------------------------------------------- - # ----------------------------------------------------------------- checksums # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout index 75526c6227..b35f0d2249 100644 --- a/src/mainboard/asrock/e350m1/cmos.layout +++ b/src/mainboard/asrock/e350m1/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock @@ -24,8 +23,6 @@ entries # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout index c4f1b08216..ed5cac5725 100644 --- a/src/mainboard/asrock/g41c-gs/cmos.layout +++ b/src/mainboard/asrock/g41c-gs/cmos.layout @@ -3,51 +3,26 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#435 549 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/asrock/h110m/cmos.layout +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout index e03d040796..1f89bef581 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.layout +++ b/src/mainboard/asrock/h81m-hds/cmos.layout @@ -3,28 +3,8 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) @@ -33,9 +13,7 @@ entries # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 4 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte diff --git a/src/mainboard/asrock/imb-a180/cmos.layout b/src/mainboard/asrock/imb-a180/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/asrock/imb-a180/cmos.layout +++ b/src/mainboard/asrock/imb-a180/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout index 2355292411..fa85c710b3 100644 --- a/src/mainboard/asus/a88xm-e/cmos.layout +++ b/src/mainboard/asus/a88xm-e/cmos.layout @@ -5,7 +5,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/asus/am1i-a/cmos.layout b/src/mainboard/asus/am1i-a/cmos.layout index 9f9ee80faa..c00b1c67eb 100644 --- a/src/mainboard/asus/am1i-a/cmos.layout +++ b/src/mainboard/asus/am1i-a/cmos.layout @@ -9,7 +9,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 r 0 reboot_counter -#392 3 r 0 unused #400 1 e 1 power_on_after_fail 412 4 e 6 debug_level 416 4 e 7 boot_first diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/asus/f2a85-m/cmos.layout +++ b/src/mainboard/asus/f2a85-m/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/asus/h61m-cs/cmos.layout b/src/mainboard/asus/h61m-cs/cmos.layout index 1860a78326..0913b6d66d 100644 --- a/src/mainboard/asus/h61m-cs/cmos.layout +++ b/src/mainboard/asus/h61m-cs/cmos.layout @@ -3,55 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 10 r 0 unused 421 1 e 9 sata_mode -#422 2 r 0 unused # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout index c8c53e745c..d3ce21948a 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout +++ b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout @@ -3,28 +3,8 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) @@ -33,9 +13,7 @@ entries # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 4 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout index a7c4b7dba7..356f38ec6f 100644 --- a/src/mainboard/asus/p5gc-mx/cmos.layout +++ b/src/mainboard/asus/p5gc-mx/cmos.layout @@ -3,22 +3,17 @@ # ----------------------------------------------------------------- entries 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -28,11 +23,9 @@ entries # coreboot config options: bootloader 416 512 s 0 boot_devices -#928 80 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/asus/p5qc/cmos.layout b/src/mainboard/asus/p5qc/cmos.layout index 3e8d5f0a77..cd00074c9c 100644 --- a/src/mainboard/asus/p5qc/cmos.layout +++ b/src/mainboard/asus/p5qc/cmos.layout @@ -3,34 +3,13 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console @@ -42,10 +21,8 @@ entries 411 1 e 1 nmi # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge -#432 554 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout index e98886258b..b306341dc5 100644 --- a/src/mainboard/asus/p5ql-em/cmos.layout +++ b/src/mainboard/asus/p5ql-em/cmos.layout @@ -5,29 +5,24 @@ entries # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused # ----------------------------------------------------------------- # coreboot config options: console 395 4 e 6 debug_level # coreboot config options: southbridge -#408 1 e 0 unused 409 2 e 7 power_on_after_fail 411 1 e 1 nmi # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#436 548 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/asus/p5qpl-am/cmos.layout b/src/mainboard/asus/p5qpl-am/cmos.layout index b1f6e77558..cbf83229c9 100644 --- a/src/mainboard/asus/p5qpl-am/cmos.layout +++ b/src/mainboard/asus/p5qpl-am/cmos.layout @@ -3,51 +3,26 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#435 549 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/asus/p8h61-m_lx/cmos.layout b/src/mainboard/asus/p8h61-m_lx/cmos.layout index 2aef2ac876..7fcbcfbfd4 100644 --- a/src/mainboard/asus/p8h61-m_lx/cmos.layout +++ b/src/mainboard/asus/p8h61-m_lx/cmos.layout @@ -3,28 +3,8 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) @@ -33,9 +13,7 @@ entries # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 4 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte diff --git a/src/mainboard/asus/p8h61-m_pro/cmos.layout b/src/mainboard/asus/p8h61-m_pro/cmos.layout index 1860a78326..0913b6d66d 100644 --- a/src/mainboard/asus/p8h61-m_pro/cmos.layout +++ b/src/mainboard/asus/p8h61-m_pro/cmos.layout @@ -3,55 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 10 r 0 unused 421 1 e 9 sata_mode -#422 2 r 0 unused # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index 1b82ffde13..a912c29496 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -3,28 +3,8 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) @@ -33,9 +13,7 @@ entries # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 4 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte # ----------------------------------------------------------------- diff --git a/src/mainboard/bap/ode_e20XX/cmos.layout b/src/mainboard/bap/ode_e20XX/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/bap/ode_e20XX/cmos.layout +++ b/src/mainboard/bap/ode_e20XX/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/biostar/a68n_5200/cmos.layout b/src/mainboard/biostar/a68n_5200/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/biostar/a68n_5200/cmos.layout +++ b/src/mainboard/biostar/a68n_5200/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/biostar/am1ml/cmos.layout b/src/mainboard/biostar/am1ml/cmos.layout index 0cf4ede05a..dd4d88cd66 100644 --- a/src/mainboard/biostar/am1ml/cmos.layout +++ b/src/mainboard/biostar/am1ml/cmos.layout @@ -32,7 +32,6 @@ entries 384 1 e 4 boot_option 386 1 e 1 ECC_memory 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/dell/optiplex_9010/cmos.layout b/src/mainboard/dell/optiplex_9010/cmos.layout index dcf9639d3f..524907712f 100644 --- a/src/mainboard/dell/optiplex_9010/cmos.layout +++ b/src/mainboard/dell/optiplex_9010/cmos.layout @@ -3,25 +3,6 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory @@ -88,7 +69,6 @@ enumerations 9 5 192M 9 6 224M - # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout index bc5b428588..dd35365409 100644 --- a/src/mainboard/elmex/pcm205400/cmos.layout +++ b/src/mainboard/elmex/pcm205400/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 r 0 reboot_bits -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock @@ -24,8 +23,6 @@ entries # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text diff --git a/src/mainboard/facebook/fbg1701/cmos.layout b/src/mainboard/facebook/fbg1701/cmos.layout index f80f2c597f..45b17be291 100644 --- a/src/mainboard/facebook/fbg1701/cmos.layout +++ b/src/mainboard/facebook/fbg1701/cmos.layout @@ -4,78 +4,30 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) # reboot_counter reserved for core, not used by platform. 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#400 1 e 2 unused -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader -#416 568 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/facebook/monolith/cmos.layout b/src/mainboard/facebook/monolith/cmos.layout index 61c34f3a94..0be89b60db 100644 --- a/src/mainboard/facebook/monolith/cmos.layout +++ b/src/mainboard/facebook/monolith/cmos.layout @@ -4,78 +4,30 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option # reboot_counter reserved for core, not used by platform. 388 4 h 0 reboot_counter -#390 2 r 0 unused # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#400 1 e 2 unused -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader -#416 568 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout index 0a329956af..fa9bd26736 100644 --- a/src/mainboard/foxconn/d41s/cmos.layout +++ b/src/mainboard/foxconn/d41s/cmos.layout @@ -3,22 +3,17 @@ # ----------------------------------------------------------------- entries - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -30,7 +25,6 @@ entries 416 512 s 0 boot_devices # coreboot config options: cpu -#945 7 r 0 unused # coreboot config options: northbridge 952 3 e 11 gfx_uma_size diff --git a/src/mainboard/foxconn/g41s-k/cmos.layout b/src/mainboard/foxconn/g41s-k/cmos.layout index c4f1b08216..ed5cac5725 100644 --- a/src/mainboard/foxconn/g41s-k/cmos.layout +++ b/src/mainboard/foxconn/g41s-k/cmos.layout @@ -3,51 +3,26 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#435 549 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index 5f60dc98af..f96a51aae0 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -3,43 +3,19 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -53,11 +29,9 @@ entries 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded 937 1 e 1 lpt -#938 46 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout index e0d6ec5244..58f96f03f1 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout @@ -3,43 +3,19 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -50,11 +26,9 @@ entries # coreboot config options: bootloader 416 512 s 0 boot_devices -#928 80 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout index 1860a78326..0913b6d66d 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -3,55 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 10 r 0 unused 421 1 e 9 sata_mode -#422 2 r 0 unused # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 46940bd91f..1a26c25ca8 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -3,52 +3,26 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#435 549 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/gigabyte/ga-h61m-series/cmos.layout b/src/mainboard/gigabyte/ga-h61m-series/cmos.layout index 1860a78326..0913b6d66d 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/cmos.layout +++ b/src/mainboard/gigabyte/ga-h61m-series/cmos.layout @@ -3,55 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 10 r 0 unused 421 1 e 9 sata_mode -#422 2 r 0 unused # coreboot config options: cpu -#425 7 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/gizmosphere/gizmo/cmos.layout b/src/mainboard/gizmosphere/gizmo/cmos.layout index beedaa7930..18bac8ee34 100644 --- a/src/mainboard/gizmosphere/gizmo/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock @@ -24,8 +23,6 @@ entries # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text diff --git a/src/mainboard/gizmosphere/gizmo2/cmos.layout b/src/mainboard/gizmosphere/gizmo2/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/gizmosphere/gizmo2/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo2/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/google/auron/cmos.layout b/src/mainboard/google/auron/cmos.layout index da1b185c7e..3b2b829209 100644 --- a/src/mainboard/google/auron/cmos.layout +++ b/src/mainboard/google/auron/cmos.layout @@ -3,54 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -58,7 +32,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout index da1b185c7e..3b2b829209 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -3,54 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -58,7 +32,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index bee1e86fe5..9bd6d1b7f6 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -3,52 +3,27 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console # No serial port on this motherboard -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu # hyper_threading not supported by the Celeron 847 on this board #400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -57,8 +32,6 @@ entries # coreboot config options: northbridge 544 3 e 11 gfx_uma_size -#547 437 r 0 unused - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 @@ -66,7 +39,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/google/cyan/cmos.layout +++ b/src/mainboard/google/cyan/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/google/glados/cmos.layout +++ b/src/mainboard/google/glados/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/jecht/cmos.layout b/src/mainboard/google/jecht/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/google/jecht/cmos.layout +++ b/src/mainboard/google/jecht/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index 0cf582192b..eecfdfaf4b 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -3,50 +3,25 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -55,15 +30,12 @@ entries # coreboot config options: northbridge 544 3 e 11 gfx_uma_size -#547 437 r 0 unused - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index 0cf582192b..eecfdfaf4b 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -3,50 +3,25 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -55,15 +30,12 @@ entries # coreboot config options: northbridge 544 3 e 11 gfx_uma_size -#547 437 r 0 unused - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout index da1b185c7e..3b2b829209 100644 --- a/src/mainboard/google/rambi/cmos.layout +++ b/src/mainboard/google/rambi/cmos.layout @@ -3,54 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -58,7 +32,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index da1b185c7e..3b2b829209 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -3,54 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -58,7 +32,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index 0cf582192b..eecfdfaf4b 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -3,50 +3,25 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -55,15 +30,12 @@ entries # coreboot config options: northbridge 544 3 e 11 gfx_uma_size -#547 437 r 0 unused - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/hp/abm/cmos.layout +++ b/src/mainboard/hp/abm/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout index e26a347b0e..7666ddb5cd 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout +++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout @@ -3,54 +3,27 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused 400 3 h 0 psu_fan_lvl -#403 5 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 10 r 0 unused 421 1 e 9 sata_mode -#422 10 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.layout b/src/mainboard/hp/snb_ivb_laptops/cmos.layout index 858dc4e69e..10b2e2a622 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.layout +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -47,11 +24,9 @@ entries 421 1 e 9 sata_mode # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/hp/z220_sff_workstation/cmos.layout b/src/mainboard/hp/z220_sff_workstation/cmos.layout index 33b2068e2b..f5185028e8 100644 --- a/src/mainboard/hp/z220_sff_workstation/cmos.layout +++ b/src/mainboard/hp/z220_sff_workstation/cmos.layout @@ -3,54 +3,27 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused 400 3 h 0 psu_fan_lvl -#403 5 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 10 r 0 unused 421 1 e 9 sata_mode -#422 10 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused 448 128 r 0 vbnv diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout index e51185bc8f..61e63ebd46 100644 --- a/src/mainboard/ibase/mb899/cmos.layout +++ b/src/mainboard/ibase/mb899/cmos.layout @@ -3,43 +3,19 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -50,7 +26,6 @@ entries # coreboot config options: bootloader 416 512 s 0 boot_devices -#928 40 r 0 unused # coreboot config options: mainboard specific options 948 2 e 8 cpufan_cruise_control @@ -64,11 +39,8 @@ entries 969 1 e 2 ethernet2 970 1 e 2 ethernet3 -#971 13 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout index 7c4d614196..6d2caea110 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -3,58 +3,31 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout index 0a329956af..fa9bd26736 100644 --- a/src/mainboard/intel/d510mo/cmos.layout +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -3,22 +3,17 @@ # ----------------------------------------------------------------- entries - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -30,7 +25,6 @@ entries 416 512 s 0 boot_devices # coreboot config options: cpu -#945 7 r 0 unused # coreboot config options: northbridge 952 3 e 11 gfx_uma_size diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index e0d6ec5244..58f96f03f1 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -3,43 +3,19 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -50,11 +26,9 @@ entries # coreboot config options: bootloader 416 512 s 0 boot_devices -#928 80 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/intel/dg41wv/cmos.layout b/src/mainboard/intel/dg41wv/cmos.layout index b1f6e77558..cbf83229c9 100644 --- a/src/mainboard/intel/dg41wv/cmos.layout +++ b/src/mainboard/intel/dg41wv/cmos.layout @@ -3,51 +3,26 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#435 549 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout index 2174ecd097..0bd628c7a7 100644 --- a/src/mainboard/intel/dg43gt/cmos.layout +++ b/src/mainboard/intel/dg43gt/cmos.layout @@ -3,34 +3,13 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console @@ -42,12 +21,9 @@ entries 411 1 e 1 nmi # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#435 549 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index 8c19c753b1..8d47ab18bc 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -3,50 +3,25 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -55,15 +30,12 @@ entries # coreboot config options: northbridge 544 3 e 11 gfx_uma_size -#547 437 r 0 unused - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/intel/kblrvp/cmos.layout +++ b/src/mainboard/intel/kblrvp/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/kunimitsu/cmos.layout b/src/mainboard/intel/kunimitsu/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/intel/kunimitsu/cmos.layout +++ b/src/mainboard/intel/kunimitsu/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout index cc55ccfc71..82d91a3c76 100644 --- a/src/mainboard/intel/saddlebrook/cmos.layout +++ b/src/mainboard/intel/saddlebrook/cmos.layout @@ -4,72 +4,26 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console 392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader -#544 440 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index 8c2244fa55..c66bb07802 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -4,75 +4,29 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -80,7 +34,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index da1b185c7e..3b2b829209 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -3,54 +3,28 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: 416 128 r 0 vbnv -#544 440 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed @@ -58,7 +32,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout index beedaa7930..18bac8ee34 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout +++ b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock @@ -24,8 +23,6 @@ entries # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index cf758b1c38..05ddf368fe 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -3,43 +3,19 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -52,7 +28,6 @@ entries 416 512 s 0 boot_devices 928 8 h 0 boot_default 936 1 e 11 cmos_defaults_loaded -#937 11 r 0 unused # coreboot config options: mainboard specific options 948 2 e 8 cpufan_cruise_control @@ -67,11 +42,8 @@ entries 970 1 e 2 ethernet3 971 1 e 1 lpt -#972 12 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index d63c75deb1..d3ad3233c1 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -3,47 +3,22 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading 401 3 e 12 gfx_uma_size -#404 3 r 0 unused - # coreboot config options: southbridge 407 1 e 1 nmi 408 2 e 7 power_on_after_fail @@ -63,7 +38,6 @@ entries 848 1 e 9 cmos_defaults_loaded 849 1 e 2 ethernet1 850 1 e 2 ethernet2 -#851 5 r 0 unused # coreboot config options: mainboard specific options 856 2 e 8 fan1_mode @@ -80,7 +54,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout index fa4f10be44..d2e1f28bab 100644 --- a/src/mainboard/lenovo/g505s/cmos.layout +++ b/src/mainboard/lenovo/g505s/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout index aecd7f3bca..0d5968c394 100644 --- a/src/mainboard/lenovo/l520/cmos.layout +++ b/src/mainboard/lenovo/l520/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -58,11 +35,9 @@ entries 422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused 440 8 h 0 volume # SandyBridge MRC Scrambler Seed values diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 8d6b608cde..f5cf15c4f0 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 240 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -57,7 +34,6 @@ entries 427 1 e 1 low_battery_beep 428 1 e 1 uwb - # coreboot config options: bootloader 432 512 s 0 boot_devices 944 8 h 0 boot_default @@ -68,7 +44,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 unused # RAM initialization internal data 1024 128 r 0 read_training_results diff --git a/src/mainboard/lenovo/t410/cmos.layout b/src/mainboard/lenovo/t410/cmos.layout index f3e1559a01..0ca4d7af0e 100644 --- a/src/mainboard/lenovo/t410/cmos.layout +++ b/src/mainboard/lenovo/t410/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -57,11 +34,9 @@ entries 420 1 e 1 low_battery_beep 421 1 e 9 sata_mode 422 2 e 11 usb_always_on -#423 1 r 1 unused # coreboot config options: northbridge 424 3 e 10 gfx_uma_size -#427 5 r 0 unused 432 2 e 12 hybrid_graphics_mode # VBOOT @@ -69,7 +44,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index ce5f04d47f..2f67013450 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -58,12 +35,10 @@ entries 422 2 e 13 usb_always_on # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size 435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index ce5f04d47f..2f67013450 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -58,12 +35,10 @@ entries 422 2 e 13 usb_always_on # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size 435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index b38a91b189..e3d3c92ba3 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -58,12 +35,10 @@ entries 422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size 435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused 440 8 h 0 volume # VBOOT diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 1697806aa3..0b7230341a 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -59,12 +36,10 @@ entries 424 1 e 1 f1_to_f12_as_primary # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size 435 1 e 1 enable_dual_graphics -#436 4 r 0 unused 440 8 h 0 volume # VBOOT diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index 222ab40fb8..4287eead03 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -56,7 +33,6 @@ entries # coreboot config options: northbridge 435 1 e 1 enable_dual_graphics -#437 3 r 0 unused 440 8 h 0 volume # VBOOT diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 2dfd682c5a..4f657fdc3f 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -58,12 +35,10 @@ entries 422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size 435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused 440 8 h 0 volume # VBOOT diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index 4130b5f806..a3b0f0637c 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -58,12 +35,10 @@ entries 422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size 435 2 e 12 hybrid_graphics_mode -#437 3 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 246d15d0c5..62f5dbab03 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -52,10 +29,8 @@ entries 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded 937 1 e 1 lpt -#938 7 r 0 unused # coreboot config options: cpu -#945 3 r 0 unused # coreboot config options: ec 948 1 e 1 touchpad @@ -65,14 +40,12 @@ entries 952 8 h 0 volume 960 1 e 9 first_battery 961 1 e 1 trackpoint -#962 1 r 0 unused 963 1 e 1 sticky_fn 964 1 e 1 power_management_beeps 965 1 e 1 low_battery_beep # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout index b1f6e77558..cbf83229c9 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout +++ b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout @@ -3,51 +3,26 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 5 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 4 e 11 gfx_uma_size -#435 549 r 0 unused - # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 32394de59a..2b6253cde0 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -54,14 +31,11 @@ entries 417 1 e 1 fn_ctrl_swap 418 1 e 1 sticky_fn 419 2 e 12 usb_always_on -#421 3 r 0 unused # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout index a3d2a0fb64..e2abae6859 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -58,11 +35,9 @@ entries 422 2 e 10 backlight # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 95c7930fd5..e300bdf5e8 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 240 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -66,7 +43,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 unused # RAM initialization internal data 1024 128 r 0 read_training_results @@ -74,7 +50,6 @@ entries # VBOOT 1152 128 r 0 vbnv - # ----------------------------------------------------------------- enumerations diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index 6dc55b24ec..a8c1d7969a 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -57,11 +34,9 @@ entries 420 1 e 1 low_battery_beep 421 1 e 9 sata_mode 422 2 e 11 usb_always_on -#423 1 r 1 unused # coreboot config options: northbridge 424 3 e 10 gfx_uma_size -#427 5 r 0 unused 432 8 h 0 volume # VBOOT @@ -69,7 +44,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index 740f57a700..ec4cbcbe3e 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -56,14 +33,11 @@ entries 419 1 e 1 power_management_beeps 421 1 e 9 sata_mode 422 2 e 12 usb_always_on -#423 1 r 1 unused # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused 440 8 h 0 volume # VBOOT diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 6a6cdd537b..30845d2db8 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -59,11 +36,9 @@ entries 424 1 e 1 f1_to_f12_as_primary # coreboot config options: cpu -#424 8 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 5 r 0 unused 440 8 h 0 volume diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index 70dcd35210..dcddc69cd2 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte @@ -52,10 +29,8 @@ entries 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded 937 1 e 1 lpt -#938 6 r 0 unused # coreboot config options: cpu -#945 4 r 0 unused # coreboot config options: ec 949 1 e 9 first_battery @@ -63,7 +38,6 @@ entries 951 1 e 1 wwan 952 1 e 1 wlan 953 1 e 1 trackpoint -#954 1 r 0 unused 955 1 e 1 sticky_fn 956 1 e 1 power_management_beeps 959 1 e 1 low_battery_beep @@ -72,7 +46,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/lippert/frontrunner-af/cmos.layout b/src/mainboard/lippert/frontrunner-af/cmos.layout index beedaa7930..18bac8ee34 100644 --- a/src/mainboard/lippert/frontrunner-af/cmos.layout +++ b/src/mainboard/lippert/frontrunner-af/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock @@ -24,8 +23,6 @@ entries # Reserve the extended AMD configuration registers 1000 24 r 0 amd_reserved - - enumerations #ID value text diff --git a/src/mainboard/msi/ms7721/cmos.layout b/src/mainboard/msi/ms7721/cmos.layout index ade4c04bf3..18bac8ee34 100644 --- a/src/mainboard/msi/ms7721/cmos.layout +++ b/src/mainboard/msi/ms7721/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/packardbell/ms2290/cmos.layout b/src/mainboard/packardbell/ms2290/cmos.layout index a3cd554cd2..809f913612 100644 --- a/src/mainboard/packardbell/ms2290/cmos.layout +++ b/src/mainboard/packardbell/ms2290/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -48,7 +25,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout index f2c551f4bf..a1165b118b 100644 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -6,7 +6,6 @@ entries # leave 3 bits to make checksummed area start byte-aligned 392 1 e 2 boot_option 393 1 e 1 multi_core -#394 6 unused 400 4 e 4 debug_level # leave 7 bits to make checksummed area end byte-aligned 408 16 h 0 check_sum diff --git a/src/mainboard/pcengines/apu2/cmos.layout b/src/mainboard/pcengines/apu2/cmos.layout index 8663fcc1ae..dd35365409 100644 --- a/src/mainboard/pcengines/apu2/cmos.layout +++ b/src/mainboard/pcengines/apu2/cmos.layout @@ -8,7 +8,6 @@ entries 0 384 r 0 reserved_memory 384 1 e 4 boot_option 388 4 r 0 reboot_bits -#392 3 r 0 unused 395 1 e 1 hw_scrubber 396 1 e 1 interleave_chip_selects 397 2 e 8 max_mem_clock diff --git a/src/mainboard/portwell/m107/cmos.layout b/src/mainboard/portwell/m107/cmos.layout index f80f2c597f..45b17be291 100644 --- a/src/mainboard/portwell/m107/cmos.layout +++ b/src/mainboard/portwell/m107/cmos.layout @@ -4,78 +4,30 @@ entries #start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -# ----------------------------------------------------------------- -# Status Register A -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -# ----------------------------------------------------------------- -# Status Register B -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) # reboot_counter reserved for core, not used by platform. 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#400 1 e 2 unused -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 5 r 0 unused # coreboot config options: bootloader -#416 568 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/roda/rk886ex/cmos.layout b/src/mainboard/roda/rk886ex/cmos.layout index 755aad009f..f96a51aae0 100644 --- a/src/mainboard/roda/rk886ex/cmos.layout +++ b/src/mainboard/roda/rk886ex/cmos.layout @@ -3,43 +3,19 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi @@ -48,17 +24,14 @@ entries # coreboot config options: northbridge 411 3 e 11 gfx_uma_size - # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded 937 1 e 1 lpt -#938 46 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # RAM initialization internal data 1024 8 r 0 C0WL0REOST diff --git a/src/mainboard/roda/rk9/cmos.layout b/src/mainboard/roda/rk9/cmos.layout index 2dce4640c9..526bc5e690 100644 --- a/src/mainboard/roda/rk9/cmos.layout +++ b/src/mainboard/roda/rk9/cmos.layout @@ -3,53 +3,27 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu -#400 8 r 0 unused # coreboot config options: southbridge 408 1 e 9 sata_mode -#409 7 r 0 unused # coreboot config options: bootloader 416 512 s 0 boot_devices 928 8 h 0 boot_default 936 1 e 8 cmos_defaults_loaded -#937 7 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum @@ -57,8 +31,6 @@ entries # coreboot config options: northbridge 1000 4 e 10 gfx_uma_size -#1004 20 r 0 unused - # RAM initialization internal data 1024 128 r 0 read_training_results diff --git a/src/mainboard/roda/rv11/cmos.layout b/src/mainboard/roda/rv11/cmos.layout index ea36a26644..c32eed267f 100644 --- a/src/mainboard/roda/rv11/cmos.layout +++ b/src/mainboard/roda/rv11/cmos.layout @@ -3,28 +3,8 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) @@ -34,40 +14,30 @@ entries # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 5 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading 401 3 e 9 gfx_uma_size -#404 4 r 0 unused - # coreboot config options: southbridge 408 1 e 1 nmi -#409 2 r 0 unused 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader 416 424 s 0 boot_devices 840 8 h 0 boot_default 848 1 e 7 cmos_defaults_loaded -#851 5 r 0 unused # coreboot config options: mainboard specific options -#856 40 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 960 16 r 0 mrc_scrambler_seed_chk -#976 8 r 0 unused # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/samsung/lumpy/cmos.layout b/src/mainboard/samsung/lumpy/cmos.layout index 4f80ef06e7..8f831ac48b 100644 --- a/src/mainboard/samsung/lumpy/cmos.layout +++ b/src/mainboard/samsung/lumpy/cmos.layout @@ -3,50 +3,25 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # coreboot config options: cpu 400 1 e 2 hyper_threading -#401 7 r 0 unused # coreboot config options: southbridge 408 1 e 1 nmi #409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -55,15 +30,12 @@ entries # coreboot config options: northbridge 544 3 e 11 gfx_uma_size -#547 437 r 0 unused - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/samsung/stumpy/cmos.layout b/src/mainboard/samsung/stumpy/cmos.layout index 8977a9acc8..26ac57e71d 100644 --- a/src/mainboard/samsung/stumpy/cmos.layout +++ b/src/mainboard/samsung/stumpy/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused? # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused # Stumpy USB reset workaround disable 400 8 r 0 stumpy_usb_reset_disable @@ -45,7 +22,6 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 8 sata_mode -#412 4 r 0 unused # coreboot config options: bootloader #Used by ChromeOS: @@ -54,8 +30,6 @@ entries # coreboot config options: northbridge 544 3 e 11 gfx_uma_size -#547 437 r 0 unused - # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed 928 32 r 0 mrc_scrambler_seed_s3 @@ -63,7 +37,6 @@ entries # coreboot config options: check sums 984 16 h 0 check_sum -#1000 24 r 0 amd_reserved # ----------------------------------------------------------------- diff --git a/src/mainboard/sapphire/pureplatinumh61/cmos.layout b/src/mainboard/sapphire/pureplatinumh61/cmos.layout index 06e9085e48..62dae3e968 100644 --- a/src/mainboard/sapphire/pureplatinumh61/cmos.layout +++ b/src/mainboard/sapphire/pureplatinumh61/cmos.layout @@ -3,40 +3,17 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) 384 1 e 4 boot_option 388 4 h 0 reboot_counter -#390 2 r 0 unused # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 6 debug_level -#399 1 r 0 unused 400 8 h 0 volume @@ -44,17 +21,13 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail -#411 10 r 0 unused 421 1 e 9 sata_mode -#422 2 r 0 unused # coreboot config options: cpu 424 1 e 2 hyper_threading -#425 7 r 0 unused # coreboot config options: northbridge 432 3 e 11 gfx_uma_size -#435 549 r 0 unused # SandyBridge MRC Scrambler Seed values 896 32 r 0 mrc_scrambler_seed diff --git a/src/mainboard/supermicro/x10slm-f/cmos.layout b/src/mainboard/supermicro/x10slm-f/cmos.layout index 65b1d9b830..c48abe4ab4 100644 --- a/src/mainboard/supermicro/x10slm-f/cmos.layout +++ b/src/mainboard/supermicro/x10slm-f/cmos.layout @@ -3,28 +3,8 @@ # ----------------------------------------------------------------- entries -# ----------------------------------------------------------------- -# Status Register A -# ----------------------------------------------------------------- -# Status Register B -# ----------------------------------------------------------------- -# Status Register C -#96 4 r 0 status_c_rsvd -#100 1 r 0 uf_flag -#101 1 r 0 af_flag -#102 1 r 0 pf_flag -#103 1 r 0 irqf_flag -# ----------------------------------------------------------------- -# Status Register D -#104 7 r 0 status_d_rsvd -#111 1 r 0 valid_cmos_ram -# ----------------------------------------------------------------- -# Diagnostic Status Register -#112 8 r 0 diag_rsvd1 - # ----------------------------------------------------------------- 0 120 r 0 reserved_memory -#120 264 r 0 unused # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) @@ -33,9 +13,7 @@ entries # ----------------------------------------------------------------- # coreboot config options: console -#392 3 r 0 unused 395 4 e 4 debug_level -#399 1 r 0 unused #400 8 r 0 reserved for century byte From c85cce077cc9ded8f33b9b059ce0b165da618639 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 3 Nov 2020 00:29:39 +0100 Subject: [PATCH 097/107] mb/**/cmos.layout: Indent everything with tabs Time has shown that using spaces never converges into proper alignment. Change-Id: I5338aeaf139580f9eab3e1e02cb910080a95d2c2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47147 Tested-by: build bot (Jenkins) Reviewed-by: Frans Hendriks --- src/mainboard/acer/g43t-am3/cmos.layout | 84 ++++----- src/mainboard/amd/inagua/cmos.layout | 78 ++++---- src/mainboard/amd/olivehill/cmos.layout | 78 ++++---- src/mainboard/amd/parmer/cmos.layout | 78 ++++---- src/mainboard/amd/persimmon/cmos.layout | 78 ++++---- src/mainboard/amd/south_station/cmos.layout | 78 ++++---- src/mainboard/amd/thatcher/cmos.layout | 78 ++++---- src/mainboard/amd/union_station/cmos.layout | 78 ++++---- src/mainboard/apple/macbook21/cmos.layout | 94 ++++----- src/mainboard/apple/macbookair4_2/cmos.layout | 64 +++---- src/mainboard/asrock/e350m1/cmos.layout | 84 ++++----- src/mainboard/asrock/g41c-gs/cmos.layout | 68 +++---- src/mainboard/asrock/h110m/cmos.layout | 62 +++--- src/mainboard/asrock/h81m-hds/cmos.layout | 54 +++--- src/mainboard/asrock/imb-a180/cmos.layout | 78 ++++---- src/mainboard/asus/a88xm-e/cmos.layout | 88 ++++----- src/mainboard/asus/am1i-a/cmos.layout | 70 +++---- src/mainboard/asus/f2a85-m/cmos.layout | 78 ++++---- src/mainboard/asus/h61m-cs/cmos.layout | 70 +++---- .../asus/maximus_iv_gene-z/cmos.layout | 82 ++++---- src/mainboard/asus/p5gc-mx/cmos.layout | 72 +++---- src/mainboard/asus/p5qc/cmos.layout | 58 +++--- src/mainboard/asus/p5ql-em/cmos.layout | 68 +++---- src/mainboard/asus/p5qpl-am/cmos.layout | 68 +++---- src/mainboard/asus/p8h61-m_lx/cmos.layout | 76 ++++---- src/mainboard/asus/p8h61-m_pro/cmos.layout | 70 +++---- src/mainboard/asus/p8z77-m_pro/cmos.layout | 146 +++++++------- src/mainboard/bap/ode_e20XX/cmos.layout | 78 ++++---- src/mainboard/biostar/a68n_5200/cmos.layout | 78 ++++---- src/mainboard/biostar/am1ml/cmos.layout | 148 +++++++-------- src/mainboard/biostar/th61-itx/cmos.layout | 70 +++---- src/mainboard/bostentech/gbyt4/cmos.layout | 54 +++--- src/mainboard/dell/optiplex_9010/cmos.layout | 84 ++++----- src/mainboard/elmex/pcm205400/cmos.layout | 78 ++++---- .../emulation/qemu-i440fx/cmos.layout | 42 ++--- src/mainboard/emulation/qemu-q35/cmos.layout | 42 ++--- src/mainboard/facebook/fbg1701/cmos.layout | 54 +++--- src/mainboard/facebook/monolith/cmos.layout | 54 +++--- src/mainboard/foxconn/d41s/cmos.layout | 72 +++---- src/mainboard/foxconn/g41s-k/cmos.layout | 68 +++---- src/mainboard/getac/p470/cmos.layout | 90 ++++----- .../gigabyte/ga-945gcm-s2l/cmos.layout | 80 ++++---- .../gigabyte/ga-b75m-d3h/cmos.layout | 70 +++---- .../gigabyte/ga-g41m-es2l/cmos.layout | 78 ++++---- .../gigabyte/ga-h61m-series/cmos.layout | 70 +++---- src/mainboard/gizmosphere/gizmo/cmos.layout | 78 ++++---- src/mainboard/gizmosphere/gizmo2/cmos.layout | 78 ++++---- src/mainboard/google/auron/cmos.layout | 60 +++--- src/mainboard/google/beltino/cmos.layout | 60 +++--- src/mainboard/google/butterfly/cmos.layout | 84 ++++----- src/mainboard/google/cyan/cmos.layout | 62 +++--- src/mainboard/google/glados/cmos.layout | 62 +++--- src/mainboard/google/jecht/cmos.layout | 62 +++--- src/mainboard/google/link/cmos.layout | 82 ++++---- src/mainboard/google/parrot/cmos.layout | 82 ++++---- src/mainboard/google/rambi/cmos.layout | 60 +++--- src/mainboard/google/slippy/cmos.layout | 60 +++--- src/mainboard/google/stout/cmos.layout | 82 ++++---- src/mainboard/hp/abm/cmos.layout | 78 ++++---- .../hp/compaq_8200_elite_sff/cmos.layout | 82 ++++---- .../hp/pavilion_m6_1035dx/cmos.layout | 46 ++--- src/mainboard/hp/snb_ivb_laptops/cmos.layout | 84 ++++----- .../hp/z220_sff_workstation/cmos.layout | 84 ++++----- src/mainboard/ibase/mb899/cmos.layout | 168 ++++++++--------- src/mainboard/intel/baskingridge/cmos.layout | 56 +++--- src/mainboard/intel/d510mo/cmos.layout | 72 +++---- src/mainboard/intel/d945gclf/cmos.layout | 80 ++++---- src/mainboard/intel/dg41wv/cmos.layout | 68 +++---- src/mainboard/intel/dg43gt/cmos.layout | 84 ++++----- src/mainboard/intel/emeraldlake2/cmos.layout | 82 ++++---- src/mainboard/intel/kblrvp/cmos.layout | 62 +++--- src/mainboard/intel/kunimitsu/cmos.layout | 62 +++--- src/mainboard/intel/saddlebrook/cmos.layout | 54 +++--- src/mainboard/intel/strago/cmos.layout | 62 +++--- src/mainboard/intel/wtm2/cmos.layout | 60 +++--- src/mainboard/jetway/nf81-t56n-lf/cmos.layout | 78 ++++---- src/mainboard/kontron/986lcd-m/cmos.layout | 178 +++++++++--------- src/mainboard/kontron/bsl6/cmos.layout | 60 +++--- src/mainboard/kontron/ktqm77/cmos.layout | 140 +++++++------- src/mainboard/lenovo/g505s/cmos.layout | 80 ++++---- src/mainboard/lenovo/l520/cmos.layout | 122 ++++++------ src/mainboard/lenovo/t400/cmos.layout | 124 ++++++------ src/mainboard/lenovo/t410/cmos.layout | 114 +++++------ src/mainboard/lenovo/t420/cmos.layout | 132 ++++++------- src/mainboard/lenovo/t420s/cmos.layout | 132 ++++++------- src/mainboard/lenovo/t430/cmos.layout | 132 ++++++------- src/mainboard/lenovo/t430s/cmos.layout | 128 ++++++------- src/mainboard/lenovo/t440p/cmos.layout | 98 +++++----- src/mainboard/lenovo/t520/cmos.layout | 132 ++++++------- src/mainboard/lenovo/t530/cmos.layout | 132 ++++++------- src/mainboard/lenovo/t60/cmos.layout | 116 ++++++------ .../lenovo/thinkcentre_a58/cmos.layout | 68 +++---- src/mainboard/lenovo/x131e/cmos.layout | 108 +++++------ .../lenovo/x1_carbon_gen1/cmos.layout | 124 ++++++------ src/mainboard/lenovo/x200/cmos.layout | 116 ++++++------ src/mainboard/lenovo/x201/cmos.layout | 110 +++++------ src/mainboard/lenovo/x220/cmos.layout | 124 ++++++------ src/mainboard/lenovo/x230/cmos.layout | 126 ++++++------- src/mainboard/lenovo/x60/cmos.layout | 118 ++++++------ .../lippert/frontrunner-af/cmos.layout | 78 ++++---- src/mainboard/msi/ms7721/cmos.layout | 78 ++++---- src/mainboard/packardbell/ms2290/cmos.layout | 76 ++++---- src/mainboard/pcengines/apu1/cmos.layout | 38 ++-- src/mainboard/pcengines/apu2/cmos.layout | 78 ++++---- src/mainboard/portwell/m107/cmos.layout | 54 +++--- src/mainboard/roda/rk886ex/cmos.layout | 90 ++++----- src/mainboard/roda/rk9/cmos.layout | 86 ++++----- src/mainboard/roda/rv11/cmos.layout | 92 ++++----- src/mainboard/samsung/lumpy/cmos.layout | 82 ++++---- src/mainboard/samsung/stumpy/cmos.layout | 84 ++++----- .../sapphire/pureplatinumh61/cmos.layout | 84 ++++----- src/mainboard/siemens/chili/cmos.layout | 58 +++--- src/mainboard/supermicro/x10slm-f/cmos.layout | 56 +++--- .../supermicro/x11-lga1151-series/cmos.layout | 54 +++--- 114 files changed, 4733 insertions(+), 4733 deletions(-) diff --git a/src/mainboard/acer/g43t-am3/cmos.layout b/src/mainboard/acer/g43t-am3/cmos.layout index 8377631659..9f5012adb4 100644 --- a/src/mainboard/acer/g43t-am3/cmos.layout +++ b/src/mainboard/acer/g43t-am3/cmos.layout @@ -4,67 +4,67 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 10 sata_mode -409 2 e 7 power_on_after_fail -411 1 e 1 nmi +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi # coreboot config options: cpu # coreboot config options: northbridge -432 4 e 11 gfx_uma_size +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -10 0 AHCI -10 1 Compatible -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/amd/inagua/cmos.layout b/src/mainboard/amd/inagua/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/amd/inagua/cmos.layout +++ b/src/mainboard/amd/inagua/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/olivehill/cmos.layout b/src/mainboard/amd/olivehill/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/amd/olivehill/cmos.layout +++ b/src/mainboard/amd/olivehill/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/parmer/cmos.layout b/src/mainboard/amd/parmer/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/amd/parmer/cmos.layout +++ b/src/mainboard/amd/parmer/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/persimmon/cmos.layout b/src/mainboard/amd/persimmon/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/amd/persimmon/cmos.layout +++ b/src/mainboard/amd/persimmon/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/south_station/cmos.layout b/src/mainboard/amd/south_station/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/amd/south_station/cmos.layout +++ b/src/mainboard/amd/south_station/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/thatcher/cmos.layout b/src/mainboard/amd/thatcher/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/amd/thatcher/cmos.layout +++ b/src/mainboard/amd/thatcher/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/amd/union_station/cmos.layout b/src/mainboard/amd/union_station/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/amd/union_station/cmos.layout +++ b/src/mainboard/amd/union_station/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/apple/macbook21/cmos.layout b/src/mainboard/apple/macbook21/cmos.layout index cbf1d466ec..5d3d0746ab 100644 --- a/src/mainboard/apple/macbook21/cmos.layout +++ b/src/mainboard/apple/macbook21/cmos.layout @@ -4,76 +4,76 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/apple/macbookair4_2/cmos.layout b/src/mainboard/apple/macbookair4_2/cmos.layout index 3fffea5e9e..6a23ab6853 100644 --- a/src/mainboard/apple/macbookair4_2/cmos.layout +++ b/src/mainboard/apple/macbookair4_2/cmos.layout @@ -3,49 +3,49 @@ # ----------------------------------------------------------------- entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +395 4 e 6 debug_level +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu # coreboot config options: northbridge -#432 5 e 11 gfx_uma_size -#440 8 h 0 volume +#432 5 e 11 gfx_uma_size +#440 8 h 0 volume # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums checksum 392 447 984 diff --git a/src/mainboard/asrock/e350m1/cmos.layout b/src/mainboard/asrock/e350m1/cmos.layout index b35f0d2249..28b4b42be1 100644 --- a/src/mainboard/asrock/e350m1/cmos.layout +++ b/src/mainboard/asrock/e350m1/cmos.layout @@ -5,52 +5,52 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 2 e 3 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 2 e 3 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -3 0 Off -3 1 On -3 2 Last -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +3 0 Off +3 1 On +3 2 Last +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/asrock/g41c-gs/cmos.layout b/src/mainboard/asrock/g41c-gs/cmos.layout index ed5cac5725..a9abba3f81 100644 --- a/src/mainboard/asrock/g41c-gs/cmos.layout +++ b/src/mainboard/asrock/g41c-gs/cmos.layout @@ -4,59 +4,59 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu # coreboot config options: northbridge -432 4 e 11 gfx_uma_size +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asrock/h110m/cmos.layout b/src/mainboard/asrock/h110m/cmos.layout index c66bb07802..929f7aaf9b 100644 --- a/src/mainboard/asrock/h110m/cmos.layout +++ b/src/mainboard/asrock/h110m/cmos.layout @@ -3,61 +3,61 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asrock/h81m-hds/cmos.layout b/src/mainboard/asrock/h81m-hds/cmos.layout index 1f89bef581..c9ba76c78f 100644 --- a/src/mainboard/asrock/h81m-hds/cmos.layout +++ b/src/mainboard/asrock/h81m-hds/cmos.layout @@ -4,53 +4,53 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option -388 4 h 0 reboot_counter +384 1 e 3 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 4 debug_level +395 4 e 4 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 5 power_on_after_fail +408 1 e 1 nmi +409 2 e 5 power_on_after_fail # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable +#ID value text +1 0 Disable +1 1 Enable -2 0 Enable -2 1 Disable +2 0 Enable +2 1 Disable -3 0 Fallback -3 1 Normal +3 0 Fallback +3 1 Normal -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew -5 0 Disable -5 1 Enable -5 2 Keep +5 0 Disable +5 1 Enable +5 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asrock/imb-a180/cmos.layout b/src/mainboard/asrock/imb-a180/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/asrock/imb-a180/cmos.layout +++ b/src/mainboard/asrock/imb-a180/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/asus/a88xm-e/cmos.layout b/src/mainboard/asus/a88xm-e/cmos.layout index fa85c710b3..4839dd57b8 100644 --- a/src/mainboard/asus/a88xm-e/cmos.layout +++ b/src/mainboard/asus/a88xm-e/cmos.layout @@ -2,54 +2,54 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -#456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +#456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/asus/am1i-a/cmos.layout b/src/mainboard/asus/am1i-a/cmos.layout index c00b1c67eb..40d77fda92 100644 --- a/src/mainboard/asus/am1i-a/cmos.layout +++ b/src/mainboard/asus/am1i-a/cmos.layout @@ -5,45 +5,45 @@ entries -#start-bit length config config-ID name -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 r 0 reboot_counter -#400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 r 0 boot_index -432 8 r 0 boot_countdown -440 8 e 10 sata_mode -448 8 e 11 sata_speed -#728 256 h 0 user_data -984 16 h 0 check_sum +#start-bit length config config-ID name +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_counter +#400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 r 0 boot_index +432 8 r 0 boot_countdown +440 8 e 10 sata_mode +448 8 e 11 sata_speed +#728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -#1 0 Disable -#1 1 Enable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -10 0 IDE -10 2 AHCI -11 1 3Gbps -11 0 6Gbps +#ID value text +#1 0 Disable +#1 1 Enable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +10 0 IDE +10 2 AHCI +11 1 3Gbps +11 0 6Gbps checksums diff --git a/src/mainboard/asus/f2a85-m/cmos.layout b/src/mainboard/asus/f2a85-m/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/asus/f2a85-m/cmos.layout +++ b/src/mainboard/asus/f2a85-m/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/asus/h61m-cs/cmos.layout b/src/mainboard/asus/h61m-cs/cmos.layout index 0913b6d66d..8c6a055ca3 100644 --- a/src/mainboard/asus/h61m-cs/cmos.layout +++ b/src/mainboard/asus/h61m-cs/cmos.layout @@ -4,61 +4,61 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +421 1 e 9 sata_mode # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout index d3ce21948a..54a379b770 100644 --- a/src/mainboard/asus/maximus_iv_gene-z/cmos.layout +++ b/src/mainboard/asus/maximus_iv_gene-z/cmos.layout @@ -4,73 +4,73 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option -388 4 h 0 reboot_counter +384 1 e 3 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 4 debug_level +395 4 e 4 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 5 power_on_after_fail -411 1 e 6 sata_mode +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode # coreboot config options: northbridge -412 3 e 7 gfx_uma_size +412 3 e 7 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable +#ID value text +1 0 Disable +1 1 Enable -2 0 Enable -2 1 Disable +2 0 Enable +2 1 Disable -3 0 Fallback -3 1 Normal +3 0 Fallback +3 1 Normal -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew -5 0 Disable -5 1 Enable -5 2 Keep +5 0 Disable +5 1 Enable +5 2 Keep -6 0 AHCI -6 1 Compatible +6 0 AHCI +6 1 Compatible -7 0 32M -7 1 64M -7 2 96M -7 3 128M -7 4 160M -7 5 192M -7 6 224M +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p5gc-mx/cmos.layout b/src/mainboard/asus/p5gc-mx/cmos.layout index 356f38ec6f..08fe2255c1 100644 --- a/src/mainboard/asus/p5gc-mx/cmos.layout +++ b/src/mainboard/asus/p5gc-mx/cmos.layout @@ -2,65 +2,65 @@ # ----------------------------------------------------------------- entries -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi +408 1 e 1 nmi # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices +416 512 s 0 boot_devices # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p5qc/cmos.layout b/src/mainboard/asus/p5qc/cmos.layout index cd00074c9c..2b46a5f790 100644 --- a/src/mainboard/asus/p5qc/cmos.layout +++ b/src/mainboard/asus/p5qc/cmos.layout @@ -4,54 +4,54 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 10 sata_mode -409 2 e 7 power_on_after_fail -411 1 e 1 nmi +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi # coreboot config options: cpu # coreboot config options: northbridge # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -10 0 AHCI -10 1 Compatible +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p5ql-em/cmos.layout b/src/mainboard/asus/p5ql-em/cmos.layout index b306341dc5..70f29b7a3b 100644 --- a/src/mainboard/asus/p5ql-em/cmos.layout +++ b/src/mainboard/asus/p5ql-em/cmos.layout @@ -4,59 +4,59 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -409 2 e 7 power_on_after_fail -411 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 1 nmi # coreboot config options: cpu # coreboot config options: northbridge -432 4 e 11 gfx_uma_size +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p5qpl-am/cmos.layout b/src/mainboard/asus/p5qpl-am/cmos.layout index cbf83229c9..11a078e35c 100644 --- a/src/mainboard/asus/p5qpl-am/cmos.layout +++ b/src/mainboard/asus/p5qpl-am/cmos.layout @@ -4,59 +4,59 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu # coreboot config options: northbridge -432 4 e 11 gfx_uma_size +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p8h61-m_lx/cmos.layout b/src/mainboard/asus/p8h61-m_lx/cmos.layout index 7fcbcfbfd4..782a1b8c10 100644 --- a/src/mainboard/asus/p8h61-m_lx/cmos.layout +++ b/src/mainboard/asus/p8h61-m_lx/cmos.layout @@ -4,68 +4,68 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option -388 4 h 0 reboot_counter +384 1 e 3 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 4 debug_level +395 4 e 4 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 5 power_on_after_fail -411 1 e 6 sata_mode +408 1 e 1 nmi +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode # coreboot config options: northbridge -412 3 e 7 gfx_uma_size +412 3 e 7 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable +#ID value text +1 0 Disable +1 1 Enable -2 0 Enable -2 1 Disable +2 0 Enable +2 1 Disable -3 0 Fallback -3 1 Normal +3 0 Fallback +3 1 Normal -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew -5 0 Disable -5 1 Enable -5 2 Keep +5 0 Disable +5 1 Enable +5 2 Keep -6 0 AHCI -6 1 Compatible +6 0 AHCI +6 1 Compatible -7 0 32M -7 1 64M -7 2 96M -7 3 128M -7 4 160M -7 5 192M -7 6 224M +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p8h61-m_pro/cmos.layout b/src/mainboard/asus/p8h61-m_pro/cmos.layout index 0913b6d66d..8c6a055ca3 100644 --- a/src/mainboard/asus/p8h61-m_pro/cmos.layout +++ b/src/mainboard/asus/p8h61-m_pro/cmos.layout @@ -4,61 +4,61 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +421 1 e 9 sata_mode # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/asus/p8z77-m_pro/cmos.layout b/src/mainboard/asus/p8z77-m_pro/cmos.layout index a912c29496..3d717b444d 100644 --- a/src/mainboard/asus/p8z77-m_pro/cmos.layout +++ b/src/mainboard/asus/p8z77-m_pro/cmos.layout @@ -4,27 +4,27 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 3 boot_option -388 4 h 0 reboot_counter +384 1 e 3 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 4 debug_level -#400 8 r 0 reserved for century byte +395 4 e 4 debug_level +#400 8 r 0 reserved for century byte # ----------------------------------------------------------------- # coreboot config options: southbridge # Non Maskable Interrupt(NMI) support, which is an interrupt that may # occur on a RAM or unrecoverable error. -408 1 e 1 nmi +408 1 e 1 nmi -409 2 e 5 power_on_after_fail -411 1 e 6 sata_mode +409 2 e 5 power_on_after_fail +411 1 e 6 sata_mode # ----------------------------------------------------------------- # coreboot config options: northbridge @@ -32,119 +32,119 @@ entries # gfx_uma_size # Quantity of shared video memory the IGP can use # -416 5 e 7 gfx_uma_size +416 5 e 7 gfx_uma_size # ----------------------------------------------------------------- # coreboot config options: usb3 # usb3_mode # Controls how the motherboard's USB3 ports act at boot time -421 2 e 8 usb3_mode +421 2 e 8 usb3_mode # usb3_drv # Load (or not) pre-OS xHCI USB3 BIOS driver # -423 1 e 1 usb3_drv +423 1 e 1 usb3_drv # usb3_streams # Streams can provide more speed (as they can use 64Kb packets), # but they might cause incompatibilities with some devices. # -424 1 e 1 usb3_streams +424 1 e 1 usb3_streams # ----------------------------------------------------------------- # Sandy/Ivy Bridge MRC Scrambler Seed values # note: MUST NOT be covered by checksum! -464 32 r 0 mrc_scrambler_seed -496 32 r 0 mrc_scrambler_seed_s3 -528 16 r 0 mrc_scrambler_seed_chk +464 32 r 0 mrc_scrambler_seed +496 32 r 0 mrc_scrambler_seed_s3 +528 16 r 0 mrc_scrambler_seed_chk # ----------------------------------------------------------------- # coreboot config options: check sums -544 16 h 0 check_sum +544 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text +#ID value text # Generic on/off enum -1 0 Disable -1 1 Enable +1 0 Disable +1 1 Enable # boot_option -3 0 Fallback -3 1 Normal +3 0 Fallback +3 1 Normal # debug_level -4 0 Emergency -4 1 Alert -4 2 Critical -4 3 Error -4 4 Warning -4 5 Notice -4 6 Info -4 7 Debug -4 8 Spew +4 0 Emergency +4 1 Alert +4 2 Critical +4 3 Error +4 4 Warning +4 5 Notice +4 6 Info +4 7 Debug +4 8 Spew # power_on_after_fail -5 0 Disable -5 1 Enable -5 2 Keep +5 0 Disable +5 1 Enable +5 2 Keep # sata_mode -6 0 AHCI -6 1 Compatible +6 0 AHCI +6 1 Compatible # gfx_uma_size (Intel IGP Video RAM size) -7 0 32M -7 1 64M -7 2 96M -7 3 128M -7 4 160M -7 5 192M -7 6 224M -7 7 256M -7 8 288M -7 9 320M -7 10 352M -7 11 384M -7 12 416M -7 13 448M -7 14 480M -7 15 512M -7 16 544M -7 17 576M -7 18 608M -7 19 640M -7 20 672M -7 21 704M -7 22 736M -7 23 768M -7 24 800M -7 25 832M -7 26 864M -7 27 896M -7 28 928M -7 29 960M -7 30 992M +7 0 32M +7 1 64M +7 2 96M +7 3 128M +7 4 160M +7 5 192M +7 6 224M +7 7 256M +7 8 288M +7 9 320M +7 10 352M +7 11 384M +7 12 416M +7 13 448M +7 14 480M +7 15 512M +7 16 544M +7 17 576M +7 18 608M +7 19 640M +7 20 672M +7 21 704M +7 22 736M +7 23 768M +7 24 800M +7 25 832M +7 26 864M +7 27 896M +7 28 928M +7 29 960M +7 30 992M # usb3_mode # Disable = Use the port always as USB 2.0 for compatibility # Enable = Use the port always as USB 3.0 for speed # Auto = Initialize the port as USB 2.0, until the OS loads -# xHCI USB 3.0 driver +# xHCI USB 3.0 driver # SmartAuto = Same as Auto but, if the OS loads the xHCI USB 3.0 driver -# and the computer is reset, keep the USB 3.0 mode. +# and the computer is reset, keep the USB 3.0 mode. # -8 0 Disable -8 1 Enable -8 2 Auto -8 3 SmartAuto +8 0 Disable +8 1 Enable +8 2 Auto +8 3 SmartAuto # ----------------------------------------------------------------- # -# +# checksums checksum 392 431 544 diff --git a/src/mainboard/bap/ode_e20XX/cmos.layout b/src/mainboard/bap/ode_e20XX/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/bap/ode_e20XX/cmos.layout +++ b/src/mainboard/bap/ode_e20XX/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/biostar/a68n_5200/cmos.layout b/src/mainboard/biostar/a68n_5200/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/biostar/a68n_5200/cmos.layout +++ b/src/mainboard/biostar/a68n_5200/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/biostar/am1ml/cmos.layout b/src/mainboard/biostar/am1ml/cmos.layout index dd4d88cd66..7430eb0389 100644 --- a/src/mainboard/biostar/am1ml/cmos.layout +++ b/src/mainboard/biostar/am1ml/cmos.layout @@ -5,84 +5,84 @@ entries -#start-bit length config config-ID name -#0 8 r 0 seconds -#8 8 r 0 alarm_seconds -#16 8 r 0 minutes -#24 8 r 0 alarm_minutes -#32 8 r 0 hours -#40 8 r 0 alarm_hours -#48 8 r 0 day_of_week -#56 8 r 0 day_of_month -#64 8 r 0 month -#72 8 r 0 year -#80 4 r 0 rate_select -#84 3 r 0 REF_Clock -#87 1 r 0 UIP -#88 1 r 0 auto_switch_DST -#89 1 r 0 24_hour_mode -#90 1 r 0 binary_values_enable -#91 1 r 0 square-wave_out_enable -#92 1 r 0 update_finished_enable -#93 1 r 0 alarm_interrupt_enable -#94 1 r 0 periodic_interrupt_enable -#95 1 r 0 disable_clock_updates -#96 288 r 0 temporary_filler -0 384 r 0 reserved_memory -384 1 e 4 boot_option -386 1 e 1 ECC_memory -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -416 4 e 7 boot_first -420 4 e 7 boot_second -424 4 e 7 boot_third -428 4 h 0 boot_index -432 8 h 0 boot_countdown -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -728 256 h 0 user_data -984 16 h 0 check_sum +#start-bit length config config-ID name +#0 8 r 0 seconds +#8 8 r 0 alarm_seconds +#16 8 r 0 minutes +#24 8 r 0 alarm_minutes +#32 8 r 0 hours +#40 8 r 0 alarm_hours +#48 8 r 0 day_of_week +#56 8 r 0 day_of_month +#64 8 r 0 month +#72 8 r 0 year +#80 4 r 0 rate_select +#84 3 r 0 REF_Clock +#87 1 r 0 UIP +#88 1 r 0 auto_switch_DST +#89 1 r 0 24_hour_mode +#90 1 r 0 binary_values_enable +#91 1 r 0 square-wave_out_enable +#92 1 r 0 update_finished_enable +#93 1 r 0 alarm_interrupt_enable +#94 1 r 0 periodic_interrupt_enable +#95 1 r 0 disable_clock_updates +#96 288 r 0 temporary_filler +0 384 r 0 reserved_memory +384 1 e 4 boot_option +386 1 e 1 ECC_memory +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +416 4 e 7 boot_first +420 4 e 7 boot_second +424 4 e 7 boot_third +428 4 h 0 boot_index +432 8 h 0 boot_countdown +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Network -7 1 HDD -7 2 Floppy -7 8 Fallback_Network -7 9 Fallback_HDD -7 10 Fallback_Floppy -#7 3 ROM -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Network +7 1 HDD +7 2 Floppy +7 8 Fallback_Network +7 9 Fallback_HDD +7 10 Fallback_Floppy +#7 3 ROM +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/biostar/th61-itx/cmos.layout b/src/mainboard/biostar/th61-itx/cmos.layout index 556b34e29d..483512ed07 100644 --- a/src/mainboard/biostar/th61-itx/cmos.layout +++ b/src/mainboard/biostar/th61-itx/cmos.layout @@ -5,60 +5,60 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +421 1 e 9 sata_mode # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/bostentech/gbyt4/cmos.layout b/src/mainboard/bostentech/gbyt4/cmos.layout index f0d18dd7ae..018db314ac 100644 --- a/src/mainboard/bostentech/gbyt4/cmos.layout +++ b/src/mainboard/bostentech/gbyt4/cmos.layout @@ -3,45 +3,45 @@ # ----------------------------------------------------------------- entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/dell/optiplex_9010/cmos.layout b/src/mainboard/dell/optiplex_9010/cmos.layout index 524907712f..cff6004fec 100644 --- a/src/mainboard/dell/optiplex_9010/cmos.layout +++ b/src/mainboard/dell/optiplex_9010/cmos.layout @@ -4,70 +4,70 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: EC -412 1 e 1 fan_full_speed +412 1 e 1 fan_full_speed # coreboot config options: northbridge -432 3 e 9 gfx_uma_size +432 3 e 9 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -9 0 32M -9 1 64M -9 2 96M -9 3 128M -9 4 160M -9 5 192M -9 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +9 0 32M +9 1 64M +9 2 96M +9 3 128M +9 4 160M +9 5 192M +9 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/elmex/pcm205400/cmos.layout b/src/mainboard/elmex/pcm205400/cmos.layout index dd35365409..586e22a9bf 100644 --- a/src/mainboard/elmex/pcm205400/cmos.layout +++ b/src/mainboard/elmex/pcm205400/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 r 0 reboot_bits -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 r 0 reboot_bits +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/emulation/qemu-i440fx/cmos.layout b/src/mainboard/emulation/qemu-i440fx/cmos.layout index 9019afb7a3..8963e13e16 100644 --- a/src/mainboard/emulation/qemu-i440fx/cmos.layout +++ b/src/mainboard/emulation/qemu-i440fx/cmos.layout @@ -1,35 +1,35 @@ entries -0 384 r 0 reserved_memory +0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter -400 8 r 0 reserved_century -440 8 r 0 reserved_ibm_ps2_century +400 8 r 0 reserved_century +440 8 r 0 reserved_ibm_ps2_century -448 1 e 1 power_on_after_fail -452 4 e 6 debug_level -456 1 e 1 ECC_memory +448 1 e 1 power_on_after_fail +452 4 e 6 debug_level +456 1 e 1 ECC_memory # VBOOT -464 128 r 0 vbnv +464 128 r 0 vbnv -1008 16 h 0 check_sum +1008 16 h 0 check_sum enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew checksums diff --git a/src/mainboard/emulation/qemu-q35/cmos.layout b/src/mainboard/emulation/qemu-q35/cmos.layout index 9019afb7a3..8963e13e16 100644 --- a/src/mainboard/emulation/qemu-q35/cmos.layout +++ b/src/mainboard/emulation/qemu-q35/cmos.layout @@ -1,35 +1,35 @@ entries -0 384 r 0 reserved_memory +0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter -400 8 r 0 reserved_century -440 8 r 0 reserved_ibm_ps2_century +400 8 r 0 reserved_century +440 8 r 0 reserved_ibm_ps2_century -448 1 e 1 power_on_after_fail -452 4 e 6 debug_level -456 1 e 1 ECC_memory +448 1 e 1 power_on_after_fail +452 4 e 6 debug_level +456 1 e 1 ECC_memory # VBOOT -464 128 r 0 vbnv +464 128 r 0 vbnv -1008 16 h 0 check_sum +1008 16 h 0 check_sum enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew checksums diff --git a/src/mainboard/facebook/fbg1701/cmos.layout b/src/mainboard/facebook/fbg1701/cmos.layout index 45b17be291..29bc4f80b5 100644 --- a/src/mainboard/facebook/fbg1701/cmos.layout +++ b/src/mainboard/facebook/fbg1701/cmos.layout @@ -3,55 +3,55 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) # reboot_counter reserved for core, not used by platform. -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/facebook/monolith/cmos.layout b/src/mainboard/facebook/monolith/cmos.layout index 0be89b60db..705eaba627 100644 --- a/src/mainboard/facebook/monolith/cmos.layout +++ b/src/mainboard/facebook/monolith/cmos.layout @@ -3,55 +3,55 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option +384 1 e 4 boot_option # reboot_counter reserved for core, not used by platform. -388 4 h 0 reboot_counter +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/foxconn/d41s/cmos.layout b/src/mainboard/foxconn/d41s/cmos.layout index fa9bd26736..a2298978b3 100644 --- a/src/mainboard/foxconn/d41s/cmos.layout +++ b/src/mainboard/foxconn/d41s/cmos.layout @@ -4,64 +4,64 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader -416 512 s 0 boot_devices +416 512 s 0 boot_devices # coreboot config options: cpu # coreboot config options: northbridge -952 3 e 11 gfx_uma_size +952 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 0 8M -11 1 16M -11 2 32M -11 3 48M -11 4 64M -11 5 128M -11 6 256M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 8M +11 1 16M +11 2 32M +11 3 48M +11 4 64M +11 5 128M +11 6 256M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/foxconn/g41s-k/cmos.layout b/src/mainboard/foxconn/g41s-k/cmos.layout index ed5cac5725..a9abba3f81 100644 --- a/src/mainboard/foxconn/g41s-k/cmos.layout +++ b/src/mainboard/foxconn/g41s-k/cmos.layout @@ -4,59 +4,59 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu # coreboot config options: northbridge -432 4 e 11 gfx_uma_size +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/getac/p470/cmos.layout b/src/mainboard/getac/p470/cmos.layout index f96a51aae0..825f54b828 100644 --- a/src/mainboard/getac/p470/cmos.layout +++ b/src/mainboard/getac/p470/cmos.layout @@ -4,74 +4,74 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout index 58f96f03f1..41f967d7ab 100644 --- a/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-945gcm-s2l/cmos.layout @@ -4,69 +4,69 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices +416 512 s 0 boot_devices # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout index 0913b6d66d..8c6a055ca3 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout +++ b/src/mainboard/gigabyte/ga-b75m-d3h/cmos.layout @@ -4,61 +4,61 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +421 1 e 9 sata_mode # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout index 1a26c25ca8..60635e0b2b 100644 --- a/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout +++ b/src/mainboard/gigabyte/ga-g41m-es2l/cmos.layout @@ -4,64 +4,64 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu # coreboot config options: northbridge -432 4 e 11 gfx_uma_size +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/gigabyte/ga-h61m-series/cmos.layout b/src/mainboard/gigabyte/ga-h61m-series/cmos.layout index 0913b6d66d..8c6a055ca3 100644 --- a/src/mainboard/gigabyte/ga-h61m-series/cmos.layout +++ b/src/mainboard/gigabyte/ga-h61m-series/cmos.layout @@ -4,61 +4,61 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +421 1 e 9 sata_mode # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/gizmosphere/gizmo/cmos.layout b/src/mainboard/gizmosphere/gizmo/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/gizmosphere/gizmo/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/gizmosphere/gizmo2/cmos.layout b/src/mainboard/gizmosphere/gizmo2/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/gizmosphere/gizmo2/cmos.layout +++ b/src/mainboard/gizmosphere/gizmo2/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/google/auron/cmos.layout b/src/mainboard/google/auron/cmos.layout index 3b2b829209..283aa1ea35 100644 --- a/src/mainboard/google/auron/cmos.layout +++ b/src/mainboard/google/auron/cmos.layout @@ -4,58 +4,58 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/beltino/cmos.layout b/src/mainboard/google/beltino/cmos.layout index 3b2b829209..283aa1ea35 100644 --- a/src/mainboard/google/beltino/cmos.layout +++ b/src/mainboard/google/beltino/cmos.layout @@ -4,58 +4,58 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/butterfly/cmos.layout b/src/mainboard/google/butterfly/cmos.layout index 9bd6d1b7f6..057f6a5a9e 100644 --- a/src/mainboard/google/butterfly/cmos.layout +++ b/src/mainboard/google/butterfly/cmos.layout @@ -4,74 +4,74 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console # No serial port on this motherboard -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # hyper_threading not supported by the Celeron 847 on this board -#400 1 e 2 hyper_threading +#400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/cyan/cmos.layout b/src/mainboard/google/cyan/cmos.layout index c66bb07802..929f7aaf9b 100644 --- a/src/mainboard/google/cyan/cmos.layout +++ b/src/mainboard/google/cyan/cmos.layout @@ -3,61 +3,61 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/glados/cmos.layout b/src/mainboard/google/glados/cmos.layout index c66bb07802..929f7aaf9b 100644 --- a/src/mainboard/google/glados/cmos.layout +++ b/src/mainboard/google/glados/cmos.layout @@ -3,61 +3,61 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/jecht/cmos.layout b/src/mainboard/google/jecht/cmos.layout index c66bb07802..929f7aaf9b 100644 --- a/src/mainboard/google/jecht/cmos.layout +++ b/src/mainboard/google/jecht/cmos.layout @@ -3,61 +3,61 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/link/cmos.layout b/src/mainboard/google/link/cmos.layout index eecfdfaf4b..5cfca4f15f 100644 --- a/src/mainboard/google/link/cmos.layout +++ b/src/mainboard/google/link/cmos.layout @@ -4,71 +4,71 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/parrot/cmos.layout b/src/mainboard/google/parrot/cmos.layout index eecfdfaf4b..5cfca4f15f 100644 --- a/src/mainboard/google/parrot/cmos.layout +++ b/src/mainboard/google/parrot/cmos.layout @@ -4,71 +4,71 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/rambi/cmos.layout b/src/mainboard/google/rambi/cmos.layout index 3b2b829209..283aa1ea35 100644 --- a/src/mainboard/google/rambi/cmos.layout +++ b/src/mainboard/google/rambi/cmos.layout @@ -4,58 +4,58 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/slippy/cmos.layout b/src/mainboard/google/slippy/cmos.layout index 3b2b829209..283aa1ea35 100644 --- a/src/mainboard/google/slippy/cmos.layout +++ b/src/mainboard/google/slippy/cmos.layout @@ -4,58 +4,58 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/google/stout/cmos.layout b/src/mainboard/google/stout/cmos.layout index eecfdfaf4b..5cfca4f15f 100644 --- a/src/mainboard/google/stout/cmos.layout +++ b/src/mainboard/google/stout/cmos.layout @@ -4,71 +4,71 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/hp/abm/cmos.layout b/src/mainboard/hp/abm/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/hp/abm/cmos.layout +++ b/src/mainboard/hp/abm/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout index 7666ddb5cd..3edda3b7dc 100644 --- a/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout +++ b/src/mainboard/hp/compaq_8200_elite_sff/cmos.layout @@ -4,67 +4,67 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level -400 3 h 0 psu_fan_lvl +395 4 e 6 debug_level +400 3 h 0 psu_fan_lvl # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +421 1 e 9 sata_mode # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout b/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout index 87858cb0a9..1f3fc0a38a 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout +++ b/src/mainboard/hp/pavilion_m6_1035dx/cmos.layout @@ -1,42 +1,42 @@ entries -#start-bit length config config-ID name +#start-bit length config config-ID name # RTC_BOOT_BYTE (coreboot hardcoded) -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter # southbridge/amd/agesa/hudson should use this but it doesn't -400 1 e 1 power_on_after_fail +400 1 e 1 power_on_after_fail # The only option that is actually used -412 4 e 6 debug_level +412 4 e 6 debug_level # southbridge/amd/agesa/hudson should use this but it doesn't -444 1 e 1 nmi +444 1 e 1 nmi -984 16 h 0 check_sum +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew +#ID value text +1 0 Disable +1 1 Enable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew checksums diff --git a/src/mainboard/hp/snb_ivb_laptops/cmos.layout b/src/mainboard/hp/snb_ivb_laptops/cmos.layout index 10b2e2a622..31889ad24b 100644 --- a/src/mainboard/hp/snb_ivb_laptops/cmos.layout +++ b/src/mainboard/hp/snb_ivb_laptops/cmos.layout @@ -4,72 +4,72 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +421 1 e 9 sata_mode # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size -440 8 h 0 volume +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/hp/z220_sff_workstation/cmos.layout b/src/mainboard/hp/z220_sff_workstation/cmos.layout index f5185028e8..1fc83b1a55 100644 --- a/src/mainboard/hp/z220_sff_workstation/cmos.layout +++ b/src/mainboard/hp/z220_sff_workstation/cmos.layout @@ -4,69 +4,69 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level -400 3 h 0 psu_fan_lvl +395 4 e 6 debug_level +400 3 h 0 psu_fan_lvl # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail -421 1 e 9 sata_mode +421 1 e 9 sata_mode # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -9 0 AHCI -9 1 IDE -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +9 0 AHCI +9 1 IDE +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/ibase/mb899/cmos.layout b/src/mainboard/ibase/mb899/cmos.layout index 61e63ebd46..499fc2ccea 100644 --- a/src/mainboard/ibase/mb899/cmos.layout +++ b/src/mainboard/ibase/mb899/cmos.layout @@ -4,120 +4,120 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices +416 512 s 0 boot_devices # coreboot config options: mainboard specific options -948 2 e 8 cpufan_cruise_control -950 2 e 8 sysfan_cruise_control -952 4 e 9 cpufan_speed -#956 4 e 10 cpufan_temperature -960 4 e 9 sysfan_speed -#964 4 e 10 sysfan_temperature +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature -968 1 e 2 ethernet1 -969 1 e 2 ethernet2 -970 1 e 2 ethernet3 +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # Fan Cruise Control -8 0 Disabled -8 1 Speed -#8 2 Thermal +8 0 Disabled +8 1 Speed +#8 2 Thermal # Fan Speed (Rotations per Minute) -9 0 5625 -9 1 5192 -9 2 4753 -9 3 4326 -9 4 3924 -9 5 3552 -9 6 3214 -9 7 2909 -9 8 2636 -9 9 2393 -9 10 2177 -9 11 1985 -9 12 1814 -9 13 1662 -9 14 1527 -9 15 1406 +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 # # Temperature (°C/°F) -#10 0 30/86 -#10 1 33/91 -#10 2 36/96 -#10 3 39/102 -#10 4 42/107 -#10 5 45/113 -#10 6 48/118 -#10 7 51/123 -#10 8 54/129 -#10 9 57/134 -#10 10 60/140 -#10 11 63/145 -#10 12 66/150 -#10 13 69/156 -#10 14 72/161 -#10 15 75/167 -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/baskingridge/cmos.layout b/src/mainboard/intel/baskingridge/cmos.layout index 6d2caea110..77ff74375e 100644 --- a/src/mainboard/intel/baskingridge/cmos.layout +++ b/src/mainboard/intel/baskingridge/cmos.layout @@ -4,54 +4,54 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/d510mo/cmos.layout b/src/mainboard/intel/d510mo/cmos.layout index fa9bd26736..a2298978b3 100644 --- a/src/mainboard/intel/d510mo/cmos.layout +++ b/src/mainboard/intel/d510mo/cmos.layout @@ -4,64 +4,64 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader -416 512 s 0 boot_devices +416 512 s 0 boot_devices # coreboot config options: cpu # coreboot config options: northbridge -952 3 e 11 gfx_uma_size +952 3 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 0 8M -11 1 16M -11 2 32M -11 3 48M -11 4 64M -11 5 128M -11 6 256M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 8M +11 1 16M +11 2 32M +11 3 48M +11 4 64M +11 5 128M +11 6 256M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/d945gclf/cmos.layout b/src/mainboard/intel/d945gclf/cmos.layout index 58f96f03f1..41f967d7ab 100644 --- a/src/mainboard/intel/d945gclf/cmos.layout +++ b/src/mainboard/intel/d945gclf/cmos.layout @@ -4,69 +4,69 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices +416 512 s 0 boot_devices # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/dg41wv/cmos.layout b/src/mainboard/intel/dg41wv/cmos.layout index cbf83229c9..11a078e35c 100644 --- a/src/mainboard/intel/dg41wv/cmos.layout +++ b/src/mainboard/intel/dg41wv/cmos.layout @@ -4,59 +4,59 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu # coreboot config options: northbridge -432 4 e 11 gfx_uma_size +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/dg43gt/cmos.layout b/src/mainboard/intel/dg43gt/cmos.layout index 0bd628c7a7..9f5012adb4 100644 --- a/src/mainboard/intel/dg43gt/cmos.layout +++ b/src/mainboard/intel/dg43gt/cmos.layout @@ -4,67 +4,67 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 10 sata_mode -409 2 e 7 power_on_after_fail -411 1 e 1 nmi +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail +411 1 e 1 nmi # coreboot config options: cpu # coreboot config options: northbridge -432 4 e 11 gfx_uma_size +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -10 0 AHCI -10 1 Compatible -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +10 0 AHCI +10 1 Compatible +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/emeraldlake2/cmos.layout b/src/mainboard/intel/emeraldlake2/cmos.layout index 8d47ab18bc..7301ef9d5d 100644 --- a/src/mainboard/intel/emeraldlake2/cmos.layout +++ b/src/mainboard/intel/emeraldlake2/cmos.layout @@ -4,71 +4,71 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # coreboot config options: northbridge -544 3 e 11 gfx_uma_size +544 3 e 11 gfx_uma_size # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/kblrvp/cmos.layout b/src/mainboard/intel/kblrvp/cmos.layout index c66bb07802..929f7aaf9b 100644 --- a/src/mainboard/intel/kblrvp/cmos.layout +++ b/src/mainboard/intel/kblrvp/cmos.layout @@ -3,61 +3,61 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/kunimitsu/cmos.layout b/src/mainboard/intel/kunimitsu/cmos.layout index c66bb07802..929f7aaf9b 100644 --- a/src/mainboard/intel/kunimitsu/cmos.layout +++ b/src/mainboard/intel/kunimitsu/cmos.layout @@ -3,61 +3,61 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/saddlebrook/cmos.layout b/src/mainboard/intel/saddlebrook/cmos.layout index 82d91a3c76..5a92ae07c9 100644 --- a/src/mainboard/intel/saddlebrook/cmos.layout +++ b/src/mainboard/intel/saddlebrook/cmos.layout @@ -3,54 +3,54 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -392 3 r 0 unused -395 4 e 6 debug_level +392 3 r 0 unused +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -409 2 e 7 power_on_after_fail +409 2 e 7 power_on_after_fail # coreboot config options: bootloader # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/strago/cmos.layout b/src/mainboard/intel/strago/cmos.layout index c66bb07802..929f7aaf9b 100644 --- a/src/mainboard/intel/strago/cmos.layout +++ b/src/mainboard/intel/strago/cmos.layout @@ -3,61 +3,61 @@ # ----------------------------------------------------------------- entries -#start-bit length config config-ID name +#start-bit length config config-ID name # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/intel/wtm2/cmos.layout b/src/mainboard/intel/wtm2/cmos.layout index 3b2b829209..283aa1ea35 100644 --- a/src/mainboard/intel/wtm2/cmos.layout +++ b/src/mainboard/intel/wtm2/cmos.layout @@ -4,58 +4,58 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: bootloader #Used by ChromeOS: -416 128 r 0 vbnv +416 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/jetway/nf81-t56n-lf/cmos.layout +++ b/src/mainboard/jetway/nf81-t56n-lf/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/kontron/986lcd-m/cmos.layout b/src/mainboard/kontron/986lcd-m/cmos.layout index 05ddf368fe..282c603fb8 100644 --- a/src/mainboard/kontron/986lcd-m/cmos.layout +++ b/src/mainboard/kontron/986lcd-m/cmos.layout @@ -4,125 +4,125 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 12 gfx_uma_size +411 3 e 12 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 11 cmos_defaults_loaded +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 11 cmos_defaults_loaded # coreboot config options: mainboard specific options -948 2 e 8 cpufan_cruise_control -950 2 e 8 sysfan_cruise_control -952 4 e 9 cpufan_speed -#956 4 e 10 cpufan_temperature -960 4 e 9 sysfan_speed -#964 4 e 10 sysfan_temperature +948 2 e 8 cpufan_cruise_control +950 2 e 8 sysfan_cruise_control +952 4 e 9 cpufan_speed +#956 4 e 10 cpufan_temperature +960 4 e 9 sysfan_speed +#964 4 e 10 sysfan_temperature -968 1 e 2 ethernet1 -969 1 e 2 ethernet2 -970 1 e 2 ethernet3 -971 1 e 1 lpt +968 1 e 2 ethernet1 +969 1 e 2 ethernet2 +970 1 e 2 ethernet3 +971 1 e 1 lpt # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep # Fan Cruise Control -8 0 Disabled -8 1 Speed -#8 2 Thermal +8 0 Disabled +8 1 Speed +#8 2 Thermal # Fan Speed (Rotations per Minute) -9 0 5625 -9 1 5192 -9 2 4753 -9 3 4326 -9 4 3924 -9 5 3552 -9 6 3214 -9 7 2909 -9 8 2636 -9 9 2393 -9 10 2177 -9 11 1985 -9 12 1814 -9 13 1662 -9 14 1527 -9 15 1406 +9 0 5625 +9 1 5192 +9 2 4753 +9 3 4326 +9 4 3924 +9 5 3552 +9 6 3214 +9 7 2909 +9 8 2636 +9 9 2393 +9 10 2177 +9 11 1985 +9 12 1814 +9 13 1662 +9 14 1527 +9 15 1406 # # Temperature (°C/°F) -#10 0 30/86 -#10 1 33/91 -#10 2 36/96 -#10 3 39/102 -#10 4 42/107 -#10 5 45/113 -#10 6 48/118 -#10 7 51/123 -#10 8 54/129 -#10 9 57/134 -#10 10 60/140 -#10 11 63/145 -#10 12 66/150 -#10 13 69/156 -#10 14 72/161 -#10 15 75/167 -11 0 No -11 1 Yes -12 0 1M -12 1 4M -12 2 8M -12 3 16M -12 4 32M -12 5 48M -12 6 64M +#10 0 30/86 +#10 1 33/91 +#10 2 36/96 +#10 3 39/102 +#10 4 42/107 +#10 5 45/113 +#10 6 48/118 +#10 7 51/123 +#10 8 54/129 +#10 9 57/134 +#10 10 60/140 +#10 11 63/145 +#10 12 66/150 +#10 13 69/156 +#10 14 72/161 +#10 15 75/167 +11 0 No +11 1 Yes +12 0 1M +12 1 4M +12 2 8M +12 3 16M +12 4 32M +12 5 48M +12 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/bsl6/cmos.layout b/src/mainboard/kontron/bsl6/cmos.layout index e4bd05c43c..2ace8ae00f 100644 --- a/src/mainboard/kontron/bsl6/cmos.layout +++ b/src/mainboard/kontron/bsl6/cmos.layout @@ -3,55 +3,55 @@ # ----------------------------------------------------------------- entries -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # coreboot config options: console -395 4 e 3 debug_level +395 4 e 3 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading +400 1 e 2 hyper_threading # coreboot config options: pch -408 2 e 4 power_on_after_fail +408 2 e 4 power_on_after_fail # coreboot config options: mainboard -440 1 e 2 ethernet1 -441 1 e 2 ethernet2 -442 1 e 2 ethernet3 +440 1 e 2 ethernet1 +441 1 e 2 ethernet2 +442 1 e 2 ethernet3 # payload config options -512 256 s 0 boot_devices -768 8 h 0 boot_default -776 1 e 1 cmos_defaults_loaded +512 256 s 0 boot_devices +768 8 h 0 boot_default +776 1 e 1 cmos_defaults_loaded # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 No -1 1 Yes -2 0 Disable -2 1 Enable -3 1 Emergency -3 2 Alert -3 3 Critical -3 4 Error -3 5 Warning -3 6 Notice -3 7 Info -3 8 Debug -3 9 Spew -4 0 Disable -4 1 Enable -4 2 Keep +#ID value text +1 0 No +1 1 Yes +2 0 Disable +2 1 Enable +3 1 Emergency +3 2 Alert +3 3 Critical +3 4 Error +3 5 Warning +3 6 Notice +3 7 Info +3 8 Debug +3 9 Spew +4 0 Disable +4 1 Enable +4 2 Keep # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index d3ad3233c1..914ad6df6a 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -4,101 +4,101 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: cpu -400 1 e 2 hyper_threading -401 3 e 12 gfx_uma_size +400 1 e 2 hyper_threading +401 3 e 12 gfx_uma_size # coreboot config options: southbridge -407 1 e 1 nmi -408 2 e 7 power_on_after_fail -410 2 e 11 sata_mode +407 1 e 1 nmi +408 2 e 7 power_on_after_fail +410 2 e 11 sata_mode # coreboot config options: additional mainboard options -412 4 e 10 systemp_type -416 7 h 0 fan1_min -424 7 h 0 fan1_max -432 7 h 0 fan2_min -440 7 h 0 fan2_max +412 4 e 10 systemp_type +416 7 h 0 fan1_min +424 7 h 0 fan1_max +432 7 h 0 fan2_min +440 7 h 0 fan2_max # coreboot config options: bootloader -448 64 r 0 write_protected_by_bios -512 328 s 0 boot_devices -840 8 h 0 boot_default -848 1 e 9 cmos_defaults_loaded -849 1 e 2 ethernet1 -850 1 e 2 ethernet2 +448 64 r 0 write_protected_by_bios +512 328 s 0 boot_devices +840 8 h 0 boot_default +848 1 e 9 cmos_defaults_loaded +849 1 e 2 ethernet1 +850 1 e 2 ethernet2 # coreboot config options: mainboard specific options -856 2 e 8 fan1_mode -858 2 r 0 fan1_reserved -860 2 e 8 fan2_mode -862 2 r 0 fan2_reserved -864 16 h 0 fan1_target -880 16 h 0 fan2_target +856 2 e 8 fan1_mode +858 2 r 0 fan1_reserved +860 2 e 8 fan2_mode +862 2 r 0 fan2_reserved +864 16 h 0 fan1_target +880 16 h 0 fan2_target # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Auto -8 1 PWM -8 2 Speed -8 3 Thermal -9 0 No -9 1 Yes -10 0 None -10 1 AMD -10 2 LM75@90 -10 3 GPIO16 -10 4 LM75@9e -11 0 AHCI -11 1 Compatible -11 2 Legacy -12 0 32M -12 1 64M -12 2 96M -12 3 128M -12 4 160M -12 5 192M -12 6 224M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Auto +8 1 PWM +8 2 Speed +8 3 Thermal +9 0 No +9 1 Yes +10 0 None +10 1 AMD +10 2 LM75@90 +10 3 GPIO16 +10 4 LM75@9e +11 0 AHCI +11 1 Compatible +11 2 Legacy +12 0 32M +12 1 64M +12 2 96M +12 3 128M +12 4 160M +12 5 192M +12 6 224M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/g505s/cmos.layout b/src/mainboard/lenovo/g505s/cmos.layout index d2e1f28bab..04ffe7e52b 100644 --- a/src/mainboard/lenovo/g505s/cmos.layout +++ b/src/mainboard/lenovo/g505s/cmos.layout @@ -5,50 +5,50 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -#400 8 r 8 reserved for century byte -408 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +#400 8 r 8 reserved for century byte +408 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/lenovo/l520/cmos.layout b/src/mainboard/lenovo/l520/cmos.layout index 0d5968c394..e96915d2d1 100644 --- a/src/mainboard/lenovo/l520/cmos.layout +++ b/src/mainboard/lenovo/l520/cmos.layout @@ -4,91 +4,91 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -440 8 h 0 volume +432 3 e 11 gfx_uma_size +440 8 h 0 volume # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index f5cf15c4f0..24038a7f87 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -4,94 +4,94 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 10 sata_mode -409 2 e 7 power_on_after_fail +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 9 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 wlan -415 1 e 1 trackpoint -416 8 h 0 volume -424 1 e 1 fn_ctrl_swap -425 1 e 1 sticky_fn -426 1 e 1 power_management_beeps -427 1 e 1 low_battery_beep -428 1 e 1 uwb +411 1 e 9 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 wlan +415 1 e 1 trackpoint +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb # coreboot config options: bootloader -432 512 s 0 boot_devices -944 8 h 0 boot_default +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -952 2 e 12 hybrid_graphics_mode -954 4 e 11 gfx_uma_size +952 2 e 12 hybrid_graphics_mode +954 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 128 r 0 read_training_results +1024 128 r 0 read_training_results # VBOOT -1152 128 r 0 vbnv +1152 128 r 0 vbnv # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -10 0 AHCI -10 1 Compatible -11 4 32M -11 5 48M -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +10 0 AHCI +10 1 Compatible +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t410/cmos.layout b/src/mainboard/lenovo/t410/cmos.layout index 0ca4d7af0e..71d65cee8d 100644 --- a/src/mainboard/lenovo/t410/cmos.layout +++ b/src/mainboard/lenovo/t410/cmos.layout @@ -4,85 +4,85 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -420 1 e 1 low_battery_beep -421 1 e 9 sata_mode -422 2 e 11 usb_always_on +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +420 1 e 1 low_battery_beep +421 1 e 9 sata_mode +422 2 e 11 usb_always_on # coreboot config options: northbridge -424 3 e 10 gfx_uma_size -432 2 e 12 hybrid_graphics_mode +424 3 e 10 gfx_uma_size +432 2 e 12 hybrid_graphics_mode # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 32M -10 1 48M -10 2 64M -10 3 128M -10 5 96M -10 6 160M -11 0 Disable -11 1 AC and battery -11 2 AC only -12 0 Integrated Only -12 1 Discrete Only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M +11 0 Disable +11 1 AC and battery +11 2 AC only +12 0 Integrated Only +12 1 Discrete Only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420/cmos.layout b/src/mainboard/lenovo/t420/cmos.layout index 2f67013450..e1d15be56b 100644 --- a/src/mainboard/lenovo/t420/cmos.layout +++ b/src/mainboard/lenovo/t420/cmos.layout @@ -4,99 +4,99 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 13 usb_always_on +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +421 1 e 9 sata_mode +422 2 e 13 usb_always_on # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t420s/cmos.layout b/src/mainboard/lenovo/t420s/cmos.layout index 2f67013450..e1d15be56b 100644 --- a/src/mainboard/lenovo/t420s/cmos.layout +++ b/src/mainboard/lenovo/t420s/cmos.layout @@ -4,99 +4,99 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 13 usb_always_on +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +421 1 e 9 sata_mode +422 2 e 13 usb_always_on # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t430/cmos.layout b/src/mainboard/lenovo/t430/cmos.layout index e3d3c92ba3..dd51c36854 100644 --- a/src/mainboard/lenovo/t430/cmos.layout +++ b/src/mainboard/lenovo/t430/cmos.layout @@ -4,98 +4,98 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 13 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 13 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -440 8 h 0 volume +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t430s/cmos.layout b/src/mainboard/lenovo/t430s/cmos.layout index 0b7230341a..02c1ea78df 100644 --- a/src/mainboard/lenovo/t430s/cmos.layout +++ b/src/mainboard/lenovo/t430s/cmos.layout @@ -4,96 +4,96 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight -424 1 e 1 f1_to_f12_as_primary +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight +424 1 e 1 f1_to_f12_as_primary # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 1 e 1 enable_dual_graphics -440 8 h 0 volume +432 3 e 11 gfx_uma_size +435 1 e 1 enable_dual_graphics +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t440p/cmos.layout b/src/mainboard/lenovo/t440p/cmos.layout index 4287eead03..464d24277b 100644 --- a/src/mainboard/lenovo/t440p/cmos.layout +++ b/src/mainboard/lenovo/t440p/cmos.layout @@ -4,78 +4,78 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 13 usb_always_on -422 2 e 10 backlight -424 1 e 1 f1_to_f12_as_primary +411 1 e 8 first_battery +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 13 usb_always_on +422 2 e 10 backlight +424 1 e 1 f1_to_f12_as_primary # coreboot config options: northbridge -435 1 e 1 enable_dual_graphics -440 8 h 0 volume +435 1 e 1 enable_dual_graphics +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible # Haswell ThinkPads have no Thinklight -#10 0 Both -10 1 Keyboard -#10 2 Thinklight only -10 3 None -13 0 Disable -13 1 AC and battery -13 2 AC only +#10 0 Both +10 1 Keyboard +#10 2 Thinklight only +10 3 None +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t520/cmos.layout b/src/mainboard/lenovo/t520/cmos.layout index 4f657fdc3f..dd51c36854 100644 --- a/src/mainboard/lenovo/t520/cmos.layout +++ b/src/mainboard/lenovo/t520/cmos.layout @@ -4,98 +4,98 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 13 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 13 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode -440 8 h 0 volume +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t530/cmos.layout b/src/mainboard/lenovo/t530/cmos.layout index a3b0f0637c..6cd8ac066b 100644 --- a/src/mainboard/lenovo/t530/cmos.layout +++ b/src/mainboard/lenovo/t530/cmos.layout @@ -4,99 +4,99 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 13 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 13 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -435 2 e 12 hybrid_graphics_mode +432 3 e 11 gfx_uma_size +435 2 e 12 hybrid_graphics_mode -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Integrated Only -12 1 Discrete Only -12 2 Dual Graphics -13 0 Disable -13 1 AC and battery -13 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Integrated Only +12 1 Discrete Only +12 2 Dual Graphics +13 0 Disable +13 1 AC and battery +13 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/t60/cmos.layout b/src/mainboard/lenovo/t60/cmos.layout index 62f5dbab03..2af6365f6f 100644 --- a/src/mainboard/lenovo/t60/cmos.layout +++ b/src/mainboard/lenovo/t60/cmos.layout @@ -4,90 +4,90 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt # coreboot config options: cpu # coreboot config options: ec -948 1 e 1 touchpad -949 1 e 1 bluetooth -950 1 e 1 wwan -951 1 e 1 wlan -952 8 h 0 volume -960 1 e 9 first_battery -961 1 e 1 trackpoint -963 1 e 1 sticky_fn -964 1 e 1 power_management_beeps -965 1 e 1 low_battery_beep +948 1 e 1 touchpad +949 1 e 1 bluetooth +950 1 e 1 wwan +951 1 e 1 wlan +952 8 h 0 volume +960 1 e 9 first_battery +961 1 e 1 trackpoint +963 1 e 1 sticky_fn +964 1 e 1 power_management_beeps +965 1 e 1 low_battery_beep # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout index cbf83229c9..11a078e35c 100644 --- a/src/mainboard/lenovo/thinkcentre_a58/cmos.layout +++ b/src/mainboard/lenovo/thinkcentre_a58/cmos.layout @@ -4,59 +4,59 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: cpu # coreboot config options: northbridge -432 4 e 11 gfx_uma_size +432 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 1 Emergency -6 2 Alert -6 3 Critical -6 4 Error -6 5 Warning -6 6 Notice -6 7 Info -6 8 Debug -6 9 Spew -7 0 Disable -7 1 Enable -7 2 Keep -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 1 Emergency +6 2 Alert +6 3 Critical +6 4 Error +6 5 Warning +6 6 Notice +6 7 Info +6 8 Debug +6 9 Spew +7 0 Disable +7 1 Enable +7 2 Keep +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x131e/cmos.layout b/src/mainboard/lenovo/x131e/cmos.layout index 2b6253cde0..b9da70dd08 100644 --- a/src/mainboard/lenovo/x131e/cmos.layout +++ b/src/mainboard/lenovo/x131e/cmos.layout @@ -4,87 +4,87 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 8 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 8 sata_mode # coreboot config options: EC -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 AHCI -8 1 Compatible -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 AHCI +8 1 Compatible +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout index e2abae6859..90a08b081a 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout +++ b/src/mainboard/lenovo/x1_carbon_gen1/cmos.layout @@ -4,95 +4,95 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index e300bdf5e8..afd5461af5 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -4,90 +4,90 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 10 sata_mode -409 2 e 7 power_on_after_fail +408 1 e 10 sata_mode +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 9 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 wlan -415 1 e 1 trackpoint -416 8 h 0 volume -424 1 e 1 fn_ctrl_swap -425 1 e 1 sticky_fn -426 1 e 1 power_management_beeps -427 1 e 1 low_battery_beep -428 1 e 1 uwb +411 1 e 9 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 wlan +415 1 e 1 trackpoint +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb # coreboot config options: bootloader -432 512 s 0 boot_devices -944 8 h 0 boot_default +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -952 4 e 11 gfx_uma_size +952 4 e 11 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 128 r 0 read_training_results +1024 128 r 0 read_training_results # VBOOT -1152 128 r 0 vbnv +1152 128 r 0 vbnv # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -10 0 AHCI -10 1 Compatible -11 4 32M -11 5 48M -11 6 64M -11 7 128M -11 8 256M -11 9 96M -11 10 160M -11 11 224M -11 12 352M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +10 0 AHCI +10 1 Compatible +11 4 32M +11 5 48M +11 6 64M +11 7 128M +11 8 256M +11 9 96M +11 10 160M +11 11 224M +11 12 352M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x201/cmos.layout b/src/mainboard/lenovo/x201/cmos.layout index a8c1d7969a..4ca1ade9b4 100644 --- a/src/mainboard/lenovo/x201/cmos.layout +++ b/src/mainboard/lenovo/x201/cmos.layout @@ -4,83 +4,83 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -420 1 e 1 low_battery_beep -421 1 e 9 sata_mode -422 2 e 11 usb_always_on +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +420 1 e 1 low_battery_beep +421 1 e 9 sata_mode +422 2 e 11 usb_always_on # coreboot config options: northbridge -424 3 e 10 gfx_uma_size -432 8 h 0 volume +424 3 e 10 gfx_uma_size +432 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 32M -10 1 48M -10 2 64M -10 3 128M -10 5 96M -10 6 160M -11 0 Disable -11 1 AC and battery -11 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M +11 0 Disable +11 1 AC and battery +11 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x220/cmos.layout b/src/mainboard/lenovo/x220/cmos.layout index ec4cbcbe3e..f152b2982a 100644 --- a/src/mainboard/lenovo/x220/cmos.layout +++ b/src/mainboard/lenovo/x220/cmos.layout @@ -4,94 +4,94 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 1 e 1 power_management_beeps -421 1 e 9 sata_mode -422 2 e 12 usb_always_on +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 1 e 1 power_management_beeps +421 1 e 9 sata_mode +422 2 e 12 usb_always_on # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size -440 8 h 0 volume +432 3 e 11 gfx_uma_size +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x230/cmos.layout b/src/mainboard/lenovo/x230/cmos.layout index 30845d2db8..89891bf0b0 100644 --- a/src/mainboard/lenovo/x230/cmos.layout +++ b/src/mainboard/lenovo/x230/cmos.layout @@ -4,96 +4,96 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail +408 1 e 1 nmi +409 2 e 7 power_on_after_fail # coreboot config options: EC -411 1 e 8 first_battery -412 1 e 1 bluetooth -413 1 e 1 wwan -414 1 e 1 touchpad -415 1 e 1 wlan -416 1 e 1 trackpoint -417 1 e 1 fn_ctrl_swap -418 1 e 1 sticky_fn -419 2 e 12 usb_always_on -421 1 e 9 sata_mode -422 2 e 10 backlight -424 1 e 1 f1_to_f12_as_primary +411 1 e 8 first_battery +412 1 e 1 bluetooth +413 1 e 1 wwan +414 1 e 1 touchpad +415 1 e 1 wlan +416 1 e 1 trackpoint +417 1 e 1 fn_ctrl_swap +418 1 e 1 sticky_fn +419 2 e 12 usb_always_on +421 1 e 9 sata_mode +422 2 e 10 backlight +424 1 e 1 f1_to_f12_as_primary # coreboot config options: cpu # coreboot config options: northbridge -432 3 e 11 gfx_uma_size +432 3 e 11 gfx_uma_size -440 8 h 0 volume +440 8 h 0 volume # VBOOT -448 128 r 0 vbnv +448 128 r 0 vbnv # SandyBridge MRC Scrambler Seed values -896 32 r 0 mrc_scrambler_seed -928 32 r 0 mrc_scrambler_seed_s3 -960 16 r 0 mrc_scrambler_seed_chk +896 32 r 0 mrc_scrambler_seed +928 32 r 0 mrc_scrambler_seed_s3 +960 16 r 0 mrc_scrambler_seed_chk # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 Both -10 1 Keyboard only -10 2 Thinklight only -10 3 None -11 0 32M -11 1 64M -11 2 96M -11 3 128M -11 4 160M -11 5 192M -11 6 224M -12 0 Disable -12 1 AC and battery -12 2 AC only +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 Both +10 1 Keyboard only +10 2 Thinklight only +10 3 None +11 0 32M +11 1 64M +11 2 96M +11 3 128M +11 4 160M +11 5 192M +11 6 224M +12 0 Disable +12 1 AC and battery +12 2 AC only # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lenovo/x60/cmos.layout b/src/mainboard/lenovo/x60/cmos.layout index dcddc69cd2..61ab465694 100644 --- a/src/mainboard/lenovo/x60/cmos.layout +++ b/src/mainboard/lenovo/x60/cmos.layout @@ -4,91 +4,91 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level -#400 8 r 0 reserved for century byte +#400 8 r 0 reserved for century byte # coreboot config options: southbridge -408 1 e 1 nmi -#409 2 e 7 power_on_after_fail +408 1 e 1 nmi +#409 2 e 7 power_on_after_fail # coreboot config options: northbridge -411 3 e 11 gfx_uma_size +411 3 e 11 gfx_uma_size # coreboot config options: bootloader -416 512 s 0 boot_devices -928 8 h 0 boot_default -936 1 e 8 cmos_defaults_loaded -937 1 e 1 lpt +416 512 s 0 boot_devices +928 8 h 0 boot_default +936 1 e 8 cmos_defaults_loaded +937 1 e 1 lpt # coreboot config options: cpu # coreboot config options: ec -949 1 e 9 first_battery -950 1 e 1 bluetooth -951 1 e 1 wwan -952 1 e 1 wlan -953 1 e 1 trackpoint -955 1 e 1 sticky_fn -956 1 e 1 power_management_beeps -959 1 e 1 low_battery_beep -960 8 h 0 volume -968 8 h 0 tft_brightness +949 1 e 9 first_battery +950 1 e 1 bluetooth +951 1 e 1 wwan +952 1 e 1 wlan +953 1 e 1 trackpoint +955 1 e 1 sticky_fn +956 1 e 1 power_management_beeps +959 1 e 1 low_battery_beep +960 8 h 0 volume +968 8 h 0 tft_brightness # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # RAM initialization internal data -1024 8 r 0 C0WL0REOST -1032 8 r 0 C1WL0REOST -1040 8 r 0 RCVENMT -1048 4 r 0 C0DRT1 -1052 4 r 0 C1DRT1 +1024 8 r 0 C0WL0REOST +1032 8 r 0 C1WL0REOST +1040 8 r 0 RCVENMT +1048 4 r 0 C0DRT1 +1052 4 r 0 C1DRT1 -1056 128 r 0 vbnv +1056 128 r 0 vbnv # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 No -8 1 Yes -9 0 Secondary -9 1 Primary -11 0 1M -11 1 4M -11 2 8M -11 3 16M -11 4 32M -11 5 48M -11 6 64M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 No +8 1 Yes +9 0 Secondary +9 1 Primary +11 0 1M +11 1 4M +11 2 8M +11 3 16M +11 4 32M +11 5 48M +11 6 64M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/lippert/frontrunner-af/cmos.layout b/src/mainboard/lippert/frontrunner-af/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/lippert/frontrunner-af/cmos.layout +++ b/src/mainboard/lippert/frontrunner-af/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/msi/ms7721/cmos.layout b/src/mainboard/msi/ms7721/cmos.layout index 18bac8ee34..b076f0a776 100644 --- a/src/mainboard/msi/ms7721/cmos.layout +++ b/src/mainboard/msi/ms7721/cmos.layout @@ -5,49 +5,49 @@ entries -0 384 r 0 reserved_memory -384 1 e 4 boot_option -388 4 h 0 reboot_counter -395 1 e 1 hw_scrubber -396 1 e 1 interleave_chip_selects -397 2 e 8 max_mem_clock -399 1 e 2 multi_core -400 1 e 1 power_on_after_fail -412 4 e 6 debug_level -440 4 e 9 slow_cpu -444 1 e 1 nmi -445 1 e 1 iommu -456 1 e 1 ECC_memory -728 256 h 0 user_data -984 16 h 0 check_sum +0 384 r 0 reserved_memory +384 1 e 4 boot_option +388 4 h 0 reboot_counter +395 1 e 1 hw_scrubber +396 1 e 1 interleave_chip_selects +397 2 e 8 max_mem_clock +399 1 e 2 multi_core +400 1 e 1 power_on_after_fail +412 4 e 6 debug_level +440 4 e 9 slow_cpu +444 1 e 1 nmi +445 1 e 1 iommu +456 1 e 1 ECC_memory +728 256 h 0 user_data +984 16 h 0 check_sum # Reserve the extended AMD configuration registers -1000 24 r 0 amd_reserved +1000 24 r 0 amd_reserved enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -8 0 400Mhz -8 1 333Mhz -8 2 266Mhz -8 3 200Mhz -9 0 off -9 1 87.5% -9 2 75.0% -9 3 62.5% -9 4 50.0% -9 5 37.5% -9 6 25.0% -9 7 12.5% +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +8 0 400Mhz +8 1 333Mhz +8 2 266Mhz +8 3 200Mhz +9 0 off +9 1 87.5% +9 2 75.0% +9 3 62.5% +9 4 50.0% +9 5 37.5% +9 6 25.0% +9 7 12.5% checksums diff --git a/src/mainboard/packardbell/ms2290/cmos.layout b/src/mainboard/packardbell/ms2290/cmos.layout index 809f913612..aec434d55d 100644 --- a/src/mainboard/packardbell/ms2290/cmos.layout +++ b/src/mainboard/packardbell/ms2290/cmos.layout @@ -4,61 +4,61 @@ entries # ----------------------------------------------------------------- -0 120 r 0 reserved_memory +0 120 r 0 reserved_memory # ----------------------------------------------------------------- # RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter +384 1 e 4 boot_option +388 4 h 0 reboot_counter # ----------------------------------------------------------------- # coreboot config options: console -395 4 e 6 debug_level +395 4 e 6 debug_level # coreboot config options: southbridge -408 1 e 1 nmi -409 2 e 7 power_on_after_fail -411 1 e 9 sata_mode +408 1 e 1 nmi +409 2 e 7 power_on_after_fail +411 1 e 9 sata_mode # coreboot config options: northbridge -424 3 e 10 gfx_uma_size +424 3 e 10 gfx_uma_size # coreboot config options: check sums -984 16 h 0 check_sum +984 16 h 0 check_sum # ----------------------------------------------------------------- enumerations -#ID value text -1 0 Disable -1 1 Enable -2 0 Enable -2 1 Disable -4 0 Fallback -4 1 Normal -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew -7 0 Disable -7 1 Enable -7 2 Keep -8 0 Secondary -8 1 Primary -9 0 AHCI -9 1 Compatible -10 0 32M -10 1 48M -10 2 64M -10 3 128M -10 5 96M -10 6 160M +#ID value text +1 0 Disable +1 1 Enable +2 0 Enable +2 1 Disable +4 0 Fallback +4 1 Normal +6 0 Emergency +6 1 Alert +6 2 Critical +6 3 Error +6 4 Warning +6 5 Notice +6 6 Info +6 7 Debug +6 8 Spew +7 0 Disable +7 1 Enable +7 2 Keep +8 0 Secondary +8 1 Primary +9 0 AHCI +9 1 Compatible +10 0 32M +10 1 48M +10 2 64M +10 3 128M +10 5 96M +10 6 160M # ----------------------------------------------------------------- checksums diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout index a1165b118b..dd3cd91f30 100644 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -1,34 +1,34 @@ entries # -0 384 r 0 reserved_memory -384 4 r 0 reboot_bits +0 384 r 0 reserved_memory +384 4 r 0 reboot_bits # leave 3 bits to make checksummed area start byte-aligned -392 1 e 2 boot_option -393 1 e 1 multi_core -400 4 e 4 debug_level +392 1 e 2 boot_option +393 1 e 1 multi_core +400 4 e 4 debug_level # leave 7 bits to make checksummed area end byte-aligned -408 16 h 0 check_sum +408 16 h 0 check_sum enumerations #