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coreboot: common stage cache

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Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.

Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Aaron Durbin
2015-03-06 23:17:33 -06:00
parent cac5050623
commit bd74a4b2d2
20 changed files with 337 additions and 367 deletions
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3
src/include/cbfs.h
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@@ -2,7 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright (C) 2008 Jordan Crouse <jordan@cosmicpenguin.net>
* Copyright (C) 2013 The Chromium OS Authors. All rights reserved.
* Copyright (C) 2013-2015 Google, Inc.
*
* This file is dual-licensed. You can choose between:
* - The GNU GPL, version 2, as published by the Free Software Foundation
@@ -90,4 +90,3 @@ void cbfs_set_header_offset(size_t offset);
static inline void cbfs_set_header_offset(size_t offset) {}
#endif
#endif