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coreboot: common stage cache

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Many chipsets were using a stage cache for reference code
or when using a relocatable ramstage. Provide a common
API for the chipsets to use while reducing code duplication.

Change-Id: Ia36efa169fe6bd8a3dbe07bf57a9729c7edbdd46
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/8625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Aaron Durbin
2015-03-06 23:17:33 -06:00
parent cac5050623
commit bd74a4b2d2
20 changed files with 337 additions and 367 deletions
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14
src/include/program_loading.h
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@ -123,18 +123,8 @@ void run_romstage(void);
/* Run ramstage from romstage. */
void run_ramstage(void);
struct romstage_handoff;
#if IS_ENABLED(CONFIG_RELOCATABLE_RAMSTAGE)
/* Cache the loaded ramstage described by prog. */
void cache_loaded_ramstage(struct romstage_handoff *, struct prog *p);
/* Load ramstage from cache filling in struct prog. */
void load_cached_ramstage(struct romstage_handoff *h, struct prog *p);
#else
static inline void cache_loaded_ramstage(struct romstage_handoff *h,
struct prog *p) {}
static inline void load_cached_ramstage(struct romstage_handoff *h,
struct prog *p) {}
#endif
/* Called when the stage cache couldn't load ramstage on resume. */
void ramstage_cache_invalid(void);
/***********************
* PAYLOAD LOADING *