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sb/intel/bd82x6x: Use helper for PCIe hotplug

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Introduce pci_is_hotplugable is helper to find hotpluggable
PCIe devices.

Test: PCI express slot is still marked as the only hotpluggable
      PCIe root port.

Change-Id: I25aae540ff2ffa3ec5b93ed9caa838b4e50048d2
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/78227
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Jan Samek <jan.samek@siemens.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Patrick Rudolph
2023-10-02 07:18:18 +02:00
committed by Felix Held
parent 91c38146a4
commit bd7a7fd4b2
1 changed files with 9 additions and 5 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/southbridge/intel/bd82x6x/pcie.c
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@@ -32,6 +32,13 @@ static const char *pch_pcie_acpi_name(const struct device *dev)
return NULL; return NULL;
} }
static bool pci_is_hotplugable(struct device *dev)
{
struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
return config && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)];
}
static void pch_pcie_pm_early(struct device *dev) static void pch_pcie_pm_early(struct device *dev)
{ {
u16 link_width_p0, link_width_p4; u16 link_width_p0, link_width_p4;
@@ -179,7 +186,6 @@ static void pch_pcie_pm_late(struct device *dev)
static void pci_init(struct device *dev) static void pci_init(struct device *dev)
{ {
u16 reg16; u16 reg16;
struct southbridge_intel_bd82x6x_config *config = dev->chip_info;
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
@@ -202,7 +208,7 @@ static void pci_init(struct device *dev)
pci_write_config16(dev, 0x1e, reg16); pci_write_config16(dev, 0x1e, reg16);
/* Enable expresscard hotplug events. */ /* Enable expresscard hotplug events. */
if (config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) { if (pci_is_hotplugable(dev)) {
pci_or_config32(dev, 0xd8, 1 << 30); pci_or_config32(dev, 0xd8, 1 << 30);
pci_write_config16(dev, 0x42, 0x142); pci_write_config16(dev, 0x42, 0x142);
} }
@@ -216,9 +222,7 @@ static void pch_pcie_enable(struct device *dev)
static void pch_pciexp_scan_bridge(struct device *dev) static void pch_pciexp_scan_bridge(struct device *dev)
{ {
struct southbridge_intel_bd82x6x_config *config = dev->chip_info; if (CONFIG(PCIEXP_HOTPLUG) && pci_is_hotplugable(dev)) {
if (CONFIG(PCIEXP_HOTPLUG) && config->pcie_hotplug_map[PCI_FUNC(dev->path.pci.devfn)]) {
pciexp_hotplug_scan_bridge(dev); pciexp_hotplug_scan_bridge(dev);
} else { } else {
/* Normal PCIe Scan */ /* Normal PCIe Scan */