sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

util: Fix typo on plural form of index

Browse Source 
Change-Id: Idc165f8eafacf3130a29b701bc3610c1a67f69d5
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32855
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jacob Garber <jgarber1@ualberta.ca>
This commit is contained in:
Elyes HAOUAS
2019-05-18 06:57:07 +02:00
committed by Patrick Georgi
parent cc8665eacc
commit bd96a84300
7 changed files with 35 additions and 35 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
util/romcc/tests/linux_test5.c
View File

@ -156,7 +156,7 @@ static const struct mem_param *spd_set_memclk(void)
unsigned device;
uint32_t value;
static const int latency_indicies[] = { 26, 23, 9 };
static const int latency_indices[] = { 26, 23, 9 };
static const unsigned char min_cycle_times[] = {
[NBCAP_MEMCLK_200MHZ] = 0x50, /* 5ns */
[NBCAP_MEMCLK_166MHZ] = 0x60, /* 6ns */
@ -224,7 +224,7 @@ static const struct mem_param *spd_set_memclk(void)
continue;
}
debug('D');
value = smbus_read_byte(device, latency_indicies[index]);
value = smbus_read_byte(device, latency_indices[index]);
if (value < 0) continue;
debug('E');
@ -310,7 +310,7 @@ static const struct mem_param *spd_set_memclk(void)
}
/* Read the min_cycle_time for this latency */
value = smbus_read_byte(device, latency_indicies[index]);
value = smbus_read_byte(device, latency_indices[index]);
/* All is good if the selected clock speed
* is what I need or slower.