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soc/intel/cannonlake: Align cosmetics with Ice Lake

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By ironing out cosmetic differences between Cannon Lake and Ice Lake,
comparing actual code differences using a diff tool becomes simpler.

Tested with BUILD_TIMELESS=1, Prodrive Hermes remains identical.

Change-Id: I4d9f882f9f8af1245e937b0d47bc7e993547365f
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45778
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by:  Felix Singer <felixsinger@posteo.net>
This commit is contained in:
Angel Pons
2020-09-28 01:10:40 +02:00
committed by Nico Huber
parent 8c8b34996d
commit bda02b0f2b
4 changed files with 46 additions and 50 deletions
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57
src/soc/intel/cannonlake/cpu.c
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@@ -54,9 +54,10 @@ static void configure_isst(void)
static void configure_misc(void)
{
config_t *conf = config_of_soc();
msr_t msr;
config_t *conf = config_of_soc();
msr = rdmsr(IA32_MISC_ENABLE);
msr.lo |= (1 << 0); /* Fast String enable */
msr.lo |= (1 << 3); /* TM1/TM2/EMTTM enable */
@@ -105,6 +106,33 @@ static void configure_dca_cap(void)
}
}
/*
* The emulated ACPI timer allows replacing of the ACPI timer
* (PM1_TMR) to have no impart on the system.
*/
static void enable_pm_timer_emulation(void)
{
const struct soc_intel_cannonlake_config *config;
msr_t msr;
config = config_of_soc();
/* Enable PM timer emulation only if ACPI PM timer is disabled */
if (!config->PmTimerDisabled)
return;
/*
* The derived frequency is calculated as follows:
* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
* Back solve the multiplier so the 3.579545MHz ACPI timer
* frequency is used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);
}
static void set_energy_perf_bias(u8 policy)
{
msr_t msr;
@@ -155,33 +183,6 @@ static void configure_c_states(void)
wrmsr(MSR_C_STATE_LATENCY_CONTROL_5, msr);
}
/*
* The emulated ACPI timer allows replacing of the ACPI timer
* (PM1_TMR) to have no impart on the system.
*/
static void enable_pm_timer_emulation(void)
{
const struct soc_intel_cannonlake_config *config;
msr_t msr;
config = config_of_soc();
/* Enable PM timer emulation only if ACPI PM timer is disabled */
if (!config->PmTimerDisabled)
return;
/*
* The derived frequency is calculated as follows:
* (CTC_FREQ * msr[63:32]) >> 32 = target frequency.
* Back solve the multiplier so the 3.579545MHz ACPI timer
* frequency is used.
*/
msr.hi = (3579545ULL << 32) / CTC_FREQ;
/* Set PM1 timer IO port and enable */
msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) |
EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR);
wrmsr(MSR_EMULATE_PM_TIMER, msr);
}
/* All CPUs including BSP will run the following function. */
void soc_core_init(struct device *cpu)
{