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cpu/amd: Rename MCA status register

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Change the defined name of MCI_STATUS (i.e. MCi_STATUS) to reflect its
MC0_STATUS address.

Change-Id: I97d2631a186965bb8b18f544ed9648b3a71f5fb0
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/27922
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Marshall Dawson
2018-08-07 07:17:41 -06:00
committed by Martin Roth
parent b388c0e557
commit bddd157ea1
11 changed files with 14 additions and 14 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/cpu/amd/agesa/family12/model_12_init.c
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@@ -27,7 +27,7 @@
#include <cpu/amd/multicore.h> #include <cpu/amd/multicore.h>
#include <cpu/amd/amdfam12.h> #include <cpu/amd/amdfam12.h>
#define MCI_STATUS 0x401 #define MC0_STATUS 0x401
static void model_12_init(struct device *dev) static void model_12_init(struct device *dev)
{ {
@@ -55,7 +55,7 @@ static void model_12_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
} }
enable_cache(); enable_cache();

4
src/cpu/amd/agesa/family14/model_14_init.c
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@@ -28,7 +28,7 @@
#include <arch/acpi.h> #include <arch/acpi.h>
#include <northbridge/amd/agesa/agesa_helper.h> #include <northbridge/amd/agesa/agesa_helper.h>
#define MCI_STATUS 0x401 #define MC0_STATUS 0x401
static void model_14_init(struct device *dev) static void model_14_init(struct device *dev)
{ {
@@ -78,7 +78,7 @@ static void model_14_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) { for (i = 0; i < 6; i++) {
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
} }
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

2
src/cpu/amd/agesa/family15tn/model_15_init.c
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@@ -75,7 +75,7 @@ static void model_15_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) { for (i = 0; i < 6; i++) {
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
} }
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

2
src/cpu/amd/agesa/family16kb/model_16_init.c
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@@ -73,7 +73,7 @@ static void model_16_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) { for (i = 0; i < 6; i++) {
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
} }
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

4
src/cpu/amd/family_10h-family_15h/model_10xxx_init.c
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@@ -32,7 +32,7 @@
#include <cpu/amd/multicore.h> #include <cpu/amd/multicore.h>
#include <cpu/amd/msr.h> #include <cpu/amd/msr.h>
#define MCI_STATUS 0x401 #define MC0_STATUS 0x401
static inline uint8_t is_gt_rev_d(void) static inline uint8_t is_gt_rev_d(void)
{ {
@@ -112,7 +112,7 @@ static void model_10xxx_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 5; i++) { for (i = 0; i < 5; i++) {
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
} }
enable_cache(); enable_cache();

2
src/cpu/amd/pi/00630F01/model_15_init.c
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@@ -72,7 +72,7 @@ static void model_15_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) for (i = 0; i < 6; i++)
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */
setup_lapic(); setup_lapic();

2
src/cpu/amd/pi/00660F01/model_15_init.c
View File

@@ -84,7 +84,7 @@ static void model_15_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) for (i = 0; i < 6; i++)
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

2
src/cpu/amd/pi/00730F01/model_16_init.c
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@@ -69,7 +69,7 @@ static void model_16_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0; i < 6; i++) for (i = 0; i < 6; i++)
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
/* Enable the local CPU APICs */ /* Enable the local CPU APICs */

2
src/include/cpu/amd/amdfam15.h
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@@ -16,7 +16,7 @@
#ifndef CPU_AMD_FAM15_H #ifndef CPU_AMD_FAM15_H
#define CPU_AMD_FAM15_H #define CPU_AMD_FAM15_H
#define MCI_STATUS 0x00000401 #define MC0_STATUS 0x00000401
#define MSR_SMM_BASE 0xC0010111 #define MSR_SMM_BASE 0xC0010111
#define MSR_TSEG_BASE 0xC0010112 #define MSR_TSEG_BASE 0xC0010112
#define MSR_SMM_MASK 0xC0010113 #define MSR_SMM_MASK 0xC0010113

2
src/include/cpu/amd/amdfam16.h
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@@ -16,7 +16,7 @@
#ifndef CPU_AMD_FAM16_H #ifndef CPU_AMD_FAM16_H
#define CPU_AMD_FAM16_H #define CPU_AMD_FAM16_H
#define MCI_STATUS 0x00000401 #define MC0_STATUS 0x00000401
#define HWCR_MSR 0xC0010015 #define HWCR_MSR 0xC0010015
#define NB_CFG_MSR 0xC001001f #define NB_CFG_MSR 0xC001001f

2
src/soc/amd/stoneyridge/cpu.c
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@@ -126,7 +126,7 @@ static void model_15_init(struct device *dev)
msr.lo = 0; msr.lo = 0;
msr.hi = 0; msr.hi = 0;
for (i = 0 ; i < 6 ; i++) for (i = 0 ; i < 6 ; i++)
wrmsr(MCI_STATUS + (i * 4), msr); wrmsr(MC0_STATUS + (i * 4), msr);
setup_lapic(); setup_lapic();
} }