x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)

src/arch/x86/boot/mpspec.c

@@ -222,7 +222,7 @@ static void smp_write_bus(struct mp_config_table *mc,
  * APIC Flags:EN, Address
  */
 void smp_write_ioapic(struct mp_config_table *mc,
-	u8 id, u8 ver, u32 apicaddr)
+	u8 id, u8 ver, void *apicaddr)
 {
 	struct mpc_config_ioapic *mpc;
 	mpc = smp_next_mpc_entry(mc);

src/arch/x86/include/arch/ebda.h

@@ -23,9 +23,9 @@
 #define __ARCH_EBDA_H
 
 #define X86_BDA_SIZE		0x200
-#define X86_BDA_BASE		0x400
-#define X86_EBDA_SEGMENT	0x40e
-#define X86_EBDA_LOWMEM		0x413
+#define X86_BDA_BASE		(void *)0x400
+#define X86_EBDA_SEGMENT	(void *)0x40e
+#define X86_EBDA_LOWMEM		(void *)0x413
 
 #define DEFAULT_EBDA_LOWMEM	(1024 << 10)
 #define DEFAULT_EBDA_SEGMENT	0xF600

src/arch/x86/include/arch/io.h

@@ -142,32 +142,32 @@ static inline void insl(uint16_t port, void *addr, unsigned long count)
 		);
 }
 
-static inline __attribute__((always_inline)) uint8_t read8(unsigned long addr)
+static inline __attribute__((always_inline)) uint8_t read8(const volatile void *addr)
 {
 	return *((volatile uint8_t *)(addr));
 }
 
-static inline __attribute__((always_inline)) uint16_t read16(unsigned long addr)
+static inline __attribute__((always_inline)) uint16_t read16(const volatile void *addr)
 {
 	return *((volatile uint16_t *)(addr));
 }
 
-static inline __attribute__((always_inline)) uint32_t read32(unsigned long addr)
+static inline __attribute__((always_inline)) uint32_t read32(const volatile void *addr)
 {
 	return *((volatile uint32_t *)(addr));
 }
 
-static inline __attribute__((always_inline)) void write8(unsigned long addr, uint8_t value)
+static inline __attribute__((always_inline)) void write8(volatile void *addr, uint8_t value)
 {
 	*((volatile uint8_t *)(addr)) = value;
 }
 
-static inline __attribute__((always_inline)) void write16(unsigned long addr, uint16_t value)
+static inline __attribute__((always_inline)) void write16(volatile void *addr, uint16_t value)
 {
 	*((volatile uint16_t *)(addr)) = value;
 }
 
-static inline __attribute__((always_inline)) void write32(unsigned long addr, uint32_t value)
+static inline __attribute__((always_inline)) void write32(volatile void *addr, uint32_t value)
 {
 	*((volatile uint32_t *)(addr)) = value;
 }

src/arch/x86/include/arch/ioapic.h

@@ -21,6 +21,7 @@
 #define __I386_ARCH_IOAPIC_H
 
 #define IO_APIC_ADDR	0xfec00000
+#define VIO_APIC_VADDR	((u8 *)IO_APIC_ADDR)
 #define IO_APIC_INTERRUPTS 24
 
 #ifndef __ACPI__
@@ -42,11 +43,11 @@
 #define SMI		(2 << 8)
 #define INT		(1 << 8)
 
-u32 io_apic_read(u32 ioapic_base, u32 reg);
-void io_apic_write(u32 ioapic_base, u32 reg, u32 value);
-void set_ioapic_id(u32 ioapic_base, u8 ioapic_id);
-void setup_ioapic(u32 ioapic_base, u8 ioapic_id);
-void clear_ioapic(u32 ioapic_base);
+u32 io_apic_read(void *ioapic_base, u32 reg);
+void io_apic_write(void *ioapic_base, u32 reg, u32 value);
+void set_ioapic_id(void *ioapic_base, u8 ioapic_id);
+void setup_ioapic(void *ioapic_base, u8 ioapic_id);
+void clear_ioapic(void *ioapic_base);
 #endif
 
 #endif

src/arch/x86/include/arch/pci_mmio_cfg.h

@@ -28,48 +28,48 @@
 static inline __attribute__ ((always_inline))
 u8 pcie_read_config8(pci_devfn_t dev, unsigned int where)
 {
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
+	void *addr;
+	addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
 	return read8(addr);
 }
 
 static inline __attribute__ ((always_inline))
 u16 pcie_read_config16(pci_devfn_t dev, unsigned int where)
 {
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
+	void *addr;
+	addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
 	return read16(addr);
 }
 
 static inline __attribute__ ((always_inline))
 u32 pcie_read_config32(pci_devfn_t dev, unsigned int where)
 {
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
+	void *addr;
+	addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
 	return read32(addr);
 }
 
 static inline __attribute__ ((always_inline))
 void pcie_write_config8(pci_devfn_t dev, unsigned int where, u8 value)
 {
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | where;
+	void *addr;
+	addr = (void *)(DEFAULT_PCIEXBAR | dev | where);
 	write8(addr, value);
 }
 
 static inline __attribute__ ((always_inline))
 void pcie_write_config16(pci_devfn_t dev, unsigned int where, u16 value)
 {
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | (where & ~1);
+	void *addr;
+	addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~1));
 	write16(addr, value);
 }
 
 static inline __attribute__ ((always_inline))
 void pcie_write_config32(pci_devfn_t dev, unsigned int where, u32 value)
 {
-	unsigned long addr;
-	addr = DEFAULT_PCIEXBAR | dev | (where & ~3);
+	void *addr;
+	addr = (void *)(DEFAULT_PCIEXBAR | dev | (where & ~3));
 	write32(addr, value);
 }
 

src/arch/x86/include/arch/smp/mpspec.h

@@ -123,7 +123,7 @@ struct mpc_config_ioapic
 	u8 mpc_apicver;
 	u8 mpc_flags;
 #define MPC_APIC_USABLE		0x01
-	u32 mpc_apicaddr;
+	void *mpc_apicaddr;
 } __attribute__((packed));
 
 struct mpc_config_intsrc
@@ -260,7 +260,7 @@ void smp_write_processor(struct mp_config_table *mc,
 	u32 featureflag);
 void smp_write_processors(struct mp_config_table *mc);
 void smp_write_ioapic(struct mp_config_table *mc,
-	u8 id, u8 ver, u32 apicaddr);
+	u8 id, u8 ver, void *apicaddr);
 void smp_write_intsrc(struct mp_config_table *mc,
 	u8 irqtype, u16 irqflag, u8 srcbus, u8 srcbusirq,
 	u8 dstapic, u8 dstirq);

src/arch/x86/lib/ebda.c

@@ -42,7 +42,7 @@ void setup_ebda(u32 low_memory_size, u16 ebda_segment, u16 ebda_size)
 
 	/* Set up EBDA */
 	memset((void *)(ebda_segment << 4), 0, ebda_size);
-	write16((ebda_segment << 4), (ebda_size >> 10));
+	write16((void*)(ebda_segment << 4), (ebda_size >> 10));
 }
 
 void setup_default_ebda(void)

src/arch/x86/lib/ioapic.c

@@ -22,19 +22,19 @@
 #include <console/console.h>
 #include <cpu/x86/lapic.h>
 
-u32 io_apic_read(u32 ioapic_base, u32 reg)
+u32 io_apic_read(void *ioapic_base, u32 reg)
 {
 	write32(ioapic_base, reg);
 	return read32(ioapic_base + 0x10);
 }
 
-void io_apic_write(u32 ioapic_base, u32 reg, u32 value)
+void io_apic_write(void *ioapic_base, u32 reg, u32 value)
 {
 	write32(ioapic_base, reg);
 	write32(ioapic_base + 0x10, value);
 }
 
-static int ioapic_interrupt_count(int ioapic_base)
+static int ioapic_interrupt_count(void *ioapic_base)
 {
 	/* Read the available number of interrupts. */
 	int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
@@ -48,12 +48,12 @@ static int ioapic_interrupt_count(int ioapic_base)
 	return ioapic_interrupts;
 }
 
-void clear_ioapic(u32 ioapic_base)
+void clear_ioapic(void *ioapic_base)
 {
 	u32 low, high;
 	u32 i, ioapic_interrupts;
 
-	printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at 0x%08x\n", ioapic_base);
+	printk(BIOS_DEBUG, "IOAPIC: Clearing IOAPIC at %p\n", ioapic_base);
 
 	ioapic_interrupts = ioapic_interrupt_count(ioapic_base);
 
@@ -74,12 +74,12 @@ void clear_ioapic(u32 ioapic_base)
 	}
 }
 
-void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
+void set_ioapic_id(void *ioapic_base, u8 ioapic_id)
 {
 	u32 bsp_lapicid = lapicid();
 	int i;
 
-	printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%08x\n",
+	printk(BIOS_DEBUG, "IOAPIC: Initializing IOAPIC at 0x%p\n",
 	       ioapic_base);
 	printk(BIOS_DEBUG, "IOAPIC: Bootstrap Processor Local APIC = 0x%02x\n",
 	       bsp_lapicid);
@@ -99,7 +99,7 @@ void set_ioapic_id(u32 ioapic_base, u8 ioapic_id)
 
 }
 
-static void load_vectors(u32 ioapic_base)
+static void load_vectors(void *ioapic_base)
 {
 	u32 bsp_lapicid = lapicid();
 	u32 low, high;
@@ -146,7 +146,7 @@ static void load_vectors(u32 ioapic_base)
 	}
 }
 
-void setup_ioapic(u32 ioapic_base, u8 ioapic_id)
+void setup_ioapic(void *ioapic_base, u8 ioapic_id)
 {
 	set_ioapic_id(ioapic_base, ioapic_id);
 	load_vectors(ioapic_base);

src/arch/x86/lib/pci_ops_mmconf.c

@@ -9,46 +9,46 @@
  * Functions for accessing PCI configuration space with mmconf accesses
  */
 
-#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE)	\
-				(CONFIG_MMCONF_BASE_ADDRESS |\
-				(((SEGBUS) & 0xFFF) << 20) |\
-				(((DEVFN) & 0xFF) << 12) |\
-				((WHERE) & 0xFFF))
+#define PCI_MMIO_ADDR(SEGBUS, DEVFN, WHERE, MASK)	\
+				((void *)((CONFIG_MMCONF_BASE_ADDRESS |\
+					   (((SEGBUS) & 0xFFF) << 20) |\
+					   (((DEVFN) & 0xFF) << 12) |\
+					   ((WHERE) & 0xFFF)) & ~MASK))
 
 static uint8_t pci_mmconf_read_config8(struct bus *pbus, int bus, int devfn,
 				       int where)
 {
-	return (read8(PCI_MMIO_ADDR(bus, devfn, where)));
+	return read8(PCI_MMIO_ADDR(bus, devfn, where, 0));
 }
 
 static uint16_t pci_mmconf_read_config16(struct bus *pbus, int bus, int devfn,
 					 int where)
 {
-	return (read16(PCI_MMIO_ADDR(bus, devfn, where) & ~1));
+	return read16(PCI_MMIO_ADDR(bus, devfn, where, 1));
 }
 
 static uint32_t pci_mmconf_read_config32(struct bus *pbus, int bus, int devfn,
 					 int where)
 {
-	return (read32(PCI_MMIO_ADDR(bus, devfn, where) & ~3));
+	return read32(PCI_MMIO_ADDR(bus, devfn, where, 3));
 }
 
 static void pci_mmconf_write_config8(struct bus *pbus, int bus, int devfn,
 				     int where, uint8_t value)
 {
-	write8(PCI_MMIO_ADDR(bus, devfn, where), value);
+	write8(PCI_MMIO_ADDR(bus, devfn, where, 0), value);
 }
 
 static void pci_mmconf_write_config16(struct bus *pbus, int bus, int devfn,
 				      int where, uint16_t value)
 {
-	write16(PCI_MMIO_ADDR(bus, devfn, where) & ~1, value);
+	write16(PCI_MMIO_ADDR(bus, devfn, where, 1), value);
 }
 
 static void pci_mmconf_write_config32(struct bus *pbus, int bus, int devfn,
 				      int where, uint32_t value)
 {
-	write32(PCI_MMIO_ADDR(bus, devfn, where) & ~3, value);
+	write32(PCI_MMIO_ADDR(bus, devfn, where, 3), value);
 }
 
 const struct pci_bus_operations pci_ops_mmconf = {