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x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

Browse Source 
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
This commit is contained in:
Kevin Paul Herbert
2014-12-24 18:43:20 -08:00
committed by Alexandru Gagniuc
parent 4b10dec1a6
commit bde6d309df
354 changed files with 1900 additions and 1684 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/baytrail/acpi.c
View File

@@ -106,7 +106,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
static int acpi_sci_irq(void)
{
const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
int scis;
static int sci_irq;

22
src/soc/intel/baytrail/baytrail/gpio.h
View File

@@ -387,15 +387,15 @@ struct soc_gpio_config* mainboard_get_gpios(void);
#define PCU_SMB_DATA_PAD 90
#define SOC_DDI1_VDDEN_PAD 16
static inline unsigned int ncore_pconf0(int pad_num)
static inline u32 *ncore_pconf0(int pad_num)
{
return GPNCORE_PAD_BASE + pad_num * 16;
return (u32 *)(GPNCORE_PAD_BASE + pad_num * 16);
}
static inline void ncore_select_func(int pad, int func)
{
uint32_t reg;
uint32_t pconf0_addr = ncore_pconf0(pad);
u32 *pconf0_addr = ncore_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -403,20 +403,20 @@ static inline void ncore_select_func(int pad, int func)
write32(pconf0_addr, reg);
}
static inline unsigned int score_pconf0(int pad_num)
static inline u32 *score_pconf0(int pad_num)
{
return GPSCORE_PAD_BASE + pad_num * 16;
return (u32 *)(GPSCORE_PAD_BASE + pad_num * 16);
}
static inline unsigned int ssus_pconf0(int pad_num)
static inline u32 *ssus_pconf0(int pad_num)
{
return GPSSUS_PAD_BASE + pad_num * 16;
return (u32 *)(GPSSUS_PAD_BASE + pad_num * 16);
}
static inline void score_select_func(int pad, int func)
{
uint32_t reg;
uint32_t pconf0_addr = score_pconf0(pad);
uint32_t *pconf0_addr = score_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -427,7 +427,7 @@ static inline void score_select_func(int pad, int func)
static inline void ssus_select_func(int pad, int func)
{
uint32_t reg;
uint32_t pconf0_addr = ssus_pconf0(pad);
uint32_t *pconf0_addr = ssus_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -438,14 +438,14 @@ static inline void ssus_select_func(int pad, int func)
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
{
uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
static inline int ssus_get_gpio(int pad)
{
uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}

4
src/soc/intel/baytrail/gfx.c
View File

@@ -59,7 +59,7 @@ static void gfx_lock_pcbase(device_t dev)
pcbase += (gmsize-1) * wopcmsz - pcsize;
pcbase |= 1; /* Lock */
write32(res->base + 0x182120, pcbase);
write32((u32 *)(uintptr_t)(res->base + 0x182120), pcbase);
}
static const struct reg_script gfx_init_script[] = {
@@ -308,7 +308,7 @@ static void set_backlight_pwm(device_t dev, uint32_t bklt_reg, int req_hz)
divider = 25 * 1000 * 1000 / (16 * req_hz);
/* Do not set duty cycle (lower 16 bits). Just set the divider. */
write32(res->base + bklt_reg, divider << 16);
write32((u32 *)(uintptr_t)(res->base + bklt_reg), divider << 16);
}
static void gfx_panel_setup(device_t dev)

16
src/soc/intel/baytrail/gpio.c
View File

@@ -142,9 +142,9 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
reg, pad_conf0, config->pad_conf1, config->pad_val);
#endif
write32(reg + PAD_CONF0_REG, pad_conf0);
write32(reg + PAD_CONF1_REG, config->pad_conf1);
write32(reg + PAD_VAL_REG, config->pad_val);
write32((u32 *)(reg + PAD_CONF0_REG), pad_conf0);
write32((u32 *)(reg + PAD_CONF1_REG), config->pad_conf1);
write32((u32 *)(reg + PAD_VAL_REG), config->pad_val);
}
if (bank->legacy_base != GP_LEGACY_BASE_NONE)
@@ -198,7 +198,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
const struct gpio_bank *bank)
{
u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET;
u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
u32 val;
int i;
@@ -206,10 +206,10 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
for (i=0; i<4; ++i) {
val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
dirq[i * 4 + 1] << 8 | dirq[i * 4];
write32(reg + i * 4, val);
write32(reg + i, val);
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
reg + i * 4, val);
reg + i, val);
#endif
}
}
@@ -233,8 +233,8 @@ void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
*/
if (!enable_xdp_tap) {
printk(BIOS_DEBUG, "Tri-state TDO and TMS\n");
write32(GPSSUS_PAD_BASE + 0x2fc, 0xc);
write32(GPSSUS_PAD_BASE + 0x2cc, 0xc);
write32((u32 *)(GPSSUS_PAD_BASE + 0x2fc), 0xc);
write32((u32 *)(GPSSUS_PAD_BASE + 0x2cc), 0xc);
}
}

6
src/soc/intel/baytrail/hda.c
View File

@@ -83,6 +83,7 @@ static void hda_init(device_t dev)
struct resource *res;
int codec_mask;
int i;
u8 *base;
reg_script_run_on_dev(dev, init_ops);
@@ -90,7 +91,8 @@ static void hda_init(device_t dev)
if (res == NULL)
return;
codec_mask = hda_codec_detect(res->base);
base = res2mmio(res, 0, 0);
codec_mask = hda_codec_detect(base);
printk(BIOS_DEBUG, "codec mask = %x\n", codec_mask);
if (!codec_mask)
@@ -99,7 +101,7 @@ static void hda_init(device_t dev)
for (i = 3; i >= 0; i--) {
if (!((1 << i) & codec_mask))
continue;
hda_codec_init(res->base, i, sizeof(hdmi_codec_verb_table),
hda_codec_init(base, i, sizeof(hdmi_codec_verb_table),
hdmi_codec_verb_table);
}
}

4
src/soc/intel/baytrail/iosf.c
View File

@@ -25,11 +25,11 @@
static inline void write_iosf_reg(int reg, uint32_t value)
{
write32(IOSF_PCI_BASE + reg, value);
write32((u32 *)(IOSF_PCI_BASE + reg), value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return read32(IOSF_PCI_BASE + reg);
return read32((u32 *)(IOSF_PCI_BASE + reg));
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)

12
src/soc/intel/baytrail/lpe.c
View File

@@ -90,7 +90,7 @@ static void lpe_enable_acpi_mode(device_t dev)
static void setup_codec_clock(device_t dev)
{
uint32_t reg;
int clk_reg;
u32 *clk_reg;
struct soc_intel_baytrail_config *config;
const char *freq_str;
@@ -119,8 +119,8 @@ static void setup_codec_clock(device_t dev)
printk(BIOS_DEBUG, "LPE Audio codec clock set to %sMHz.\n", freq_str);
clk_reg = PMC_BASE_ADDRESS + PLT_CLK_CTL_0;
clk_reg += 4 * config->lpe_codec_clk_num;
clk_reg = (u32 *)(PMC_BASE_ADDRESS + PLT_CLK_CTL_0);
clk_reg += config->lpe_codec_clk_num;
write32(clk_reg, (read32(clk_reg) & ~0x7) | reg);
}
@@ -144,8 +144,10 @@ static void lpe_stash_firmware_info(device_t dev)
/* C0 and later steppings use an offset in the MMIO space. */
if (pattrs->stepping >= STEP_C0) {
mmio = find_resource(dev, PCI_BASE_ADDRESS_0);
write32(mmio->base + FIRMWARE_REG_BASE_C0, res->base);
write32(mmio->base + FIRMWARE_REG_LENGTH_C0, res->size);
write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_BASE_C0),
res->base);
write32((u32 *)(uintptr_t)(mmio->base + FIRMWARE_REG_LENGTH_C0),
res->size);
}
}

8
src/soc/intel/baytrail/pmutil.c
View File

@@ -355,10 +355,10 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
prsts = read32(PMC_BASE_ADDRESS + PRSTS);
gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
write32(PMC_BASE_ADDRESS + PRSTS, prsts);
write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
}

10
src/soc/intel/baytrail/romstage/romstage.c
View File

@@ -84,8 +84,8 @@ static void program_base_addresses(void)
static void spi_init(void)
{
const unsigned long scs = SPI_BASE_ADDRESS + SCS;
const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
u32 *scs = (u32 *)(SPI_BASE_ADDRESS + SCS);
u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
@@ -169,9 +169,9 @@ static struct chipset_power_state *fill_power_state(void)
ps->gpe0_sts = inl(ACPI_BASE_ADDRESS + GPE0_STS);
ps->gpe0_en = inl(ACPI_BASE_ADDRESS + GPE0_EN);
ps->tco_sts = inl(ACPI_BASE_ADDRESS + TCO_STS);
ps->prsts = read32(PMC_BASE_ADDRESS + PRSTS);
ps->gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
ps->gen_pmcon2 = read32(PMC_BASE_ADDRESS + GEN_PMCON2);
ps->prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
ps->gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
ps->gen_pmcon2 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2));
printk(BIOS_DEBUG, "pm1_sts: %04x pm1_en: %04x pm1_cnt: %08x\n",
ps->pm1_sts, ps->pm1_en, ps->pm1_cnt);

2
src/soc/intel/baytrail/sata.c
View File

@@ -92,7 +92,7 @@ static void sata_init(struct device *dev)
pci_write_config16(dev, 0x92, reg16);
if (config->sata_ahci) {
u32 abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
u8 *abar = (u8 *)pci_read_config32(dev, PCI_BASE_ADDRESS_5);
/* Enable CR memory space decoding */
reg16 = pci_read_config16(dev, 0x04);

2
src/soc/intel/baytrail/smm.c
View File

@@ -66,7 +66,7 @@ void southcluster_smm_clear_state(void)
static void southcluster_smm_route_gpios(void)
{
const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT;
u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
uint32_t alt_gpio_reg = 0;
uint32_t route_reg = smm_save_params[SMM_SAVE_PARAM_GPIO_ROUTE];

30
src/soc/intel/baytrail/southcluster.c
View File

@@ -134,7 +134,7 @@ static void sc_rtc_init(void)
if (ps != NULL) {
gen_pmcon1 = ps->gen_pmcon1;
} else {
gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
}
rtc_fail = !!(gen_pmcon1 & RPS);
@@ -185,20 +185,20 @@ static void com1_configure_resume(device_t dev)
static void sc_init(device_t dev)
{
int i;
const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
const unsigned long gen_pmcon1 = PMC_BASE_ADDRESS + GEN_PMCON1;
const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
u16 *ir_base = (u16 *)ILB_BASE_ADDRESS + 0x20;
u32 *gen_pmcon1 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1);
u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
struct soc_intel_baytrail_config *config = dev->chip_info;
/* Set up the PIRQ PIC routing based on static config. */
for (i = 0; i < NUM_PIRQS; i++) {
write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
write8(pr_base + i, ir->pic[i]);
}
/* Set up the per device PIRQ routing base on static config. */
for (i = 0; i < NUM_IR_DEVS; i++) {
write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
write16(ir_base + i, ir->pcidev[i]);
}
/* Route SCI to IRQ9 */
@@ -226,8 +226,8 @@ static void sc_init(device_t dev)
/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(device_t dev)
{
const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t mask = 0;
uint32_t mask2 = 0;
@@ -347,7 +347,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
* the audio paths work for LPE audio. */
static void hda_work_around(device_t dev)
{
unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
/* Need to set magic register 0x43 to 0xd7 in config space. */
pci_write_config8(dev, 0x43, 0xd7);
@@ -534,11 +534,11 @@ int __attribute__((weak)) mainboard_get_spi_config(struct spi_config *cfg)
static void finalize_chipset(void *unused)
{
const unsigned long bcr = SPI_BASE_ADDRESS + BCR;
const unsigned long gcs = RCBA_BASE_ADDRESS + GCS;
const unsigned long gen_pmcon2 = PMC_BASE_ADDRESS + GEN_PMCON2;
const unsigned long etr = PMC_BASE_ADDRESS + ETR;
const unsigned long spi = SPI_BASE_ADDRESS;
u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
u32 *gcs = (u32 *)(RCBA_BASE_ADDRESS + GCS);
u32 *gen_pmcon2 = (u32 *)(PMC_BASE_ADDRESS + GEN_PMCON2);
u32 *etr = (u32 *)(PMC_BASE_ADDRESS + ETR);
u8 *spi = (u8 *)SPI_BASE_ADDRESS;
struct spi_config cfg;
/* Set the lock enable on the BIOS control register. */

18
src/soc/intel/baytrail/spi.c
View File

@@ -196,33 +196,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
write8((unsigned long)addr, b);
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
write16((unsigned long)addr, b);
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
write32((unsigned long)addr, b);
write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
#define readb_(a) read8((uint32_t)a)
#define readw_(a) read16((uint32_t)a)
#define readl_(a) read32((uint32_t)a)
#define writeb_(val, addr) write8((uint32_t)addr, val)
#define writew_(val, addr) write16((uint32_t)addr, val)
#define writel_(val, addr) write32((uint32_t)addr, val)
#define readb_(a) read8(a)
#define readw_(a) read16(a)
#define readl_(a) read32(a)
#define writeb_(val, addr) write8(addr, val)
#define writew_(val, addr) write16(addr, val)
#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */

7
src/soc/intel/broadwell/adsp.c
View File

@@ -58,7 +58,8 @@ static void adsp_init(struct device *dev)
* SNOOP_REQ[13]=1b SNOOP_SCALE[12:10]=100b (1ms) SNOOP_VAL[9:0]=3h
*/
tmp32 = pch_is_wpt() ? ADSP_SHIM_BASE_WPT : ADSP_SHIM_BASE_LPT;
write32(bar0->base + tmp32 + ADSP_SHIM_LTRC, ADSP_SHIM_LTRC_VALUE);
write32(res2mmio(bar0, tmp32 + ADSP_SHIM_LTRC, 0),
ADSP_SHIM_LTRC_VALUE);
/* Program VDRTCTL2 D19:F0:A8[31:0] = 0x00000fff */
pci_write_config32(dev, ADSP_PCI_VDRTCTL2, ADSP_VDRTCTL2_VALUE);
@@ -115,9 +116,9 @@ static void adsp_init(struct device *dev)
ADSP_PCICFGCTL_ACPIIE);
/* Put ADSP in D3hot */
tmp32 = read32(bar1->base + PCH_PCS);
tmp32 = read32(res2mmio(bar1, PCH_PCS, 0));
tmp32 |= PCH_PCS_PS_D3HOT;
write32(bar1->base + PCH_PCS, tmp32);
write32(res2mmio(bar1, PCH_PCS, 0), tmp32);
} else {
printk(BIOS_INFO, "ADSP: Enable PCI Mode IRQ23\n");

10
src/soc/intel/broadwell/hda.c
View File

@@ -36,7 +36,7 @@ u32 cim_verb_data_size = 0;
const u32 * pc_beep_verbs = NULL;
u32 pc_beep_verbs_size = 0;
static void codecs_init(u32 base, u32 codec_mask)
static void codecs_init(u8 *base, u32 codec_mask)
{
int i;
@@ -52,7 +52,7 @@ static void codecs_init(u32 base, u32 codec_mask)
hda_codec_write(base, pc_beep_verbs_size, pc_beep_verbs);
}
static void hda_pch_init(struct device *dev, u32 base)
static void hda_pch_init(struct device *dev, u8 *base)
{
u8 reg8;
u16 reg16;
@@ -108,7 +108,7 @@ static void hda_pch_init(struct device *dev, u32 base)
static void hda_init(struct device *dev)
{
u32 base;
u8 *base;
struct resource *res;
u32 codec_mask;
u32 reg32;
@@ -118,8 +118,8 @@ static void hda_init(struct device *dev)
if (!res)
return;
base = (u32)res->base;
printk(BIOS_DEBUG, "HDA: base = %08x\n", (u32)base);
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "HDA: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);

4
src/soc/intel/broadwell/igd.c
View File

@@ -246,14 +246,14 @@ static struct resource *gtt_res = NULL;
static unsigned long gtt_read(unsigned long reg)
{
u32 val;
val = read32(gtt_res->base + reg);
val = read32(res2mmio(gtt_res, reg, 0));
return val;
}
static void gtt_write(unsigned long reg, unsigned long data)
{
write32(gtt_res->base + reg, data);
write32(res2mmio(gtt_res, reg, 0), data);
}
static inline void gtt_rmw(u32 reg, u32 andmask, u32 ormask)

8
src/soc/intel/broadwell/lpc.c
View File

@@ -53,22 +53,22 @@ static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
set_ioapic_id(IO_APIC_ADDR, 0x02);
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(IO_APIC_ADDR, 0x01);
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
/* PCH-LP has 39 redirection entries */
reg32 &= ~0x00ff0000;
reg32 |= 0x00270000;
io_apic_write(IO_APIC_ADDR, 0x01, reg32);
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/*
* Select Boot Configuration register (0x03) and
* use Processor System Bus (0x01) to deliver interrupts.
*/
io_apic_write(IO_APIC_ADDR, 0x03, 0x01);
io_apic_write(VIO_APIC_VADDR, 0x03, 0x01);
}
/* PIRQ[n]_ROUT[3:0] - PIRQ Routing Control

6
src/soc/intel/broadwell/me.c
View File

@@ -60,7 +60,7 @@ static const char *me_bios_path_values[] = {
static int intel_me_read_mbp(me_bios_payload *mbp_data, device_t dev);
/* MMIO base address for MEI interface */
static u32 mei_base_address;
static u8 *mei_base_address;
void intel_me_mbp_clear(device_t dev);
#if CONFIG_DEBUG_INTEL_ME
@@ -572,7 +572,7 @@ void intel_me_finalize(void)
u32 reg32;
/* S3 path will have hidden this device already */
if (!mei_base_address || mei_base_address == 0xfffffff0)
if (!mei_base_address || mei_base_address == (u8 *)0xfffffff0)
return;
#if CONFIG_ME_MBP_CLEAR_LATE
@@ -710,7 +710,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
mei_base_address = res->base;
mei_base_address = res2mmio(res, 0, 0);
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);

6
src/soc/intel/broadwell/minihd.c
View File

@@ -68,7 +68,7 @@ static const u32 minihd_verb_table[] = {
static void minihd_init(struct device *dev)
{
struct resource *res;
u32 base, reg32;
u8 *base, reg32;
int codec_mask, i;
/* Find base address */
@@ -76,8 +76,8 @@ static void minihd_init(struct device *dev)
if (!res)
return;
base = (u32)res->base;
printk(BIOS_DEBUG, "Mini-HD: base = %08x\n", (u32)base);
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND);

7
src/soc/intel/broadwell/sata.c
View File

@@ -45,7 +45,8 @@ static inline void sir_write(struct device *dev, int idx, u32 value)
static void sata_init(struct device *dev)
{
config_t *config = dev->chip_info;
u32 reg32, abar;
u32 reg32;
u8 *abar;
u16 reg16;
printk(BIOS_DEBUG, "SATA: Initializing controller in AHCI mode.\n");
@@ -107,8 +108,8 @@ static void sata_init(struct device *dev)
pci_write_config32(dev, 0x94, reg32);
/* Initialize AHCI memory-mapped space */
abar = pci_read_config32(dev, PCI_BASE_ADDRESS_5);
printk(BIOS_DEBUG, "ABAR: %08X\n", abar);
abar = (u8 *)(pci_read_config32(dev, PCI_BASE_ADDRESS_5));
printk(BIOS_DEBUG, "ABAR: %p\n", abar);
/* CAP (HBA Capabilities) : enable power management */
reg32 = read32(abar + 0x00);

36
src/soc/intel/broadwell/serialio.c
View File

@@ -37,9 +37,9 @@
/* Set D3Hot Power State in ACPI mode */
static void serialio_enable_d3hot(struct resource *res)
{
u32 reg32 = read32(res->base + PCH_PCS);
u32 reg32 = read32(res2mmio(res, PCH_PCS, 0));
reg32 |= PCH_PCS_PS_D3HOT;
write32(res->base + PCH_PCS, reg32);
write32(res2mmio(res, PCH_PCS, 0), reg32);
}
static int serialio_uart_is_debug(struct device *dev)
@@ -58,9 +58,9 @@ static int serialio_uart_is_debug(struct device *dev)
/* Enable clock in PCI mode */
static void serialio_enable_clock(struct resource *bar0)
{
u32 reg32 = read32(bar0->base + SIO_REG_PPR_CLOCK);
u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0));
reg32 |= SIO_REG_PPR_CLOCK_EN;
write32(bar0->base + SIO_REG_PPR_CLOCK, reg32);
write32(res2mmio(bar0, SIO_REG_PPR_CLOCK, 0), reg32);
}
/* Put Serial IO D21:F0-F6 device into desired mode. */
@@ -111,22 +111,22 @@ static void serialio_d21_ltr(struct resource *bar0)
u32 reg;
/* 1. Program BAR0 + 808h[2] = 0b */
reg = read32(bar0->base + SIO_REG_PPR_GEN);
reg = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
reg &= ~SIO_REG_PPR_GEN_LTR_MODE_MASK;
write32(bar0->base + SIO_REG_PPR_GEN, reg);
write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg);
/* 2. Program BAR0 + 804h[1:0] = 00b */
reg = read32(bar0->base + SIO_REG_PPR_RST);
reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
reg &= ~SIO_REG_PPR_RST_ASSERT;
write32(bar0->base + SIO_REG_PPR_RST, reg);
write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
/* 3. Program BAR0 + 804h[1:0] = 11b */
reg = read32(bar0->base + SIO_REG_PPR_RST);
reg = read32(res2mmio(bar0, SIO_REG_PPR_RST, 0));
reg |= SIO_REG_PPR_RST_ASSERT;
write32(bar0->base + SIO_REG_PPR_RST, reg);
write32(res2mmio(bar0, SIO_REG_PPR_RST, 0), reg);
/* 4. Program BAR0 + 814h[31:0] = 00000000h */
write32(bar0->base + SIO_REG_AUTO_LTR, 0);
write32(res2mmio(bar0, SIO_REG_AUTO_LTR, 0), 0);
}
/* Enable LTR Auto Mode for D23:F0. */
@@ -135,26 +135,26 @@ static void serialio_d23_ltr(struct resource *bar0)
u32 reg;
/* Program BAR0 + 1008h[2] = 1b */
reg = read32(bar0->base + SIO_REG_SDIO_PPR_GEN);
reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0));
reg |= SIO_REG_PPR_GEN_LTR_MODE_MASK;
write32(bar0->base + SIO_REG_SDIO_PPR_GEN, reg);
write32(res2mmio(bar0, SIO_REG_SDIO_PPR_GEN, 0), reg);
/* Program BAR0 + 1010h = 0x00000000 */
write32(bar0->base + SIO_REG_SDIO_PPR_SW_LTR, 0);
write32(res2mmio(bar0, SIO_REG_SDIO_PPR_SW_LTR, 0), 0);
/* Program BAR0 + 3Ch[30] = 1b */
reg = read32(bar0->base + SIO_REG_SDIO_PPR_CMD12);
reg = read32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0));
reg |= SIO_REG_SDIO_PPR_CMD12_B30;
write32(bar0->base + SIO_REG_SDIO_PPR_CMD12, reg);
write32(res2mmio(bar0, SIO_REG_SDIO_PPR_CMD12, 0), reg);
}
/* Select I2C voltage of 1.8V or 3.3V. */
static void serialio_i2c_voltage_sel(struct resource *bar0, u8 voltage)
{
u32 reg32 = read32(bar0->base + SIO_REG_PPR_GEN);
u32 reg32 = read32(res2mmio(bar0, SIO_REG_PPR_GEN, 0));
reg32 &= ~SIO_REG_PPR_GEN_VOLTAGE_MASK;
reg32 |= SIO_REG_PPR_GEN_VOLTAGE(voltage);
write32(bar0->base + SIO_REG_PPR_GEN, reg32);
write32(res2mmio(bar0, SIO_REG_PPR_GEN, 0), reg32);
}
/* Init sequence to be run once, done as part of D21:F0 (SDMA) init. */

24
src/soc/intel/broadwell/spi.c
View File

@@ -168,7 +168,7 @@ enum {
static u8 readb_(const void *addr)
{
u8 v = read8((unsigned long)addr);
u8 v = read8(addr);
printk(BIOS_DEBUG, "read %2.2x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -176,7 +176,7 @@ static u8 readb_(const void *addr)
static u16 readw_(const void *addr)
{
u16 v = read16((unsigned long)addr);
u16 v = read16(addr);
printk(BIOS_DEBUG, "read %4.4x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -184,7 +184,7 @@ static u16 readw_(const void *addr)
static u32 readl_(const void *addr)
{
u32 v = read32((unsigned long)addr);
u32 v = read32(addr);
printk(BIOS_DEBUG, "read %8.8x from %4.4x\n",
v, ((unsigned) addr & 0xffff) - 0xf020);
return v;
@@ -192,33 +192,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
write8((unsigned long)addr, b);
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
write16((unsigned long)addr, b);
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
write32((unsigned long)addr, b);
write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
#define readb_(a) read8((uint32_t)a)
#define readw_(a) read16((uint32_t)a)
#define readl_(a) read32((uint32_t)a)
#define writeb_(val, addr) write8((uint32_t)addr, val)
#define writew_(val, addr) write16((uint32_t)addr, val)
#define writel_(val, addr) write32((uint32_t)addr, val)
#define readb_(a) read8(a)
#define readw_(a) read16(a)
#define readl_(a) read32(a)
#define writeb_(val, addr) write8(addr, val)
#define writew_(val, addr) write16(addr, val)
#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */

18
src/soc/intel/broadwell/xhci.c
View File

@@ -27,7 +27,7 @@
#include <broadwell/xhci.h>
#ifdef __SMM__
static u32 usb_xhci_mem_base(device_t dev)
static u8 *usb_xhci_mem_base(device_t dev)
{
u32 mem_base = pci_read_config32(dev, PCI_BASE_ADDRESS_0);
@@ -35,7 +35,7 @@ static u32 usb_xhci_mem_base(device_t dev)
if (mem_base == 0 || mem_base == 0xffffffff)
return 0;
return mem_base & ~0xf;
return (u8 *)(mem_base & ~0xf);
}
static int usb_xhci_port_count_usb3(device_t dev)
@@ -44,9 +44,9 @@ static int usb_xhci_port_count_usb3(device_t dev)
return 4;
}
static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
static void usb_xhci_reset_status_usb3(u8 *mem_base, int port)
{
u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
u32 status = read32(portsc);
/* Do not set Port Enabled/Disabled field */
status &= ~XHCI_USB3_PORTSC_PED;
@@ -55,9 +55,9 @@ static void usb_xhci_reset_status_usb3(u32 mem_base, int port)
write32(portsc, status);
}
static void usb_xhci_reset_port_usb3(u32 mem_base, int port)
static void usb_xhci_reset_port_usb3(u8 *mem_base, int port)
{
u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
write32(portsc, read32(portsc) | XHCI_USB3_PORTSC_WPR);
}
@@ -76,7 +76,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
u32 status, port_disabled;
int timeout, port;
int port_count = usb_xhci_port_count_usb3(dev);
u32 mem_base = usb_xhci_mem_base(dev);
u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || !port_count)
return;
@@ -105,7 +105,7 @@ static void usb_xhci_reset_usb3(device_t dev, int all)
/* Reset all requested ports */
for (port = 0; port < port_count; port++) {
u32 portsc = mem_base + XHCI_USB3_PORTSC(port);
u8 *portsc = mem_base + XHCI_USB3_PORTSC(port);
/* Skip disabled ports */
if (port_disabled & (1 << port))
continue;
@@ -146,7 +146,7 @@ void usb_xhci_sleep_prepare(device_t dev, u8 slp_typ)
{
u16 reg16;
u32 reg32;
u32 mem_base = usb_xhci_mem_base(dev);
u8 *mem_base = usb_xhci_mem_base(dev);
if (!mem_base || slp_typ < 3)
return;

12
src/soc/intel/common/hda_verb.c
View File

@@ -27,7 +27,7 @@
/**
* Set bits in a register and wait for status
*/
static int set_bits(u32 port, u32 mask, u32 val)
static int set_bits(void *port, u32 mask, u32 val)
{
u32 reg32;
int count;
@@ -59,7 +59,7 @@ static int set_bits(u32 port, u32 mask, u32 val)
/**
* Probe for supported codecs
*/
int hda_codec_detect(u32 base)
int hda_codec_detect(u8 *base)
{
u8 reg8;
@@ -90,7 +90,7 @@ no_codec:
* Wait 50usec for the codec to indicate it is ready
* no response would imply that the codec is non-operative
*/
static int hda_wait_for_ready(u32 base)
static int hda_wait_for_ready(u8 *base)
{
/* Use a 50 usec timeout - the Linux kernel uses the
* same duration */
@@ -112,7 +112,7 @@ static int hda_wait_for_ready(u32 base)
* the previous command. No response would imply that the code
* is non-operative
*/
static int hda_wait_for_valid(u32 base)
static int hda_wait_for_valid(u8 *base)
{
u32 reg32;
@@ -184,7 +184,7 @@ static u32 hda_find_verb(u32 verb_table_bytes,
/**
* Write a supplied verb table
*/
int hda_codec_write(u32 base, u32 size, const u32 *data)
int hda_codec_write(u8 *base, u32 size, const u32 *data)
{
int i;
@@ -204,7 +204,7 @@ int hda_codec_write(u32 base, u32 size, const u32 *data)
/**
* Initialize codec, then find the verb table and write it
*/
int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data)
int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data)
{
const u32 *verb;
u32 reg32, size;

6
src/soc/intel/common/hda_verb.h
View File

@@ -32,8 +32,8 @@
#define HDA_ICII_BUSY (1 << 0)
#define HDA_ICII_VALID (1 << 1)
int hda_codec_detect(u32 base);
int hda_codec_write(u32 base, u32 size, const u32 *data);
int hda_codec_init(u32 base, int addr, int verb_size, const u32 *verb_data);
int hda_codec_detect(u8 *base);
int hda_codec_write(u8 *base, u32 size, const u32 *data);
int hda_codec_init(u8 *base, int addr, int verb_size, const u32 *verb_data);
#endif /* _COMMON_HDA_VERB_H_ */

2
src/soc/intel/fsp_baytrail/acpi.c
View File

@@ -105,7 +105,7 @@ void acpi_init_gnvs(global_nvs_t *gnvs)
static int acpi_sci_irq(void)
{
const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
int scis;
static int sci_irq;

5
src/soc/intel/fsp_baytrail/baytrail/baytrail.h
View File

@@ -34,8 +34,11 @@
/* Southbridge internal device MEM BARs (Set to match FSP settings) */
#define DEFAULT_IBASE 0xfed08000
#define DEFAULT_PBASE 0xfed03000
#ifndef __ACPI__
#define DEFAULT_RCBA ((u8 *)0xfed1c000)
#else
#define DEFAULT_RCBA 0xfed1c000
#endif
/* Everything below this line is ignored in the DSDT */
#ifndef __ACPI__

16
src/soc/intel/fsp_baytrail/baytrail/gpio.h
View File

@@ -353,20 +353,20 @@ void configure_score_gpio(uint8_t gpio_num, uint32_t pconf0, uint32_t pad_val);
#define PCU_SMB_CLK_PAD 88
#define PCU_SMB_DATA_PAD 90
static inline unsigned int score_pconf0(int pad_num)
static inline uint32_t *score_pconf0(int pad_num)
{
return GPSCORE_PAD_BASE + pad_num * 16;
return (uint32_t *)(GPSCORE_PAD_BASE + pad_num * 16);
}
static inline unsigned int ssus_pconf0(int pad_num)
static inline uint32_t *ssus_pconf0(int pad_num)
{
return GPSSUS_PAD_BASE + pad_num * 16;
return (uint32_t *)(GPSSUS_PAD_BASE + pad_num * 16);
}
static inline void score_select_func(int pad, int func)
{
uint32_t reg;
uint32_t pconf0_addr = score_pconf0(pad);
uint32_t *pconf0_addr = score_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -377,7 +377,7 @@ static inline void score_select_func(int pad, int func)
static inline void ssus_select_func(int pad, int func)
{
uint32_t reg;
uint32_t pconf0_addr = ssus_pconf0(pad);
uint32_t *pconf0_addr = ssus_pconf0(pad);
reg = read32(pconf0_addr);
reg &= ~0x7;
@@ -390,14 +390,14 @@ static inline void ssus_select_func(int pad, int func)
/* These functions require that the input pad be configured as an input GPIO */
static inline int score_get_gpio(int pad)
{
uint32_t val_addr = score_pconf0(pad) + PAD_VAL_REG;
uint32_t *val_addr = score_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}
static inline int ssus_get_gpio(int pad)
{
uint32_t val_addr = ssus_pconf0(pad) + PAD_VAL_REG;
uint32_t *val_addr = ssus_pconf0(pad) + (PAD_VAL_REG/sizeof(uint32_t));
return read32(val_addr) & PAD_VAL_HIGH;
}

2
src/soc/intel/fsp_baytrail/bootblock/bootblock.c
View File

@@ -63,7 +63,7 @@ static void set_var_mtrr(int reg, uint32_t base, uint32_t size, int type)
*/
static void enable_spi_prefetch(void)
{
uint32_t bcr = SPI_BASE_ADDRESS + BCR;
u32 *bcr = (u32 *)(SPI_BASE_ADDRESS + BCR);
/* Enable caching and prefetching in the SPI controller. */
write32(bcr, (read32(bcr) & ~SRC_MASK) | SRC_CACHE_PREFETCH);
}

30
src/soc/intel/fsp_baytrail/gpio.c
View File

@@ -103,7 +103,7 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
{
const struct soc_gpio_map *config;
int gpio = 0;
u32 reg, pad_conf0;
u32 reg, pad_conf0, *regmmio;
u8 set, bit;
u32 use_sel[4] = {0};
@@ -138,7 +138,8 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
}
/* Pad configuration registers */
reg = bank->pad_base + 16 * bank->gpio_to_pad[gpio];
regmmio = (u32 *)(bank->pad_base + 16 *
bank->gpio_to_pad[gpio]);
/* Add correct func to GPIO pad config */
pad_conf0 = config->pad_conf0;
@@ -152,13 +153,14 @@ static void setup_gpios(const struct soc_gpio_map *gpios,
}
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write Pad: Base(%x) - %x %x %x\n",
reg, pad_conf0, config->pad_conf1, config->pad_val);
printk(BIOS_DEBUG, "Write Pad: Base(%p) - %x %x %x\n",
regmmio, pad_conf0, config->pad_conf1, config->pad_val);
#endif
write32(reg + PAD_CONF0_REG, pad_conf0);
write32(reg + PAD_CONF1_REG, config->pad_conf1);
write32(reg + PAD_VAL_REG, config->pad_val);
write32(regmmio + (PAD_CONF0_REG/sizeof(u32)), pad_conf0);
write32(regmmio + (PAD_CONF1_REG/sizeof(u32)),
config->pad_conf1);
write32(regmmio + (PAD_VAL_REG/sizeof(u32)), config->pad_val);
}
if (bank->legacy_base != GP_LEGACY_BASE_NONE)
@@ -215,7 +217,7 @@ static void setup_gpio_route(const struct soc_gpio_map *sus,
static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
const struct gpio_bank *bank)
{
u32 reg = bank->pad_base + PAD_BASE_DIRQ_OFFSET;
u32 *reg = (u32 *)(bank->pad_base + PAD_BASE_DIRQ_OFFSET);
u32 val;
int i;
@@ -223,10 +225,10 @@ static void setup_dirqs(const u8 dirq[GPIO_MAX_DIRQS],
for (i=0; i<4; ++i) {
val = dirq[i * 4 + 3] << 24 | dirq[i * 4 + 2] << 16 |
dirq[i * 4 + 1] << 8 | dirq[i * 4];
write32(reg + i * 4, val);
write32(reg + i, val);
#ifdef GPIO_DEBUG
printk(BIOS_DEBUG, "Write DIRQ reg(%x) - %x\n",
reg + i * 4, val);
reg + i, val);
#endif
}
}
@@ -299,7 +301,7 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
uint32_t pconf0, uint32_t pad_val)
{
uint32_t reg;
uint32_t pad_addr;
uint32_t *pad_addr;
if (ssus_gpio)
pad_addr = ssus_pconf0(gpssus_gpio_to_pad[gpio_num]);
else
@@ -321,7 +323,7 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
*/
reg = PAD_CONFIG0_DEFAULT;
reg |= pconf0 & 0x787;
write32(pad_addr + PAD_CONF0_REG, reg);
write32(pad_addr + (PAD_CONF0_REG/sizeof(u32)), reg);
/*
* Pad Value Register
@@ -329,10 +331,10 @@ static void configure_ssus_score_gpio(uint8_t ssus_gpio, uint8_t gpio_num,
* 1: output enable (0 is enabled)
* 2: input enable (0 is enabled)
*/
reg = read32(pad_addr + PAD_VAL_REG);
reg = read32(pad_addr + (PAD_VAL_REG/sizeof(u32)));
reg &= ~0x7;
reg |= pad_val & 0x7;
write32(pad_addr + PAD_VAL_REG, reg);
write32(pad_addr + (PAD_VAL_REG/sizeof(u32)), reg);
}
/** \brief Sets up the function, pulls, and Input/Output of a Baytrail S5 GPIO

4
src/soc/intel/fsp_baytrail/iosf.c
View File

@@ -29,11 +29,11 @@
static inline void write_iosf_reg(int reg, uint32_t value)
{
write32(IOSF_PCI_BASE + reg, value);
write32((u32 *)(IOSF_PCI_BASE + reg), value);
}
static inline uint32_t read_iosf_reg(int reg)
{
return read32(IOSF_PCI_BASE + reg);
return read32((u32 *)(IOSF_PCI_BASE + reg));
}
#else
static inline void write_iosf_reg(int reg, uint32_t value)

8
src/soc/intel/fsp_baytrail/pmutil.c
View File

@@ -355,10 +355,10 @@ void clear_pmc_status(void)
uint32_t prsts;
uint32_t gen_pmcon1;
prsts = read32(PMC_BASE_ADDRESS + PRSTS);
gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
prsts = read32((u32 *)(PMC_BASE_ADDRESS + PRSTS));
gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
/* Clear the status bits. The RPS field is cleared on a 0 write. */
write32(PMC_BASE_ADDRESS + GEN_PMCON1, gen_pmcon1 & ~RPS);
write32(PMC_BASE_ADDRESS + PRSTS, prsts);
write32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1), gen_pmcon1 & ~RPS);
write32((u32 *)(PMC_BASE_ADDRESS + PRSTS), prsts);
}

16
src/soc/intel/fsp_baytrail/romstage/romstage.c
View File

@@ -56,7 +56,7 @@ uint32_t chipset_prev_sleep_state(uint32_t clear)
/* Read Power State */
pm1_sts = inw(ACPI_BASE_ADDRESS + PM1_STS);
pm1_cnt = inl(ACPI_BASE_ADDRESS + PM1_CNT);
gen_pmcon1 = read32(PMC_BASE_ADDRESS + GEN_PMCON1);
gen_pmcon1 = read32((u32 *)(PMC_BASE_ADDRESS + GEN_PMCON1));
printk(BIOS_DEBUG, "PM1_STS = 0x%x PM1_CNT = 0x%x GEN_PMCON1 = 0x%x\n",
pm1_sts, pm1_cnt, gen_pmcon1);
@@ -118,8 +118,8 @@ static void program_base_addresses(void)
static void spi_init(void)
{
const uint32_t scs = SPI_BASE_ADDRESS + SCS;
const uint32_t bcr = SPI_BASE_ADDRESS + BCR;
uint32_t *scs = (uint32_t *)(SPI_BASE_ADDRESS + SCS);
uint32_t *bcr = (uint32_t *)(SPI_BASE_ADDRESS + BCR);
uint32_t reg;
/* Disable generating SMI when setting WPD bit. */
@@ -135,8 +135,8 @@ static void spi_init(void)
static void baytrail_rtc_init(void)
{
uint32_t pbase = pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0;
uint32_t gen_pmcon1 = read32(pbase + GEN_PMCON1);
uint32_t *pbase = (uint32_t *)(pci_read_config32(LPC_BDF, PBASE) & 0xfffffff0);
uint32_t gen_pmcon1 = read32(pbase + (GEN_PMCON1/sizeof(u32)));
int rtc_failed = !!(gen_pmcon1 & RPS);
if (rtc_failed) {
@@ -144,7 +144,7 @@ static void baytrail_rtc_init(void)
"RTC Failure detected. Resetting Date to %s\n",
coreboot_dmi_date);
write32(DEFAULT_PBASE + GEN_PMCON1, gen_pmcon1 & ~RPS);
write32((uint32_t *)(DEFAULT_PBASE + GEN_PMCON1), gen_pmcon1 & ~RPS);
}
cmos_init(rtc_failed);
@@ -153,8 +153,8 @@ static void baytrail_rtc_init(void)
/* Entry from cache-as-ram.inc. */
void main(FSP_INFO_HEADER *fsp_info_header)
{
const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
uint32_t *func_dis = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS);
uint32_t *func_dis2 = (uint32_t *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t fd_mask = 0;
uint32_t fd2_mask = 0;

2
src/soc/intel/fsp_baytrail/smm.c
View File

@@ -67,7 +67,7 @@ void southcluster_smm_clear_state(void)
static void southcluster_smm_route_gpios(void)
{
const unsigned long gpio_rout = PMC_BASE_ADDRESS + GPIO_ROUT;
u32 *gpio_rout = (u32 *)(PMC_BASE_ADDRESS + GPIO_ROUT);
const unsigned short alt_gpio_smi = ACPI_BASE_ADDRESS + ALT_GPIO_SMI;
uint32_t alt_gpio_reg = 0;
uint32_t route_reg = gpio_route;

32
src/soc/intel/fsp_baytrail/southcluster.c
View File

@@ -82,17 +82,17 @@ static void sc_enable_ioapic(struct device *dev)
{
int i;
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
u32 ilb_base = pci_read_config32(dev, IBASE) & ~0x0f;
volatile u32 *ioapic_index = (u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (u32 *)(IO_APIC_ADDR + 0x10);
u8 *ilb_base = (u8 *)(pci_read_config32(dev, IBASE) & ~0x0f);
/*
* Enable ACPI I/O and power management.
* Set SCI IRQ to IRQ9
*/
write32(ilb_base + ILB_OIC, 0x100); /* AEN */
reg32 = read32(ilb_base + ILB_OIC); /* Read back per BWG */
write32(ilb_base + ILB_ACTL, 0); /* ACTL bit 2:0 SCIS IRQ9 */
reg32 = read32(ilb_base + (ILB_OIC/sizeof(u32))); /* Read back per BWG */
write32(ilb_base + (ILB_ACTL/sizeof(u32)), 0); /* ACTL bit 2:0 SCIS IRQ9 */
*ioapic_index = 0;
*ioapic_data = (1 << 25);
@@ -131,7 +131,7 @@ static void sc_enable_serial_irqs(struct device *dev)
* until we understand how it needs to be configured.
*/
u8 reg8;
u32 ibase = pci_read_config32(dev, IBASE) & ~0xF;
u8 *ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
/*
* Disable the IOCHK# NMI. Let the NMI handler enable it if it needs.
@@ -259,9 +259,9 @@ static void sc_pirq_init(device_t dev)
{
int i, j;
int pirq;
const unsigned long pr_base = ILB_BASE_ADDRESS + 0x08;
const unsigned long ir_base = ILB_BASE_ADDRESS + 0x20;
const unsigned long actl = ILB_BASE_ADDRESS + ACTL;
u8 *pr_base = (u8 *)(ILB_BASE_ADDRESS + 0x08);
u16 *ir_base = (u16 *)(ILB_BASE_ADDRESS + 0x20);
u32 *actl = (u32 *)(ILB_BASE_ADDRESS + ACTL);
const struct baytrail_irq_route *ir = &global_baytrail_irq_route;
/* Set up the PIRQ PIC routing based on static config. */
@@ -269,7 +269,7 @@ static void sc_pirq_init(device_t dev)
"PIRQ\tA \tB \tC \tD \tE \tF \tG \tH\n"
"IRQ ");
for (i = 0; i < NUM_PIRQS; i++) {
write8(pr_base + i*sizeof(ir->pic[i]), ir->pic[i]);
write8(pr_base + i, ir->pic[i]);
printk(BIOS_SPEW, "\t%d", ir->pic[i]);
}
printk(BIOS_SPEW, "\n\n");
@@ -278,7 +278,7 @@ static void sc_pirq_init(device_t dev)
printk(BIOS_SPEW, "\t\t\tPIRQ[A-H] routed to each INT_PIN[A-D]\n"
"Dev\tINTA (IRQ)\tINTB (IRQ)\tINTC (IRQ)\tINTD (IRQ)\n");
for (i = 0; i < NUM_OF_PCI_DEVS; i++) {
write16(ir_base + i*sizeof(ir->pcidev[i]), ir->pcidev[i]);
write16(ir_base + i, ir->pcidev[i]);
/* If the entry is more than just 0, print it out */
if(ir->pcidev[i]) {
@@ -372,11 +372,11 @@ static void enable_hpet(void)
static void sc_init(struct device *dev)
{
u32 ibase;
u8 *ibase;
printk(BIOS_DEBUG, "soc: southcluster_init\n");
ibase = pci_read_config32(dev, IBASE) & ~0xF;
ibase = (u8 *)(pci_read_config32(dev, IBASE) & ~0xF);
write8(ibase + ILB_MC, 0);
@@ -411,8 +411,8 @@ static void sc_init(struct device *dev)
/* Set bit in function disable register to hide this device. */
static void sc_disable_devfn(device_t dev)
{
const unsigned long func_dis = PMC_BASE_ADDRESS + FUNC_DIS;
const unsigned long func_dis2 = PMC_BASE_ADDRESS + FUNC_DIS2;
u32 *func_dis = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS);
u32 *func_dis2 = (u32 *)(PMC_BASE_ADDRESS + FUNC_DIS2);
uint32_t fd_mask = 0;
uint32_t fd2_mask = 0;
@@ -471,7 +471,7 @@ static inline void set_d3hot_bits(device_t dev, int offset)
* the audio paths work for LPE audio. */
static void hda_work_around(device_t dev)
{
unsigned long gctl = TEMP_BASE_ADDRESS + 0x8;
u32 *gctl = (u32 *)(TEMP_BASE_ADDRESS + 0x8);
/* Need to set magic register 0x43 to 0xd7 in config space. */
pci_write_config8(dev, 0x43, 0xd7);

18
src/soc/intel/fsp_baytrail/spi.c
View File

@@ -193,33 +193,33 @@ static u32 readl_(const void *addr)
static void writeb_(u8 b, const void *addr)
{
write8((unsigned long)addr, b);
write8(addr, b);
printk(BIOS_DEBUG, "wrote %2.2x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writew_(u16 b, const void *addr)
{
write16((unsigned long)addr, b);
write16(addr, b);
printk(BIOS_DEBUG, "wrote %4.4x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
static void writel_(u32 b, const void *addr)
{
write32((unsigned long)addr, b);
write32(addr, b);
printk(BIOS_DEBUG, "wrote %8.8x to %4.4x\n",
b, ((unsigned) addr & 0xffff) - 0xf020);
}
#else /* CONFIG_DEBUG_SPI_FLASH ^^^ enabled vvv NOT enabled */
#define readb_(a) read8((uint32_t)a)
#define readw_(a) read16((uint32_t)a)
#define readl_(a) read32((uint32_t)a)
#define writeb_(val, addr) write8((uint32_t)addr, val)
#define writew_(val, addr) write16((uint32_t)addr, val)
#define writel_(val, addr) write32((uint32_t)addr, val)
#define readb_(a) read8(a)
#define readw_(a) read16(a)
#define readl_(a) read32(a)
#define writeb_(val, addr) write8(addr, val)
#define writew_(val, addr) write16(addr, val)
#define writel_(val, addr) write32(addr, val)
#endif /* CONFIG_DEBUG_SPI_FLASH ^^^ NOT enabled */