sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

x86: Change MMIO addr in readN(addr)/writeN(addr, val) to pointer

Browse Source 
On x86, change the type of the address parameter in
read8()/read16/read32()/write8()/write16()/write32() to be a
pointer, instead of unsigned long.

Change-Id: Ic26dd8a72d82828b69be3c04944710681b7bd330
Signed-off-by: Kevin Paul Herbert <kph@meraki.net>
Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com>
Reviewed-on: http://review.coreboot.org/7784
Tested-by: build bot (Jenkins)
This commit is contained in:
Kevin Paul Herbert
2014-12-24 18:43:20 -08:00
committed by Alexandru Gagniuc
parent 4b10dec1a6
commit bde6d309df
354 changed files with 1900 additions and 1684 deletions
Download Patch File Download Diff File Expand all files Collapse all files

18
src/southbridge/intel/ibexpeak/me.c
View File

@@ -63,7 +63,7 @@ static const char *me_bios_path_values[] = {
#endif
/* MMIO base address for MEI interface */
static u32 mei_base_address;
static u32 *mei_base_address;
#if CONFIG_DEBUG_INTEL_ME
static void mei_dump(void *ptr, int dword, int offset, const char *type)
@@ -105,7 +105,7 @@ static void mei_dump(void *ptr, int dword, int offset, const char *type)
static inline void mei_read_dword_ptr(void *ptr, int offset)
{
u32 dword = read32(mei_base_address + offset);
u32 dword = read32(mei_base_address + (offset/sizeof(u32)));
memcpy(ptr, &dword, sizeof(dword));
mei_dump(ptr, dword, offset, "READ");
}
@@ -114,7 +114,7 @@ static inline void mei_write_dword_ptr(void *ptr, int offset)
{
u32 dword = 0;
memcpy(&dword, ptr, sizeof(dword));
write32(mei_base_address + offset, dword);
write32(mei_base_address + (offset/sizeof(u32)), dword);
mei_dump(ptr, dword, offset, "WRITE");
}
@@ -145,13 +145,13 @@ static inline void read_me_csr(struct mei_csr *csr)
static inline void write_cb(u32 dword)
{
write32(mei_base_address + MEI_H_CB_WW, dword);
write32(mei_base_address + (MEI_H_CB_WW/sizeof(u32)), dword);
mei_dump(NULL, dword, MEI_H_CB_WW, "WRITE");
}
static inline u32 read_cb(void)
{
u32 dword = read32(mei_base_address + MEI_ME_CB_RW);
u32 dword = read32(mei_base_address + (MEI_ME_CB_RW/sizeof(u32)));
mei_dump(NULL, dword, MEI_ME_CB_RW, "READ");
return dword;
}
@@ -382,11 +382,11 @@ static void intel_me7_finalize_smm(void)
struct me_hfs hfs;
u32 reg32;
mei_base_address =
pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf;
mei_base_address = (u32 *)
(pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf);
/* S3 path will have hidden this device already */
if (!mei_base_address || mei_base_address == 0xfffffff0)
if (!mei_base_address || mei_base_address == (u32 *)0xfffffff0)
return;
/* Make sure ME is in a mode that expects EOP */
@@ -508,7 +508,7 @@ static int intel_mei_setup(device_t dev)
printk(BIOS_DEBUG, "ME: MEI resource not present!\n");
return -1;
}
mei_base_address = res->base;
mei_base_address = (u32 *)(uintptr_t)res->base;
/* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND);