sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

acpi: Change Processor ACPI Name (Intel only)

Browse Source 
The ACPI Spec 2.0 states, that Processor declarations should be made
within the ACPI namespace \_SB and not \_PR anymore. \_PR is deprecated
and is removed here for Intel CPUs only.

Tested on:
* X11SSH (Kabylake)
* CFL Platform
* Asus P8Z77-V LX2 and Windows 10

FWTS does not return FAIL anymore on ACPI tests

Tested-by: Angel Pons <th3fanbus@gmail.com>
Change-Id: Ib101ed718f90f9056d2ecbc31b13b749ed1fc438
Signed-off-by: Christian Walter <christian.walter@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37814
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>
This commit is contained in:
Christian Walter
2019-12-18 15:07:59 +01:00
committed by Nico Huber
parent 09eb8d0c9b
commit be3979c873
30 changed files with 140 additions and 137 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu/intel/common/acpi/cpu.asl
View File

@@ -13,22 +13,22 @@
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
External (\_SB.CNOT, MethodObj)
/* Notify OS to re-read CPU tables */
Method (PNOT)
{
\_PR.CNOT (0x81)
\_SB.CNOT (0x81)
}
/* Notify OS to re-read CPU _PPC limit */
Method (PPCN)
{
\_PR.CNOT (0x80)
\_SB.CNOT (0x80)
}
/* Notify OS to re-read Throttle Limit tables */
Method (TNOT)
{
\_PR.CNOT (0x82)
\_SB.CNOT (0x82)
}

2
src/cpu/intel/haswell/acpi.c
View File

@@ -317,7 +317,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);

2
src/cpu/intel/model_2065x/acpi.c
View File

@@ -309,7 +309,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);

2
src/cpu/intel/model_206ax/acpi.c
View File

@@ -312,7 +312,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx */
/* Generate processor \_SB.CPUx */
acpigen_write_processor(
(cpuID-1)*cores_per_package+coreID-1,
pcontrol_blk, plen);

2
src/cpu/intel/speedstep/acpi.c
View File

@@ -124,7 +124,7 @@ void generate_cpu_entries(struct device *device)
plen = 0;
}
/* Generate processor \_PR.CPUx. */
/* Generate processor \_SB.CPUx. */
acpigen_write_processor(
cpuID * cores_per_package + coreID - 1,
pcontrol_blk, plen);

16
src/cpu/intel/speedstep/acpi/cpu.asl
View File

@@ -12,20 +12,20 @@
*/
/* These come from the dynamically created CPU SSDT */
External (\_PR.CNOT, MethodObj)
External (\_PR_.CP00, DeviceObj)
External (\_PR_.CP00._PPC)
External (\_PR_.CP01._PPC)
External (\_SB.CNOT, MethodObj)
External (\_SB_.CP00, DeviceObj)
External (\_SB_.CP00._PPC)
External (\_SB_.CP01._PPC)
Method (PNOT)
{
If (MPEN) {
\_PR.CNOT (0x80) // _PPC
\_SB.CNOT (0x80) // _PPC
Sleep(100)
\_PR.CNOT (0x81) // _CST
\_SB.CNOT (0x81) // _CST
} Else { // UP
Notify (\_PR_.CP00, 0x80)
Notify (\_SB_.CP00, 0x80)
Sleep(0x64)
Notify(\_PR_.CP00, 0x81)
Notify(\_SB_.CP00, 0x81)
}
}