This, ladies and gentlement, is commit #4000.

Use the (almost) same strict CFLAGS in v2 that we use on v3. And fix a few
include files and missing prototypes. Also, fix up the Config-abuild.lb files
to properly work for cross compiling.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4000 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/arch/i386/include/arch/acpi.h

@@ -5,9 +5,7 @@
  * (C) 2004 SUSE LINUX AG
  *
  * The ACPI table structs are based on the Linux kernel sources.
- * 
+ * ACPI FADT & FACS added by Nick Barker <nick.barker9@btinternet.com>
- */
-/* ACPI FADT & FACS added by Nick Barker <nick.barker9@btinternet.com>
  * those parts (C) 2004 Nick Barker
  */
 
@@ -331,6 +329,8 @@ void acpi_create_facs(acpi_facs_t *facs);
 void acpi_write_rsdt(acpi_rsdt_t *rsdt);
 void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt);
 
+unsigned long acpi_add_ssdt_pstates(acpi_rsdt_t *rsdt, unsigned long current);
+
 #define ACPI_WRITE_MADT_IOAPIC(dev,id)        		\
 do {                                                    \
         struct resource *res;                           \

src/arch/i386/include/arch/pci_ops.h

@@ -1,11 +1,11 @@
 #ifndef ARCH_I386_PCI_OPS_H
 #define ARCH_I386_PCI_OPS_H
 
-const struct pci_bus_operations pci_cf8_conf1;
+extern const struct pci_bus_operations pci_cf8_conf1;
-const struct pci_bus_operations pci_cf8_conf2;
+extern const struct pci_bus_operations pci_cf8_conf2;
 
 #if MMCONF_SUPPORT==1
-const struct pci_bus_operations pci_ops_mmconf;
+extern const struct pci_bus_operations pci_ops_mmconf;
 #endif
 
 void pci_set_method(device_t dev);

src/config/Config.lb

@@ -10,7 +10,7 @@ makedefine GCC ?= $(CC)
 makedefine GCC_INC_DIR := $(shell LC_ALL=C $(GCC) -print-search-dirs | sed -ne "s/install: \(.*\)/\1include/gp")
 
 makedefine CPPFLAGS := -I$(TOP)/src/include -I$(TOP)/src/arch/$(ARCH)/include -I$(GCC_INC_DIR) $(CPUFLAGS)
-makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -fno-builtin  -Wall
+makedefine CFLAGS := $(CPU_OPT) $(DISTRO_CFLAGS) $(CPPFLAGS) -Os -nostdinc -nostdlib -Wall -Wundef -Wstrict-prototypes -Wno-trigraphs -Werror-implicit-function-declaration -Wstrict-aliasing -Wshadow -fno-common -ffreestanding -fno-builtin -fomit-frame-pointer
 
 if ASSEMBLER_DEBUG
 makedefine DEBUG_CFLAGS := -g -dA -fverbose-asm

src/config/Options.lb

@@ -146,7 +146,7 @@ define COREBOOT_COMPILER
 	comment "Build compiler"
 end
 define COREBOOT_LINKER
-	default "$(shell  $(CC) -Wl,--version 2>&1 | grep version | tail -n 1)"
+	default "$(shell  $(CC) -Wl,--version 2>&1 | grep \" ld\")"
 	export always
 	format "\"%s\""
 	comment "Build linker"

src/drivers/generic/debug/debug_dev.c

@@ -5,6 +5,8 @@
 #include <device/pci_ids.h>
 #include <device/pci_ops.h>
 #include <cpu/x86/msr.h>
+#include <part/hard_reset.h>
+#include <delay.h>
 #include "chip.h"
 
 static void print_pci_regs(struct device *dev)

src/include/cpu/x86/smm.h

@@ -251,6 +251,9 @@ typedef struct {
 
 
 /* SMI handler function prototypes */
+void io_trap_handler(int smif);
 int southbridge_io_trap_handler(int smif);
 int mainboard_io_trap_handler(int smif);
 
+void southbridge_smi_handler(unsigned int node, smm_state_save_area_t *state_save);
+

src/include/device/device.h

@@ -102,26 +102,26 @@ extern struct device	*all_devices;	/* list of all devices */
 
 
 /* Generic device interface functions */
-extern device_t alloc_dev(struct bus *parent, struct device_path *path);
+device_t alloc_dev(struct bus *parent, struct device_path *path);
-extern void dev_enumerate(void);
+void dev_enumerate(void);
-extern void dev_configure(void);
+void dev_configure(void);
-extern void dev_enable(void);
+void dev_enable(void);
-extern void dev_initialize(void);
+void dev_initialize(void);
-extern void dev_optimize(void);
+void dev_optimize(void);
 
 /* Generic device helper functions */
-extern int reset_bus(struct bus *bus);
+int reset_bus(struct bus *bus);
-extern unsigned int scan_bus(struct device *bus, unsigned int max);
+unsigned int scan_bus(struct device *bus, unsigned int max);
-extern void compute_allocate_resource(struct bus *bus, struct resource *bridge,
+void compute_allocate_resource(struct bus *bus, struct resource *bridge,
 	unsigned long type_mask, unsigned long type);
-extern void assign_resources(struct bus *bus);
+void assign_resources(struct bus *bus);
-extern void enable_resources(struct device *dev);
+void enable_resources(struct device *dev);
-extern void enumerate_static_device(void);
+void enumerate_static_device(void);
-extern void enumerate_static_devices(void);
+void enumerate_static_devices(void);
-extern const char *dev_path(device_t dev);
+const char *dev_path(device_t dev);
 const char *bus_path(struct bus *bus);
-extern void dev_set_enabled(device_t dev, int enable);
+void dev_set_enabled(device_t dev, int enable);
-extern void disable_children(struct bus *bus);
+void disable_children(struct bus *bus);
 
 /* Helper functions */
 device_t find_dev_path(struct bus *parent, struct device_path *path);
@@ -138,12 +138,12 @@ device_t dev_find_slot_on_smbus (unsigned int bus, unsigned int addr);
 #define DEVICE_IO_ALIGN 16 
 #define DEVICE_MEM_ALIGN 4096
 
-struct device_operations default_dev_ops_root;
+extern struct device_operations default_dev_ops_root;
-extern void root_dev_read_resources(device_t dev);
+void root_dev_read_resources(device_t dev);
-extern void root_dev_set_resources(device_t dev);
+void root_dev_set_resources(device_t dev);
-extern unsigned int scan_static_bus(device_t bus, unsigned int max);
+unsigned int scan_static_bus(device_t bus, unsigned int max);
-extern void enable_childrens_resources(device_t dev);
+void enable_childrens_resources(device_t dev);
-extern void root_dev_enable_resources(device_t dev);
+void root_dev_enable_resources(device_t dev);
-extern unsigned int root_dev_scan_bus(device_t root, unsigned int max);
+unsigned int root_dev_scan_bus(device_t root, unsigned int max);
-extern void root_dev_init(device_t dev);
+void root_dev_init(device_t dev);
 #endif /* DEVICE_H */

src/include/device/pnp.h

@@ -21,7 +21,7 @@ void pnp_set_resources(device_t dev);
 void pnp_enable_resources(device_t dev);
 void pnp_enable(device_t dev);
 
-struct device_operations pnp_ops;
+extern struct device_operations pnp_ops;
 
 /* PNP helper operations */
 

src/mainboard/amd/serengeti_cheetah_fam10/cache_as_ram_auto.c

@@ -69,9 +69,13 @@ static void post_code(u8 value) {
 #include "northbridge/amd/amdfam10/amdfam10.h"
 #endif
 
-
 #include "cpu/x86/lapic/boot_cpu.c"
 #include "northbridge/amd/amdfam10/reset_test.c"
+
+#include <console/loglevel.h>
+void die(const char *msg);
+int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
+#define printk_emerg(fmt, arg...)   do_printk(BIOS_EMERG   ,fmt, ##arg)
 #include "cpu/x86/bist.h"
 
 

src/mainboard/dell/s1850/chip.h

@@ -1,4 +1,4 @@
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 
 struct mainboard_config {
 	int nothing;

src/mainboard/intel/jarrell/chip.h

@@ -1,4 +1,4 @@
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 
 struct mainboard_config {
 	int nothing;

src/mainboard/intel/mtarvon/chip.h

@@ -18,7 +18,7 @@
  *
  */
 
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 
 struct mainboard_config {
 	int nothing;

src/mainboard/intel/truxton/chip.h

@@ -18,7 +18,7 @@
  *
  */
 
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 
 struct mainboard_config {
 	int nothing;

src/mainboard/intel/xe7501devkit/reset.c

@@ -1,3 +1,4 @@
+void i82801ca_hard_reset(void);
 
 void hard_reset(void)
 {

src/mainboard/kontron/986lcd-m/chip.h

@@ -19,7 +19,7 @@
  * MA 02110-1301 USA
  */
 
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 struct mainboard_config {
 	int nothing;
 };

src/mainboard/supermicro/x6dai_g/chip.h

@@ -1,4 +1,4 @@
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 
 struct mainboard_config {
 	int nothing;

src/mainboard/supermicro/x6dai_g/mainboard.c

@@ -1,7 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-struct chip_operations supermicro_x6dai_g_ops = {
+struct chip_operations mainboard_ops = {
 	CHIP_NAME("Supermicro X6DAi-G Mainboard")
 };
 

src/mainboard/supermicro/x6dhe_g/chip.h

@@ -1,4 +1,4 @@
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 
 struct mainboard_config {
 	int nothing;

src/mainboard/supermicro/x6dhe_g/mainboard.c

@@ -1,7 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-struct chip_operations supermicro_x6dhe_g_ops = {
+struct chip_operations mainboard_ops = {
     CHIP_NAME("Supermicro X6DHE-G Mainboard")
 };
 

src/mainboard/supermicro/x6dhe_g2/chip.h

@@ -1,4 +1,4 @@
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 
 struct mainboard_config {
 	int nothing;

src/mainboard/supermicro/x6dhe_g2/mainboard.c

@@ -1,7 +1,7 @@
 #include <device/device.h>
 #include "chip.h"
 
-struct chip_operations supermicro_x6dhe_g2_ops = {
+struct chip_operations mainboard_ops = {
     CHIP_NAME("Supermicro X6DHE-G2 Mainboard")
 };
 

src/mainboard/supermicro/x6dhr_ig/chip.h

@@ -1,4 +1,4 @@
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 
 struct mainboard_config {
 	int nothing;

src/mainboard/supermicro/x6dhr_ig2/chip.h

@@ -1,4 +1,4 @@
-struct chip_operations mainboard_ops;
+extern struct chip_operations mainboard_ops;
 
 struct mainboard_config {
 	int nothing;

src/mainboard/tyan/s2735/reset.c

@@ -1,3 +1,4 @@
+void i82801er_hard_reset(void);
 
 void hard_reset(void)
 {

src/mainboard/via/epia-m/Options.lb

@@ -137,5 +137,9 @@ default HOSTCC="gcc"
 ##
 default CONFIG_MAX_PCI_BUSES = 5	 
 
+default  MAXIMUM_CONSOLE_LOGLEVEL=8
+default  DEFAULT_CONSOLE_LOGLEVEL=8
+default  CONFIG_CONSOLE_SERIAL8250=1
+
 end
 

src/mainboard/via/epia-m/mainboard.c

@@ -5,6 +5,7 @@
 #include <device/pci_ops.h>
 #include <arch/io.h>
 #include "chip.h"
+#include "vgachip.h"
 
 void vga_enable_console();
 

src/mainboard/via/epia-m/vgachip.h

@@ -7,4 +7,9 @@ struct pc80_vgabios_config {
 	int nothing;
 };
 
+void vga_enable_console(void);
+void do_vgabios(void);
+void setup_realmode_idt(void);
+void write_protect_vgabios(void);
+
 #endif /* _PC80_VGABIOS */

src/northbridge/amd/amdfam10/reset_test.c

@@ -19,6 +19,7 @@
 
 #include <stdint.h>
 #include <cpu/x86/lapic.h>
+#include "amdfam10.h"
 
 #define NODE_ID		0x60
 #define HT_INIT_CONTROL	0x6c

src/northbridge/amd/amdk8/northbridge.c

@@ -19,8 +19,8 @@
 
 #include <cpu/x86/lapic.h>
 
-#if CONFIG_LOGICAL_CPUS==1
 #include <cpu/amd/dualcore.h>
+#if CONFIG_LOGICAL_CPUS==1
 #include <pc80/mc146818rtc.h>
 #endif
 
@@ -30,9 +30,7 @@
 
 #include "amdk8.h"
 
-#if HW_MEM_HOLE_SIZEK != 0
 #include <cpu/amd/model_fxx_rev.h>
-#endif
 
 #include <cpu/amd/amdk8_sysconf.h>
 

src/northbridge/intel/e7501/northbridge.c

@@ -3,6 +3,7 @@
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
+#include <cpu/cpu.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>

src/northbridge/intel/i82830/northbridge.c

@@ -24,6 +24,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <cpu/cpu.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>

src/northbridge/intel/i855pm/northbridge.c

@@ -4,6 +4,7 @@
 #include <device/device.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
+#include <cpu/cpu.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>

src/northbridge/via/vt8601/northbridge.c

@@ -5,6 +5,7 @@
 #include <device/pci.h>
 #include <device/pci_ids.h>
 #include <device/hypertransport.h>
+#include <cpu/cpu.h>
 #include <stdlib.h>
 #include <string.h>
 #include <bitops.h>

src/northbridge/via/vt8623/northbridge.h

@@ -1,6 +1,12 @@
 #ifndef NORTHBRIDGE_VIA_VT8623_H
 #define NORTHBRIDGE_VIA_VT8623_H
 
-extern unsigned int vt8623_scan_root_bus(device_t root, unsigned int max);
+unsigned int vt8623_scan_root_bus(device_t root, unsigned int max);
+
+void vga_enable_console(void);
+void do_vgabios(void);
+void setup_realmode_idt(void);
+void write_protect_vgabios(void);
+
 
 #endif /* NORTHBRIDGE_VIA_VT8623_H */

src/southbridge/intel/pxhd/chip.h

@@ -2,4 +2,5 @@ struct southbridge_intel_pxhd_config
 {
 	/* nothing */
 };
-struct chip_operations southbridge_intel_pxhd_ops;
+
+extern struct chip_operations southbridge_intel_pxhd_ops;

src/southbridge/nvidia/mcp55/mcp55_early_setup_car.c

@@ -19,6 +19,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+static int set_ht_link_buffer_counts_chain(uint8_t ht_c_num, unsigned vendorid, unsigned val);
+
 static int set_ht_link_mcp55(uint8_t ht_c_num)
 {
 	unsigned vendorid = 0x10de;

targets/digitallogic/msm586seg/Config-abuild.lb

@@ -1,24 +1,16 @@
-target digitallogic_msm586seg
+target VENDOR_MAINBOARD
-mainboard digitallogic/msm586seg
+mainboard VENDOR/MAINBOARD
 
-
+option CC="CROSSCC"
-
+option CROSS_COMPILE="CROSS_PREFIX"
-option DEFAULT_CONSOLE_LOGLEVEL=9
+option HOSTCC="CROSS_HOSTCC"
-option MAXIMUM_CONSOLE_LOGLEVEL=9
-option CONFIG_COMPRESS=0
 
 __COMPRESSION__
 
-option CONFIG_CONSOLE_VGA=1
-
 romimage "fallback" 
 	option FALLBACK_SIZE = 256 * 1024
-#	option ROM_SIZE=512*1024
-#	option ROM_SECTION_SIZE=512*1024
 	option USE_FALLBACK_IMAGE=1
-#	option ROM_IMAGE_SIZE=32 * 1024 # 0x8000
+	option ROM_IMAGE_SIZE= 128 * 1024
-	option ROM_IMAGE_SIZE=128 * 1024 # 0x10000
-#	option ROM_IMAGE_SIZE=512 * 1024 # 0x10000
 	option COREBOOT_EXTRA_VERSION=".0Fallback"
 	payload __PAYLOAD__
 end

targets/gigabyte/ga_2761gxdk/Config-abuild.lb

@@ -18,8 +18,13 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-target gigabyte_ga_2761gxdk
+
-mainboard gigabyte/ga_2761gxdk
+target VENDOR_MAINBOARD
+mainboard VENDOR/MAINBOARD
+
+option CC="CROSSCC"
+option CROSS_COMPILE="CROSS_PREFIX"
+option HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 

targets/iei/juki-511p/Config-abuild.lb

@@ -1,7 +1,9 @@
-# abuild config file for JUKI-511P 
+target VENDOR_MAINBOARD
+mainboard VENDOR/MAINBOARD
 
-target iei_juki-511p
+option CC="CROSSCC"
-mainboard iei/juki-511p
+option CROSS_COMPILE="CROSS_PREFIX"
+option HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 

targets/msi/ms7260/Config-abuild.lb

@@ -18,8 +18,12 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-target msi_ms7260
+target VENDOR_MAINBOARD
-mainboard msi/ms7260
+mainboard VENDOR/MAINBOARD
+
+option CC="CROSSCC"
+option CROSS_COMPILE="CROSS_PREFIX"
+option HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 

targets/rca/rm4100/Config-abuild.lb

@@ -18,8 +18,14 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-target rca_rm4100
+target VENDOR_MAINBOARD
-mainboard rca/rm4100
+mainboard VENDOR/MAINBOARD
+
+option CC="CROSSCC"
+option CROSS_COMPILE="CROSS_PREFIX"
+option HOSTCC="CROSS_HOSTCC"
+
+__COMPRESSION__
 
 romimage "fallback"
 	option USE_FALLBACK_IMAGE = 1

targets/technologic/ts5300/Config-abuild.lb

@@ -1,20 +1,17 @@
-target technologic_ts5300
+target VENDOR_MAINBOARD
-mainboard technologic/ts5300
+mainboard VENDOR/MAINBOARD
 
-option DEFAULT_CONSOLE_LOGLEVEL=9
+option CC="CROSSCC"
-option MAXIMUM_CONSOLE_LOGLEVEL=9
+option CROSS_COMPILE="CROSS_PREFIX"
-option CONFIG_COMPRESS=0
+option HOSTCC="CROSS_HOSTCC"
 
 __COMPRESSION__
 
 romimage "fallback" 
 	option FALLBACK_SIZE = 256 * 1024
-#	option ROM_SIZE=512*1024
-#	option ROM_SECTION_SIZE=512*1024
 	option USE_FALLBACK_IMAGE=1
-#	option ROM_IMAGE_SIZE=32 * 1024 # 0x8000
 	option ROM_IMAGE_SIZE=128 * 1024 # 0x10000
-	option COREBOOT_EXTRA_VERSION=".0Fallback"
+	option COREBOOT_EXTRA_VERSION=".0-Fallback"
 	payload __PAYLOAD__
 end
 

targets/thomson/ip1000/Config-abuild.lb

@@ -18,8 +18,14 @@
 ## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
 ##
 
-target thomson_ip1000
+target VENDOR_MAINBOARD
-mainboard thomson/ip1000
+mainboard VENDOR/MAINBOARD
+
+option CC="CROSSCC"
+option CROSS_COMPILE="CROSS_PREFIX"
+option HOSTCC="CROSS_HOSTCC"
+
+__COMPRESSION__
 
 romimage "fallback"
 	option USE_FALLBACK_IMAGE = 1

targets/via/epia-m/Config-abuild.lb

@@ -1,32 +1,14 @@
-# abuild config file for EPIA-M
+target VENDOR_MAINBOARD
+mainboard VENDOR/MAINBOARD
 
-target via_epia-m
+option CC="CROSSCC"
-mainboard via/epia-m
+option CROSS_COMPILE="CROSS_PREFIX"
-
+option HOSTCC="CROSS_HOSTCC"
-option  MAXIMUM_CONSOLE_LOGLEVEL=8
-option  DEFAULT_CONSOLE_LOGLEVEL=8
-option  CONFIG_CONSOLE_SERIAL8250=1
 
 __COMPRESSION__
 
 option ROM_SIZE=256*1024
 
-option HAVE_OPTION_TABLE=1
-option CONFIG_ROM_PAYLOAD=1
-option HAVE_FALLBACK_BOOT=1
-
-###
-### Compute the location and size of where this firmware image
-### (coreboot plus bootloader) will live in the boot rom chip.
-###
-option FALLBACK_SIZE=131072
-
-## Coreboot C code runs at this location in RAM
-option _RAMBASE=0x00004000
-
-#
-# Via EPIA M
-#
 romimage "normal"
 	option USE_FALLBACK_IMAGE=0
 	option ROM_IMAGE_SIZE=64*1024