uart8250: Move under drivers/uart
Change-Id: Ic65ffaaa092330ed68d891e4a09a8b86cdc04a3a Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/5236 Tested-by: build bot (Jenkins)
This commit is contained in:
Kyösti Mälkki
@@ -5,6 +5,18 @@ bootblock-y += util.c
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smm-y += util.c
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endif
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ifeq ($(CONFIG_CONSOLE_SERIAL8250),y)
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romstage-y += uart8250io.c
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ramstage-y += uart8250io.c
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smm-y += uart8250io.c
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endif
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ifeq ($(CONFIG_CONSOLE_SERIAL8250MEM),y)
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romstage-y += uart8250mem.c
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ramstage-y += uart8250mem.c
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smm-y += uart8250mem.c
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endif
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ifeq ($(CONFIG_CONSOLE_SERIAL_UART),y)
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ifeq ($(CONFIG_DRIVERS_UART_PL011),y)
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131
src/drivers/uart/uart8250io.c
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131
src/drivers/uart/uart8250io.c
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@@ -0,0 +1,131 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Eric Biederman
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* Copyright (C) 2006-2010 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/uart.h>
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#include <trace.h>
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#include "uart8250reg.h"
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/* Should support 8250, 16450, 16550, 16550A type UARTs */
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/* Nominal values only, good for the range of choices Kconfig offers for
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* set of standard baudrates.
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*/
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#define BAUDRATE_REFCLK (115200)
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#define BAUDRATE_OVERSAMPLE (1)
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/* Expected character delay at 1200bps is 9ms for a working UART
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* and no flow-control. Assume UART as stuck if shift register
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* or FIFO takes more than 50ms per character to appear empty.
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*
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* Estimated that inb() from UART takes 1 microsecond.
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*/
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#define SINGLE_CHAR_TIMEOUT (50 * 1000)
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#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
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static int uart8250_can_tx_byte(unsigned base_port)
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{
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return inb(base_port + UART_LSR) & UART_LSR_THRE;
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}
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static void uart8250_tx_byte(unsigned base_port, unsigned char data)
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{
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unsigned long int i = SINGLE_CHAR_TIMEOUT;
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while (i-- && !uart8250_can_tx_byte(base_port));
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outb(data, base_port + UART_TBR);
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}
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static void uart8250_tx_flush(unsigned base_port)
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{
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unsigned long int i = FIFO_TIMEOUT;
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while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT));
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}
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static int uart8250_can_rx_byte(unsigned base_port)
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{
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return inb(base_port + UART_LSR) & UART_LSR_DR;
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}
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static unsigned char uart8250_rx_byte(unsigned base_port)
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{
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unsigned long int i = SINGLE_CHAR_TIMEOUT;
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while (i-- && !uart8250_can_rx_byte(base_port));
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if (i)
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return inb(base_port + UART_RBR);
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else
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return 0x0;
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}
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static void uart8250_init(unsigned base_port, unsigned divisor)
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{
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DISABLE_TRACE;
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/* Disable interrupts */
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outb(0x0, base_port + UART_IER);
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/* Enable FIFOs */
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outb(UART_FCR_FIFO_EN, base_port + UART_FCR);
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/* assert DTR and RTS so the other end is happy */
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outb(UART_MCR_DTR | UART_MCR_RTS, base_port + UART_MCR);
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/* DLAB on */
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outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR);
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/* Set Baud Rate Divisor. 12 ==> 9600 Baud */
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outb(divisor & 0xFF, base_port + UART_DLL);
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outb((divisor >> 8) & 0xFF, base_port + UART_DLM);
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/* Set to 3 for 8N1 */
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outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
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ENABLE_TRACE;
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}
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/* FIXME: Needs uart index from Kconfig.
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* Already use array as a work-around for ROMCC.
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*/
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static const unsigned bases[1] = { CONFIG_TTYS0_BASE };
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void uart_init(void)
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{
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unsigned int div;
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div = uart_baudrate_divisor(default_baudrate(), BAUDRATE_REFCLK,
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BAUDRATE_OVERSAMPLE);
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uart8250_init(bases[0], div);
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}
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void uart_tx_byte(unsigned char data)
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{
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uart8250_tx_byte(bases[0], data);
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}
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unsigned char uart_rx_byte(void)
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{
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return uart8250_rx_byte(bases[0]);
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}
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int uart_can_rx_byte(void)
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{
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return uart8250_can_rx_byte(bases[0]);
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}
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void uart_tx_flush(void)
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{
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uart8250_tx_flush(bases[0]);
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}
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133
src/drivers/uart/uart8250mem.c
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133
src/drivers/uart/uart8250mem.c
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@@ -0,0 +1,133 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Eric Biederman
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* Copyright (C) 2006-2010 coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <arch/io.h>
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#include <console/uart.h>
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#include <device/device.h>
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#include <delay.h>
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#include "uart8250reg.h"
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/* Should support 8250, 16450, 16550, 16550A type UARTs */
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/* Expected character delay at 1200bps is 9ms for a working UART
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* and no flow-control. Assume UART as stuck if shift register
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* or FIFO takes more than 50ms per character to appear empty.
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*/
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#define SINGLE_CHAR_TIMEOUT (50 * 1000)
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#define FIFO_TIMEOUT (16 * SINGLE_CHAR_TIMEOUT)
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static int uart8250_mem_can_tx_byte(unsigned base_port)
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{
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return read8(base_port + UART_LSR) & UART_LSR_THRE;
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}
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static void uart8250_mem_tx_byte(unsigned base_port, unsigned char data)
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{
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unsigned long int i = SINGLE_CHAR_TIMEOUT;
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while(i-- && !uart8250_mem_can_tx_byte(base_port))
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udelay(1);
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write8(base_port + UART_TBR, data);
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}
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static void uart8250_mem_tx_flush(unsigned base_port)
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{
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unsigned long int i = FIFO_TIMEOUT;
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while(i-- && !(read8(base_port + UART_LSR) & UART_LSR_TEMT))
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udelay(1);
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}
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static int uart8250_mem_can_rx_byte(unsigned base_port)
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{
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return read8(base_port + UART_LSR) & UART_LSR_DR;
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}
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static unsigned char uart8250_mem_rx_byte(unsigned base_port)
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{
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unsigned long int i = SINGLE_CHAR_TIMEOUT;
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while(i-- && !uart8250_mem_can_rx_byte(base_port))
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udelay(1);
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if (i)
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return read8(base_port + UART_RBR);
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else
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return 0x0;
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}
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static void uart8250_mem_init(unsigned base_port, unsigned divisor)
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{
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/* Disable interrupts */
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write8(base_port + UART_IER, 0x0);
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/* Enable FIFOs */
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write8(base_port + UART_FCR, UART_FCR_FIFO_EN);
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/* Assert DTR and RTS so the other end is happy */
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write8(base_port + UART_MCR, UART_MCR_DTR | UART_MCR_RTS);
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/* DLAB on */
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write8(base_port + UART_LCR, UART_LCR_DLAB | CONFIG_TTYS0_LCS);
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write8(base_port + UART_DLL, divisor & 0xFF);
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write8(base_port + UART_DLM, (divisor >> 8) & 0xFF);
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/* Set to 3 for 8N1 */
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write8(base_port + UART_LCR, CONFIG_TTYS0_LCS);
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}
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void uart_init(void)
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{
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u32 base = uart_platform_base(0);
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if (!base)
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return;
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unsigned int div;
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div = uart_baudrate_divisor(default_baudrate(), uart_platform_refclk(), 16);
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uart8250_mem_init(base, div);
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}
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void uart_tx_byte(unsigned char data)
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{
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u32 base = uart_platform_base(0);
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if (!base)
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return;
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uart8250_mem_tx_byte(base, data);
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}
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unsigned char uart_rx_byte(void)
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{
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u32 base = uart_platform_base(0);
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if (!base)
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return 0xff;
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return uart8250_mem_rx_byte(base);
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}
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int uart_can_rx_byte(void)
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{
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u32 base = uart_platform_base(0);
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if (!base)
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return 0;
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return uart8250_mem_can_rx_byte(base);
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}
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void uart_tx_flush(void)
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{
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u32 base = uart_platform_base(0);
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if (!base)
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return;
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uart8250_mem_tx_flush(base);
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}
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108
src/drivers/uart/uart8250reg.h
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108
src/drivers/uart/uart8250reg.h
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@@ -0,0 +1,108 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2003 Eric Biederman
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef UART8250REG_H
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#define UART8250REG_H
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/* Data */
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#define UART_RBR 0x00
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#define UART_TBR 0x00
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/* Control */
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#define UART_IER 0x01
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#define UART_IER_MSI 0x08 /* Enable Modem status interrupt */
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#define UART_IER_RLSI 0x04 /* Enable receiver line status interrupt */
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#define UART_IER_THRI 0x02 /* Enable Transmitter holding register int. */
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#define UART_IER_RDI 0x01 /* Enable receiver data interrupt */
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#define UART_IIR 0x02
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#define UART_IIR_NO_INT 0x01 /* No interrupts pending */
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#define UART_IIR_ID 0x06 /* Mask for the interrupt ID */
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#define UART_IIR_MSI 0x00 /* Modem status interrupt */
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#define UART_IIR_THRI 0x02 /* Transmitter holding register empty */
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#define UART_IIR_RDI 0x04 /* Receiver data interrupt */
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#define UART_IIR_RLSI 0x06 /* Receiver line status interrupt */
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#define UART_FCR 0x02
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#define UART_FCR_FIFO_EN 0x01 /* Fifo enable */
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#define UART_FCR_CLEAR_RCVR 0x02 /* Clear the RCVR FIFO */
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#define UART_FCR_CLEAR_XMIT 0x04 /* Clear the XMIT FIFO */
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#define UART_FCR_DMA_SELECT 0x08 /* For DMA applications */
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#define UART_FCR_TRIGGER_MASK 0xC0 /* Mask for the FIFO trigger range */
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#define UART_FCR_TRIGGER_1 0x00 /* Mask for trigger set at 1 */
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#define UART_FCR_TRIGGER_4 0x40 /* Mask for trigger set at 4 */
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#define UART_FCR_TRIGGER_8 0x80 /* Mask for trigger set at 8 */
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#define UART_FCR_TRIGGER_14 0xC0 /* Mask for trigger set at 14 */
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#define UART_FCR_RXSR 0x02 /* Receiver soft reset */
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#define UART_FCR_TXSR 0x04 /* Transmitter soft reset */
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#define UART_LCR 0x03
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#define UART_LCR_WLS_MSK 0x03 /* character length select mask */
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#define UART_LCR_WLS_5 0x00 /* 5 bit character length */
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#define UART_LCR_WLS_6 0x01 /* 6 bit character length */
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#define UART_LCR_WLS_7 0x02 /* 7 bit character length */
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#define UART_LCR_WLS_8 0x03 /* 8 bit character length */
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#define UART_LCR_STB 0x04 /* Number of stop Bits, off = 1, on = 1.5 or 2) */
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#define UART_LCR_PEN 0x08 /* Parity enable */
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#define UART_LCR_EPS 0x10 /* Even Parity Select */
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#define UART_LCR_STKP 0x20 /* Stick Parity */
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#define UART_LCR_SBRK 0x40 /* Set Break */
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#define UART_LCR_BKSE 0x80 /* Bank select enable */
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#define UART_LCR_DLAB 0x80 /* Divisor latch access bit */
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#define UART_MCR 0x04
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#define UART_MCR_DTR 0x01 /* DTR */
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#define UART_MCR_RTS 0x02 /* RTS */
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#define UART_MCR_OUT1 0x04 /* Out 1 */
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#define UART_MCR_OUT2 0x08 /* Out 2 */
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#define UART_MCR_LOOP 0x10 /* Enable loopback test mode */
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#define UART_MCR_DMA_EN 0x04
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#define UART_MCR_TX_DFR 0x08
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#define UART_DLL 0x00
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#define UART_DLM 0x01
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/* Status */
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#define UART_LSR 0x05
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#define UART_LSR_DR 0x01 /* Data ready */
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#define UART_LSR_OE 0x02 /* Overrun */
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#define UART_LSR_PE 0x04 /* Parity error */
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#define UART_LSR_FE 0x08 /* Framing error */
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#define UART_LSR_BI 0x10 /* Break */
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#define UART_LSR_THRE 0x20 /* Xmit holding register empty */
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#define UART_LSR_TEMT 0x40 /* Xmitter empty */
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#define UART_LSR_ERR 0x80 /* Error */
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#define UART_MSR 0x06
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#define UART_MSR_DCD 0x80 /* Data Carrier Detect */
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#define UART_MSR_RI 0x40 /* Ring Indicator */
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#define UART_MSR_DSR 0x20 /* Data Set Ready */
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#define UART_MSR_CTS 0x10 /* Clear to Send */
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#define UART_MSR_DDCD 0x08 /* Delta DCD */
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#define UART_MSR_TERI 0x04 /* Trailing edge ring indicator */
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#define UART_MSR_DDSR 0x02 /* Delta DSR */
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#define UART_MSR_DCTS 0x01 /* Delta CTS */
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#define UART_SCR 0x07
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#define UART_SPR 0x07
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#endif /* UART8250REG_H */
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