From beb8d7b318d49b578191c1259e9fbe5abaa58936 Mon Sep 17 00:00:00 2001 From: Tim Crawford Date: Fri, 30 Aug 2024 11:36:46 -0600 Subject: [PATCH] mb/system76/mtl: Enable EnableTcssCovTypeA configs Change-Id: Ide0d313257e6778664a9d5dc2efb38264e5cac69 Signed-off-by: Tim Crawford --- src/mainboard/system76/mtl/variants/darp10/ramstage.c | 2 +- src/mainboard/system76/mtl/variants/lemp13/ramstage.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/system76/mtl/variants/darp10/ramstage.c b/src/mainboard/system76/mtl/variants/darp10/ramstage.c index 993a48fd2b..63dfb35151 100644 --- a/src/mainboard/system76/mtl/variants/darp10/ramstage.c +++ b/src/mainboard/system76/mtl/variants/darp10/ramstage.c @@ -9,7 +9,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // BIT 4:5 is reserved // BIT 6 is orientational // BIT 7 is enable - //params->EnableTcssCovTypeA[1] = 0x82; + params->EnableTcssCovTypeA[1] = 0x82; // XXX: Enabling C10 reporting causes system to constantly enter and // exit opportunistic suspend when idle. diff --git a/src/mainboard/system76/mtl/variants/lemp13/ramstage.c b/src/mainboard/system76/mtl/variants/lemp13/ramstage.c index 5bec8beb60..26a52e4c88 100644 --- a/src/mainboard/system76/mtl/variants/lemp13/ramstage.c +++ b/src/mainboard/system76/mtl/variants/lemp13/ramstage.c @@ -11,8 +11,8 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) // BIT 4:5 is reserved // BIT 6 is orientational // BIT 7 is enable - //params->EnableTcssCovTypeA[1] = 0x81; - //params->EnableTcssCovTypeA[3] = 0x85; + params->EnableTcssCovTypeA[1] = 0x81; + params->EnableTcssCovTypeA[3] = 0x85; // Disable reporting CPU C10 state over eSPI (causes LED flicker). params->PchEspiHostC10ReportEnable = 0;