minor reformat
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@@ -17,7 +17,6 @@ static unsigned long resk(uint64_t value)
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return resultk;
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}
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#if 1
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static unsigned fixed_mtrr_index(unsigned long addrk)
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{
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unsigned index;
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@@ -34,7 +33,6 @@ static unsigned fixed_mtrr_index(unsigned long addrk)
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return index;
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}
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static unsigned int mtrr_msr[] = {
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MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
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MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
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@@ -98,14 +96,11 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
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return;
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}
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printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
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start_mtrr, last_mtrr);
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start_mtrr, last_mtrr);
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set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
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}
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#endif
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void amd_setup_mtrrs(void)
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{
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struct mem_state state;
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@@ -120,7 +115,7 @@ void amd_setup_mtrrs(void)
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printk_debug("\n");
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/* Initialized the fixed_mtrrs to uncached */
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printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
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0, NUM_FIXED_RANGES);
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0, NUM_FIXED_RANGES);
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set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
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/* Except for the PCI MMIO hole just before 4GB there are no
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