minor reformat

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1892 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

src/console/vga_console.c

@@ -12,7 +12,9 @@
 
 //extern void beep(int ms);
 
-static char *vidmem;		/* The video buffer, should be replaced by symbol in ldscript.ld */
+/* The video buffer, should be replaced by symbol in ldscript.ld */
+static char *vidmem;
+
 int vga_line, vga_col;
 
 extern int vga_inited; // it will be changed in pci_rom.c

src/cpu/amd/mtrr/amd_mtrr.c

@@ -17,7 +17,6 @@ static unsigned long resk(uint64_t value)
 	return resultk;
 }
 
-#if 1
 static unsigned fixed_mtrr_index(unsigned long addrk)
 {
 	unsigned index;
@@ -34,7 +33,6 @@ static unsigned fixed_mtrr_index(unsigned long addrk)
 	return index;
 }
 
-
 static unsigned int mtrr_msr[] = {
 	MTRRfix64K_00000_MSR, MTRRfix16K_80000_MSR, MTRRfix16K_A0000_MSR,
 	MTRRfix4K_C0000_MSR, MTRRfix4K_C8000_MSR, MTRRfix4K_D0000_MSR, MTRRfix4K_D8000_MSR,
@@ -98,14 +96,11 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
 		return;
 	}
 	printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
-		start_mtrr, last_mtrr);
+		     start_mtrr, last_mtrr);
 	set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
 	
 }
 
-
-#endif
-
 void amd_setup_mtrrs(void)
 {
 	struct mem_state state;
@@ -120,7 +115,7 @@ void amd_setup_mtrrs(void)
 	printk_debug("\n");
 	/* Initialized the fixed_mtrrs to uncached */
 	printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n", 
-		0, NUM_FIXED_RANGES);
+		     0, NUM_FIXED_RANGES);
 	set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
 
 	/* Except for the PCI MMIO hole just before 4GB there are no

src/cpu/x86/mtrr/earlymtrr.c

@@ -37,8 +37,8 @@ static void disable_var_mtrr(unsigned reg)
 	wrmsr(MTRRphysMask_MSR(reg), zero);
 }
 
-static void set_var_mtrr(
+static void set_var_mtrr(unsigned reg, unsigned base, unsigned size,
-	unsigned reg, unsigned base, unsigned size, unsigned type)
+			 unsigned type)
 
 {
 	/* Bit Bit 32-35 of MTRRphysMask should be set to 1 */
@@ -59,7 +59,6 @@ static void cache_lbmem(int type)
 	enable_cache();
 }
 
-
 /* the fixed and variable MTTRs are power-up with random values,
  * clear them to MTRR_TYPE_UNCACHEABLE for safty.
  */
@@ -77,7 +76,7 @@ static void do_early_mtrr_init(const unsigned long *mtrr_msrs)
 	msr.lo = 0;
 	msr.hi = 0;
 	unsigned long msr_nr;
-	for(msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
+	for (msr_addr = mtrr_msrs; (msr_nr = *msr_addr); msr_addr++) {
 		wrmsr(msr_nr, msr);
 	}
 

src/devices/emulator/biosemu.c

@@ -46,9 +46,6 @@ int run_bios_int(int num)
 	X86_CS = MEM_RW((num << 2) + 2);
 	X86_IP = MEM_RW(num << 2);
 
-	//printk_debug("%s: INT %x CS:IP = %x:%x\n", __FUNCTION__,
-	//	     num, MEM_RW((num << 2) + 2), MEM_RW(num << 2));
-
 	return 1;
 }
 
@@ -116,7 +113,7 @@ void do_int(int num)
 {
 	int ret = 0;
 
-	//printk_debug("int%x vector at %x\n", num, getIntVect(num));
+	printk_debug("int%x vector at %x\n", num, getIntVect(num));
 
 	switch (num) {
 #ifndef _PC
@@ -156,10 +153,6 @@ void do_int(int num)
 	if (!ret)
 		ret = run_bios_int(num);
 
-	if (!ret) {
-		printk_debug("\nint%x: not implemented\n", num);
-		x86emu_dump_xregs();
-	}
 }
 #define SYS_BIOS 0xf0000
 /*

src/devices/pci_device.c

@@ -218,7 +218,8 @@ static void pci_get_rom_resource(struct device *dev, unsigned long index)
 	unsigned long value;
 	resource_t  moving, limit;
 
-        if ((dev->on_mainboard) && (dev->rom_address == 0)) { //skip it if rom_address is not set in MB Config.lb
+        if ((dev->on_mainboard) && (dev->rom_address == 0)) {
+		//skip it if rom_address is not set in MB Config.lb
                 return;
         }
 

src/devices/pci_rom.c

@@ -13,18 +13,19 @@ struct rom_header * pci_rom_probe(struct device *dev)
 	rom_address = pci_read_config32(dev, PCI_ROM_ADDRESS);
 
 	if (rom_address == 0x00000000 || rom_address == 0xffffffff) {
-		if(dev->on_mainboard && (dev->rom_address!=0) ) { // in case some device PCI_ROM_ADDRESS can not be set 
+		if (dev->on_mainboard && (dev->rom_address!=0) ) {
+			// in case some device PCI_ROM_ADDRESS can not be set 
 			rom_address = dev->rom_address;
-		}
+		} else {
-		else 
 			return NULL;
+		}
 	}
 
-	printk_debug("rom address for %s = %x\n",
+	printk_debug("rom address for %s = %x\n", dev_path(dev), rom_address);
-		    dev_path(dev), rom_address);
 
 	/* enable expansion ROM address decoding */
-	pci_write_config32(dev, PCI_ROM_ADDRESS, rom_address|PCI_ROM_ADDRESS_ENABLE);
+	pci_write_config32(dev, PCI_ROM_ADDRESS,
+			   rom_address|PCI_ROM_ADDRESS_ENABLE);
 
 	rom_header = rom_address;
 	printk_spew("PCI Expansion ROM, signature 0x%04x, \n\t"
@@ -38,10 +39,11 @@ struct rom_header * pci_rom_probe(struct device *dev)
 	}
 
 	rom_data = (unsigned char *) rom_header + le32_to_cpu(rom_header->data);
-	printk_spew("PCI ROM Image,  Vendor %04x, Device %04x,\n",
+	printk_spew("PCI ROM Image, Vendor %04x, Device %04x,\n",
 		    rom_data->vendor, rom_data->device);
 	if (dev->vendor != rom_data->vendor || dev->device != rom_data->device) {
-		printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n", rom_data->vendor, rom_data->device);
+		printk_err("Device or Vendor ID mismatch Vendor %04x, Device %04x\n",
+			   rom_data->vendor, rom_data->device);
 		return NULL;
 	}
 

src/northbridge/amd/amdk8/northbridge.c

@@ -672,7 +672,6 @@ static void pci_domain_set_resources(device_t dev)
 			sizek = limitk - ((8*64)+(16*16));
 			
 		}
-
 		
 		/* See if I need to split the region to accomodate pci memory space */
 		if ((basek < mmio_basek) && (limitk > mmio_basek)) {
@@ -728,9 +727,10 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
         int apic_id_offset = bsp_apic_id;	
 
         dev_mc = dev_find_slot(0, PCI_DEVFN(0x18, 0));
-        if(pci_read_config32(dev_mc, 0x68) & ( HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST)) {
+        if (pci_read_config32(dev_mc, 0x68) & ( HTTC_APIC_EXT_ID | HTTC_APIC_EXT_BRD_CST)) {
                 enable_apic_ext_id = 1;
-                if(apic_id_offset==0) { //bsp apic id is not changed
+                if (apic_id_offset==0) {
+			//bsp apic id is not changed
                         apic_id_offset = APIC_ID_OFFSET;
                 }
         }
@@ -769,7 +769,8 @@ static unsigned int cpu_bus_scan(device_t dev, unsigned int max)
 		/* Report what I have done */
 		if (cpu) {
                         if(enable_apic_ext_id) {
-                        	if(cpu->path.u.apic.apic_id<apic_id_offset) { //all add offset except bsp cores
+                        	if(cpu->path.u.apic.apic_id<apic_id_offset) {
+					//all add offset except bsp cores
                                 	if( (cpu->path.u.apic.apic_id > 0) || (bsp_apic_id!=0) )
                                         	cpu->path.u.apic.apic_id += apic_id_offset;
                                 }