soc/intel/apollolake: add support for verstage

There previously was no support for building verstage on apollolake.
Add that suport by linking in the appropriate modules as well as
providing vboot_platform_is_resuming(). The link address for verstage
is the same as FSP-M because they would never be in CAR along side
each other. Additionally, program the ACPI I/O BAR and enable decoding
so sleep state can be determined for early firmware verification.

Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14972
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/apollolake/Kconfig

@@ -123,6 +123,12 @@ config ROMSTAGE_ADDR
 	help
 	  The base address (in CAR) where romstage should be linked
 
+config VERSTAGE_ADDR
+	hex
+	default 0xfef60000
+	help
+	  The base address (in CAR) where verstage should be linked
+
 config CACHE_MRC_SETTINGS
 	bool
 	default y