soc/intel/apollolake: add support for verstage

There previously was no support for building verstage on apollolake.
Add that suport by linking in the appropriate modules as well as
providing vboot_platform_is_resuming(). The link address for verstage
is the same as FSP-M because they would never be in CAR along side
each other. Additionally, program the ACPI I/O BAR and enable decoding
so sleep state can be determined for early firmware verification.

Change-Id: I1a0baab342ac55fd82dbed476abe0063787e3491
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/14972
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan@google.com>

src/soc/intel/apollolake/Makefile.inc

@@ -56,6 +56,12 @@ postcar-y += mmap_boot.c
 postcar-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
 postcar-y += tsc_freq.c
 
+verstage-y += memmap.c
+verstage-y += mmap_boot.c
+verstage-$(CONFIG_SOC_UART_DEBUG) += uart_early.c
+verstage-y += tsc_freq.c
+verstage-y += pmutil.c
+
 CPPFLAGS_common += -I$(src)/soc/intel/apollolake/include
 
 # Since FSP-M runs in CAR we need to relocate it to a specific address