libpayload: arm64: Keep instruction cache enabled at all times
This patch makes libpayload enable the instruction cache as the very first thing, which is similar to how we treat it in coreboot. It also prevents the icache from being disabled again during mmu_disable() as part of the two-stage page table setup in post_sysinfo_scan_mmu_setup(). It replaces the existing mmu_disable() implementation with the assembly version from coreboot which handles certain edge cases better (see CB:27238 for details). The SCTLR flag definitions in libpayload seem to have still been copy&pasted from arm32, so replace with the actual arm64 defintions from coreboot. Change-Id: Ifdbec34f0875ecc69fedcbea5c20e943379a3d2d Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/38908 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Hung-Te Lin <hungte@chromium.org>
This commit is contained in:
committed by
Patrick Georgi
parent
6cf33858b6
commit
bf33b03acf
@@ -29,6 +29,7 @@
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*/
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#include <arch/asm.h>
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#include <arch/lib_helpers.h>
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.macro dcache_apply_all crm
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dsb sy
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@@ -96,3 +97,17 @@ ENDPROC(dcache_clean_all)
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ENTRY(dcache_clean_invalidate_all)
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dcache_apply_all crm=cisw
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ENDPROC(dcache_clean_invalidate_all)
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/* This must be implemented in assembly to ensure there are no accesses to
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memory (e.g. the stack) in between disabling and flushing the cache. */
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ENTRY(mmu_disable)
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str x30, [sp, #-0x8]
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mrs x0, sctlr_el2
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mov x1, #~(SCTLR_C | SCTLR_M)
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and x0, x0, x1
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msr sctlr_el2, x0
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isb
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bl dcache_clean_invalidate_all
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ldr x30, [sp, #-0x8]
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ret
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ENDPROC(mmu_disable)
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@@ -28,11 +28,15 @@
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*/
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#include <arch/asm.h>
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#include <arch/lib_helpers.h>
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/*
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* Our entry point
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*/
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ENTRY(_entry)
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/* Initialize SCTLR to intended state (icache and stack-alignment on) */
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ldr w1, =(SCTLR_RES1 | SCTLR_I | SCTLR_SA)
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msr sctlr_el2, x1
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/* Save off the location of the coreboot tables */
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ldr x1, 1f
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@@ -303,30 +303,6 @@ static uint32_t is_mmu_enabled(void)
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return (sctlr & SCTLR_M);
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}
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/*
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* Func: mmu_disable
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* Desc: Invalidate caches and disable mmu
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*/
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void mmu_disable(void)
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{
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uint32_t sctlr;
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sctlr = raw_read_sctlr_el2();
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sctlr &= ~(SCTLR_C | SCTLR_M | SCTLR_I);
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tlbiall_el2();
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dcache_clean_invalidate_all();
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dsb();
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isb();
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raw_write_sctlr_el2(sctlr);
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dcache_clean_invalidate_all();
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dsb();
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isb();
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}
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/*
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* Func: mmu_enable
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* Desc: Initialize MAIR, TCR, TTBR and enable MMU by setting appropriate bits
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