nb/intel/x4x: Move boilerplate romstage to a common location
This adds 3 mb romstage callbacks: - void mb_lpc_setup(void) to be used to set up the superio - void mb_get_spd_map(u8 spd_map[4]) to get I2C addresses of SPDs - (optional)mb_pre_raminit_setup(int s3_resume) to set up mainboard specific things before the raminit. Change-Id: Ic3b838856b3076ed05eeeea7c0656c2078462272 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/36758 Reviewed-by: Patrick Georgi <pgeorgi@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
committed by
Patrick Georgi
Patrick Georgi
parent
dc7b2de88b
commit
bf53acca5e
@@ -14,57 +14,27 @@
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <southbridge/intel/i82801jx/i82801jx.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <arch/romstage.h>
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#include <superio/winbond/w83667hg-a/w83667hg-a.h>
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#include <superio/winbond/common/winbond.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83667HG_A_SP1)
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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/* Early mainboard specific GPIO setup.
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* We should use standard gpio.h eventually
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*/
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static void mb_misc_rcba(void)
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void mb_lpc_setup(void)
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{
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/* TODO? */
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RCBA32(RCBA_CG) = 0xbf7f001f;
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RCBA32(0x3430) = 0x00000002;
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RCBA32(0x3f00) = 0x00000038;
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}
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void mainboard_romstage_entry(void)
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{
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const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 };
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u8 boot_path = 0;
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u8 s3_resume;
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/* Set southbridge and Super I/O GPIOs. */
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i82801jx_lpc_setup();
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mb_misc_rcba();
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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enable_smbus();
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i82801jx_early_init();
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x4x_early_init();
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s3_resume = southbridge_detect_s3_resume();
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if (s3_resume)
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boot_path = BOOT_PATH_RESUME;
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if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
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boot_path = BOOT_PATH_WARM_RESET;
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sdram_initialize(boot_path, spd_addrmap);
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x4x_late_init(s3_resume);
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printk(BIOS_DEBUG, "x4x late init complete\n");
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}
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void mb_get_spd_map(u8 spd_map[4])
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{
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spd_map[0] = 0x50;
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spd_map[1] = 0x51;
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spd_map[2] = 0x52;
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spd_map[3] = 0x53;
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}
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@@ -12,22 +12,22 @@
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* GNU General Public License for more details.
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*/
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#include <device/pci_ops.h>
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#include <device/pnp_ops.h>
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#include <console/console.h>
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#include <southbridge/intel/i82801jx/i82801jx.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <cpu/x86/msr.h>
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#include <cpu/intel/speedstep.h>
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#include <arch/romstage.h>
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#include <cf9_reset.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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#include <superio/winbond/common/winbond.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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void mb_lpc_setup(void)
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{
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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static u8 msr_get_fsb(void)
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{
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@@ -103,41 +103,20 @@ static int setup_sio_gpio(void)
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return need_reset;
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}
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void mainboard_romstage_entry(void)
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void mb_pre_raminit_setup(int s3_resume)
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{
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/* This board has first dimm slot of each channel hooked up to
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rank0 and rank1, while the second dimm slot is only connected
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to rank1. The raminit does not support such setups
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const u8 spd_addrmap[4] = { 0x50, 0x51, 0x52, 0x53 }; */
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const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
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u8 boot_path = 0;
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u8 s3_resume;
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/* Set southbridge and Super I/O GPIOs. */
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i82801jx_lpc_setup();
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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enable_smbus();
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i82801jx_early_init();
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x4x_early_init();
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s3_resume = southbridge_detect_s3_resume();
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if (s3_resume)
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boot_path = BOOT_PATH_RESUME;
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if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
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boot_path = BOOT_PATH_WARM_RESET;
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if (!s3_resume && setup_sio_gpio()) {
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printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n");
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full_reset();
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}
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sdram_initialize(boot_path, spd_addrmap);
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x4x_late_init(s3_resume);
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printk(BIOS_DEBUG, "x4x late init complete\n");
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}
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void mb_get_spd_map(u8 spd_map[4])
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{
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/* This board has first dimm slot of each channel hooked up to
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rank0 and rank1, while the second dimm slot is only connected
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to rank1. The raminit does not support such setups. So only the
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first dimms of each channel are used. */
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spd_map[0] = 0x50;
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spd_map[2] = 0x52;
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}
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@@ -17,20 +17,20 @@
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#include <cf9_reset.h>
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#include <device/pnp_ops.h>
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#include <device/pci_ops.h>
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#include <console/console.h>
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#include <arch/romstage.h>
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#include <cpu/intel/speedstep.h>
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#include <cpu/x86/msr.h>
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#include <northbridge/intel/x4x/x4x.h>
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#include <southbridge/intel/common/pmclib.h>
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#include <southbridge/intel/i82801gx/i82801gx.h>
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#include <superio/winbond/common/winbond.h>
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#include <superio/winbond/w83627dhg/w83627dhg.h>
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#define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1)
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#define GPIO_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V)
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#define LPC_DEV PCI_DEV(0, 0x1f, 0)
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void mb_lpc_setup(void)
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{
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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}
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static u8 msr_get_fsb(void)
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{
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@@ -127,40 +127,16 @@ static int setup_sio_gpio(void)
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return need_reset;
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}
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void mainboard_romstage_entry(void)
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void mb_pre_raminit_setup(int s3_resume)
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{
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// ch0 ch1
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const u8 spd_addrmap[4] = { 0x50, 0, 0x52, 0 };
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u8 boot_path = 0;
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u8 s3_resume;
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/* Set southbridge and Super I/O GPIOs. */
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i82801gx_lpc_setup();
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winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
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console_init();
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enable_smbus();
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i82801gx_early_init();
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x4x_early_init();
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s3_resume = southbridge_detect_s3_resume();
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if (s3_resume)
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boot_path = BOOT_PATH_RESUME;
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if (MCHBAR32(PMSTS_MCHBAR) & PMSTS_WARM_RESET)
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boot_path = BOOT_PATH_WARM_RESET;
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if (!s3_resume && setup_sio_gpio()) {
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printk(BIOS_DEBUG,
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"Needs reset to configure CPU BSEL straps\n");
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printk(BIOS_DEBUG, "Needs reset to configure CPU BSEL straps\n");
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full_reset();
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}
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sdram_initialize(boot_path, spd_addrmap);
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x4x_late_init(s3_resume);
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printk(BIOS_DEBUG, "x4x late init complete\n");
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}
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void mb_get_spd_map(u8 spd_map[4])
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{
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spd_map[0] = 0x50;
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spd_map[2] = 0x52;
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}
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