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vc/intel/fsp/mtl: Update header files from 2344_00 to 2364_00

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Update header files for FSP for Meteor Lake platform to
version 2364_00, previous version being 2344_00.

FSPM:
1. Address offset changes

FSPS:
1. Address offset changes

BUG=b:251733481
TEST=emerge-rex intel-mtlfsp

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I8e4f62890b812f68dffe215e51c433510fca018f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68491
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tarun Tuli <taruntuli@google.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik
2022-10-17 14:57:41 +05:30
committed by Felix Held
parent e146fbd60c
commit bf71c7292a
2 changed files with 435 additions and 430 deletions
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852
src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspmUpd.h
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File diff suppressed because it is too large Load Diff

13
src/vendorcode/intel/fsp/fsp2_0/meteorlake/FspsUpd.h
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@ -138,7 +138,8 @@ typedef struct {
UINT32 MicrocodeRegionSize;
/** Offset 0x0060 - Turbo Mode
Enable/Disable processor Turbo Mode. 0:disable, <b>1: Enable</b>
Enable/Disable processor Turbo Mode (requires EMTTM enabled too). 0:disable, <b>1:
Enable</b>
$EN_DIS
**/
UINT8 TurboMode;
@ -3121,17 +3122,17 @@ typedef struct {
/** Offset 0x1CEC - Reserved
**/
UINT8 Reserved66[2];
UINT8 Reserved66[3];
/** Offset 0x1CEE - PMC C10 dynamic threshold dajustment enable
/** Offset 0x1CEF - PMC C10 dynamic threshold dajustment enable
Set if you want to enable PMC C10 dynamic threshold adjustment. Only works on supported SKUs
$EN_DIS
**/
UINT8 PmcC10DynamicThresholdAdjustment;
/** Offset 0x1CEF - Reserved
/** Offset 0x1CF0 - Reserved
**/
UINT8 Reserved67[33];
UINT8 Reserved67[32];
/** Offset 0x1D10 - FspEventHandler
<b>Optional</b> pointer to the boot loader's implementation of FSP_EVENT_HANDLER.
@ -3161,7 +3162,7 @@ typedef struct {
/** Offset 0x1D20
**/
UINT8 UnusedUpdSpace43[6];
UINT8 UnusedUpdSpace42[6];
/** Offset 0x1D26
**/