From 8b0c1c8027cc4ba1e139d90102d6236746de2def Mon Sep 17 00:00:00 2001 From: FrankChu Date: Tue, 24 Nov 2020 15:49:14 +0800 Subject: [PATCH 01/45] mb/google/dedede: Create galtic variant Create the galtic variant of the waddledee reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:170913840 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_GALTIC Signed-off-by: FrankChu Change-Id: Ie7534d56bc67aca4484f40af1221d669addc01fd Reviewed-on: https://review.coreboot.org/c/coreboot/+/47900 Reviewed-by: Paul Fagerburg Reviewed-by: Martin Roth Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/Kconfig | 2 + src/mainboard/google/dedede/Kconfig.name | 5 +++ .../variants/galtic/include/variant/ec.h | 8 ++++ .../variants/galtic/include/variant/gpio.h | 8 ++++ .../variants/galtic/memory/Makefile.inc | 5 +++ .../galtic/memory/dram_id.generated.txt | 1 + .../variants/galtic/memory/mem_parts_used.txt | 6 +++ .../dedede/variants/galtic/overridetree.cb | 42 +++++++++++++++++++ 8 files changed, 77 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/galtic/include/variant/ec.h create mode 100644 src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h create mode 100644 src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc create mode 100644 src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/dedede/variants/galtic/overridetree.cb diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 6c4f456565..9f662a493c 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -96,6 +96,7 @@ config MAINBOARD_PART_NUMBER default "Magolor" if BOARD_GOOGLE_MAGOLOR default "Metaknight" if BOARD_GOOGLE_METAKNIGHT default "Lantis" if BOARD_GOOGLE_LANTIS + default "Galtic" if BOARD_GOOGLE_GALTIC config MAX_CPUS int @@ -127,5 +128,6 @@ config VARIANT_DIR default "magolor" if BOARD_GOOGLE_MAGOLOR default "metaknight" if BOARD_GOOGLE_METAKNIGHT default "lantis" if BOARD_GOOGLE_LANTIS + default "galtic" if BOARD_GOOGLE_GALTIC endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index 2a8950c88e..c8ce0030d8 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -78,3 +78,8 @@ config BOARD_GOOGLE_LANTIS select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP select DRIVERS_GENERIC_MAX98357A + +config BOARD_GOOGLE_GALTIC + bool "-> Galtic" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP diff --git a/src/mainboard/google/dedede/variants/galtic/include/variant/ec.h b/src/mainboard/google/dedede/variants/galtic/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h b/src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc new file mode 100644 index 0000000000..b0ca2223a8 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt new file mode 100644 index 0000000000..59381dcf5b --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/galtic/overridetree.cb b/src/mainboard/google/dedede/variants/galtic/overridetree.cb new file mode 100644 index 0000000000..404024b1d6 --- /dev/null +++ b/src/mainboard/google/dedede/variants/galtic/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end From 905939b3c8fd34121c54133467b5d4a5d8a5cd32 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Tue, 24 Nov 2020 14:39:57 +0530 Subject: [PATCH 02/45] vc/intel/fsp/fsp2_0/alderlake: Update FSP header file version to 1483_11 List of changes: 1. FSP-M Header: - Adjust UPD Offset for Reservedxx - Rename UPD Offset UnusedUpdSpace32 -> UnusedUpdSpace29 2. FSP-S Header: - Rename UPD Offset UnusedUpdSpace46 -> UnusedUpdSpace44 Change-Id: Ia1ef59e4cf6ccce8f48908af51535aea761cd972 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/47901 Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak Reviewed-by: V Sowmya Tested-by: build bot (Jenkins) --- .../intel/fsp/fsp2_0/alderlake/FspmUpd.h | 175 +++++++++--------- .../intel/fsp/fsp2_0/alderlake/FspsUpd.h | 2 +- 2 files changed, 88 insertions(+), 89 deletions(-) diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h index da746ba3e4..0e9ca02d35 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspmUpd.h @@ -524,18 +524,18 @@ typedef struct { /** Offset 0x0241 - Reserved **/ - UINT8 Reserved14[143]; + UINT8 Reserved14[141]; -/** Offset 0x02D0 - DMI Gen3 Root port preset values per lane +/** Offset 0x02CE - DMI Gen3 Root port preset values per lane Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is default for each lane **/ UINT8 DmiGen3RootPortPreset[8]; -/** Offset 0x02D8 - Reserved +/** Offset 0x02D6 - Reserved **/ UINT8 Reserved15[150]; -/** Offset 0x036E - C6DRAM power gating feature +/** Offset 0x036C - C6DRAM power gating feature This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating feature.- 1: Allocate PRMRR memory for C6DRAM power gating feature. @@ -543,314 +543,314 @@ typedef struct { **/ UINT8 EnableC6Dram; -/** Offset 0x036F - Reserved +/** Offset 0x036D - Reserved **/ UINT8 Reserved16[5]; -/** Offset 0x0374 - Hyper Threading Enable/Disable +/** Offset 0x0372 - Hyper Threading Enable/Disable Enable or Disable Hyper Threading; 0: Disable; 1: Enable $EN_DIS **/ UINT8 HyperThreading; -/** Offset 0x0375 - Reserved +/** Offset 0x0373 - Reserved **/ UINT8 Reserved17; -/** Offset 0x0376 - CPU ratio value +/** Offset 0x0374 - CPU ratio value CPU ratio value. Valid Range 0 to 63 **/ UINT8 CpuRatio; -/** Offset 0x0377 - Reserved +/** Offset 0x0375 - Reserved **/ UINT8 Reserved18[2]; -/** Offset 0x0379 - Processor Early Power On Configuration FCLK setting +/** Offset 0x0377 - Processor Early Power On Configuration FCLK setting 0: 800 MHz (ULT/ULX). 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.- 2: 400 MHz. - 3: Reserved 0:800 MHz, 1: 1 GHz, 2: 400 MHz, 3: Reserved **/ UINT8 FClkFrequency; -/** Offset 0x037A - Reserved +/** Offset 0x0378 - Reserved **/ UINT8 Reserved19; -/** Offset 0x037B - Enable or Disable VMX +/** Offset 0x0379 - Enable or Disable VMX Enable or Disable VMX; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 VmxEnable; -/** Offset 0x037C - Reserved +/** Offset 0x037A - Reserved **/ UINT8 Reserved20[20]; -/** Offset 0x0390 - Enable or Disable TME +/** Offset 0x038E - Enable or Disable TME Enable or Disable TME; 0: Disable; 1: Enable. $EN_DIS **/ UINT8 TmeEnable; -/** Offset 0x0391 - Reserved +/** Offset 0x038F - Reserved **/ - UINT8 Reserved21[13]; + UINT8 Reserved21[11]; -/** Offset 0x039E - BiosGuard +/** Offset 0x039A - BiosGuard Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable $EN_DIS **/ UINT8 BiosGuard; -/** Offset 0x039F +/** Offset 0x039B **/ UINT8 BiosGuardToolsInterface; -/** Offset 0x03A0 - Reserved +/** Offset 0x039C - Reserved **/ UINT8 Reserved22[4]; -/** Offset 0x03A4 - PrmrrSize +/** Offset 0x03A0 - PrmrrSize Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable **/ UINT32 PrmrrSize; -/** Offset 0x03A8 - SinitMemorySize +/** Offset 0x03A4 - SinitMemorySize Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable **/ UINT32 SinitMemorySize; -/** Offset 0x03AC - Reserved +/** Offset 0x03A8 - Reserved **/ - UINT8 Reserved23[12]; + UINT8 Reserved23[8]; -/** Offset 0x03B8 - TxtHeapMemorySize +/** Offset 0x03B0 - TxtHeapMemorySize Enable/Disable. 0: Disable, define default value of TxtHeapMemorySize , 1: enable **/ UINT32 TxtHeapMemorySize; -/** Offset 0x03BC - TxtDprMemorySize +/** Offset 0x03B4 - TxtDprMemorySize Enable/Disable. 0: Disable, define default value of TxtDprMemorySize , 1: enable **/ UINT32 TxtDprMemorySize; -/** Offset 0x03C0 - Reserved +/** Offset 0x03B8 - Reserved **/ UINT8 Reserved24[614]; -/** Offset 0x0626 - Number of RsvdSmbusAddressTable. +/** Offset 0x061E - Number of RsvdSmbusAddressTable. The number of elements in the RsvdSmbusAddressTable. **/ UINT8 PchNumRsvdSmbusAddresses; -/** Offset 0x0627 - Reserved +/** Offset 0x061F - Reserved **/ UINT8 Reserved25[4]; -/** Offset 0x062B - Usage type for ClkSrc +/** Offset 0x0623 - Usage type for ClkSrc 0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use (free running), 0xFF: not used **/ UINT8 PcieClkSrcUsage[18]; -/** Offset 0x063D - Reserved +/** Offset 0x0635 - Reserved **/ UINT8 Reserved26[14]; -/** Offset 0x064B - ClkReq-to-ClkSrc mapping +/** Offset 0x0643 - ClkReq-to-ClkSrc mapping Number of ClkReq signal assigned to ClkSrc **/ UINT8 PcieClkSrcClkReq[18]; -/** Offset 0x065D - Reserved +/** Offset 0x0655 - Reserved **/ UINT8 Reserved27[91]; -/** Offset 0x06B8 - Enable PCIE RP Mask +/** Offset 0x06B0 - Enable PCIE RP Mask Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0 for port1, bit1 for port2, and so on. **/ UINT32 PcieRpEnableMask; -/** Offset 0x06BC - Reserved +/** Offset 0x06B4 - Reserved **/ UINT8 Reserved28[2]; -/** Offset 0x06BE - Enable HD Audio Link +/** Offset 0x06B6 - Enable HD Audio Link Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1. $EN_DIS **/ UINT8 PchHdaAudioLinkHdaEnable; -/** Offset 0x06BF - Reserved +/** Offset 0x06B7 - Reserved **/ UINT8 Reserved29[3]; -/** Offset 0x06C2 - Enable HD Audio DMIC_N Link +/** Offset 0x06BA - Enable HD Audio DMIC_N Link Enable/disable HD Audio DMIC1 link. Muxed with SNDW3. **/ UINT8 PchHdaAudioLinkDmicEnable[2]; -/** Offset 0x06C4 - DMIC ClkA Pin Muxing (N - DMIC number) +/** Offset 0x06BC - DMIC ClkA Pin Muxing (N - DMIC number) Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKA_* **/ UINT32 PchHdaAudioLinkDmicClkAPinMux[2]; -/** Offset 0x06CC - DMIC ClkB Pin Muxing +/** Offset 0x06C4 - DMIC ClkB Pin Muxing Determines DMIC ClkA Pin muxing. See GPIO_*_MUXING_DMIC_CLKB_* **/ UINT32 PchHdaAudioLinkDmicClkBPinMux[2]; -/** Offset 0x06D4 - Enable HD Audio DSP +/** Offset 0x06CC - Enable HD Audio DSP Enable/disable HD Audio DSP feature. $EN_DIS **/ UINT8 PchHdaDspEnable; -/** Offset 0x06D5 - Reserved +/** Offset 0x06CD - Reserved **/ UINT8 Reserved30[3]; -/** Offset 0x06D8 - DMIC Data Pin Muxing +/** Offset 0x06D0 - DMIC Data Pin Muxing Determines DMIC Data Pin muxing. See GPIO_*_MUXING_DMIC_DATA_* **/ UINT32 PchHdaAudioLinkDmicDataPinMux[2]; -/** Offset 0x06E0 - Enable HD Audio SSP0 Link +/** Offset 0x06D8 - Enable HD Audio SSP0 Link Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5 **/ UINT8 PchHdaAudioLinkSspEnable[6]; -/** Offset 0x06E6 - Enable HD Audio SoundWire#N Link +/** Offset 0x06DE - Enable HD Audio SoundWire#N Link Enable/disable HD Audio SNDW#N link. Muxed with HDA. **/ UINT8 PchHdaAudioLinkSndwEnable[4]; -/** Offset 0x06EA - iDisp-Link Frequency +/** Offset 0x06E2 - iDisp-Link Frequency iDisp-Link Freq (PCH_HDAUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz. 4: 96MHz, 3: 48MHz **/ UINT8 PchHdaIDispLinkFrequency; -/** Offset 0x06EB - iDisp-Link T-mode +/** Offset 0x06E3 - iDisp-Link T-mode iDisp-Link T-Mode (PCH_HDAUDIO_IDISP_TMODE enum): 0: 2T, 2: 4T, 3: 8T, 4: 16T 0: 2T, 2: 4T, 3: 8T, 4: 16T **/ UINT8 PchHdaIDispLinkTmode; -/** Offset 0x06EC - iDisplay Audio Codec disconnection +/** Offset 0x06E4 - iDisplay Audio Codec disconnection 0: Not disconnected, enumerable, 1: Disconnected SDI, not enumerable. $EN_DIS **/ UINT8 PchHdaIDispCodecDisconnect; -/** Offset 0x06ED - Debug Interfaces +/** Offset 0x06E5 - Debug Interfaces Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT2 - Not used. **/ UINT8 PcdDebugInterfaceFlags; -/** Offset 0x06EE - Serial Io Uart Debug Controller Number +/** Offset 0x06E6 - Serial Io Uart Debug Controller Number Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used for debug purpose. 0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2 **/ UINT8 SerialIoUartDebugControllerNumber; -/** Offset 0x06EF - Reserved +/** Offset 0x06E7 - Reserved **/ UINT8 Reserved31[13]; -/** Offset 0x06FC - ISA Serial Base selection +/** Offset 0x06F4 - ISA Serial Base selection Select ISA Serial Base address. Default is 0x3F8. 0:0x3F8, 1:0x2F8 **/ UINT8 PcdIsaSerialUartBase; -/** Offset 0x06FD - Reserved +/** Offset 0x06F5 - Reserved **/ UINT8 Reserved32[4]; -/** Offset 0x0701 - MRC Safe Config +/** Offset 0x06F9 - MRC Safe Config Enables/Disable MRC Safe Config $EN_DIS **/ UINT8 MrcSafeConfig; -/** Offset 0x0702 - TCSS Thunderbolt PCIE Root Port 0 Enable +/** Offset 0x06FA - TCSS Thunderbolt PCIE Root Port 0 Enable Set TCSS Thunderbolt PCIE Root Port 0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie0En; -/** Offset 0x0703 - TCSS Thunderbolt PCIE Root Port 1 Enable +/** Offset 0x06FB - TCSS Thunderbolt PCIE Root Port 1 Enable Set TCSS Thunderbolt PCIE Root Port 1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie1En; -/** Offset 0x0704 - TCSS Thunderbolt PCIE Root Port 2 Enable +/** Offset 0x06FC - TCSS Thunderbolt PCIE Root Port 2 Enable Set TCSS Thunderbolt PCIE Root Port 2. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie2En; -/** Offset 0x0705 - TCSS Thunderbolt PCIE Root Port 3 Enable +/** Offset 0x06FD - TCSS Thunderbolt PCIE Root Port 3 Enable Set TCSS Thunderbolt PCIE Root Port 3. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssItbtPcie3En; -/** Offset 0x0706 - TCSS USB HOST (xHCI) Enable +/** Offset 0x06FE - TCSS USB HOST (xHCI) Enable Set TCSS XHCI. 0:Disabled 1:Enabled - Must be enabled if xDCI is enabled below $EN_DIS **/ UINT8 TcssXhciEn; -/** Offset 0x0707 - TCSS USB DEVICE (xDCI) Enable +/** Offset 0x06FF - TCSS USB DEVICE (xDCI) Enable Set TCSS XDCI. 0:Disabled 1:Enabled - xHCI must be enabled if xDCI is enabled $EN_DIS **/ UINT8 TcssXdciEn; -/** Offset 0x0708 - TCSS DMA0 Enable +/** Offset 0x0700 - TCSS DMA0 Enable Set TCSS DMA0. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma0En; -/** Offset 0x0709 - TCSS DMA1 Enable +/** Offset 0x0701 - TCSS DMA1 Enable Set TCSS DMA1. 0:Disabled 1:Enabled $EN_DIS **/ UINT8 TcssDma1En; -/** Offset 0x070A - Reserved +/** Offset 0x0702 - Reserved **/ UINT8 Reserved33[2]; -/** Offset 0x070C - Early Command Training +/** Offset 0x0704 - Early Command Training Enables/Disable Early Command Training $EN_DIS **/ UINT8 ECT; -/** Offset 0x070D - Reserved +/** Offset 0x0705 - Reserved **/ UINT8 Reserved34[65]; -/** Offset 0x074E - Ch Hash Mask +/** Offset 0x0746 - Ch Hash Mask Set the BIT(s) to be included in the XOR function. NOTE BIT mask corresponds to BITS [19:6] Default is 0x30CC **/ UINT16 ChHashMask; -/** Offset 0x0750 - Reserved +/** Offset 0x0748 - Reserved **/ UINT8 Reserved35[64]; -/** Offset 0x0790 - PcdSerialDebugLevel +/** Offset 0x0788 - PcdSerialDebugLevel Serial Debug Message Level. 0:Disable, 1:Error Only, 2:Error & Warnings, 3:Load, Error, Warnings & Info, 4:Load, Error, Warnings, Info & Event, 5:Load, Error, Warnings, Info & Verbose. @@ -859,89 +859,89 @@ typedef struct { **/ UINT8 PcdSerialDebugLevel; -/** Offset 0x0791 - Reserved +/** Offset 0x0789 - Reserved **/ UINT8 Reserved36[2]; -/** Offset 0x0793 - Safe Mode Support +/** Offset 0x078B - Safe Mode Support This option configures the varous items in the IO and MC to be more conservative.(def=Disable) $EN_DIS **/ UINT8 SafeMode; -/** Offset 0x0794 - Reserved +/** Offset 0x078C - Reserved **/ UINT8 Reserved37[2]; -/** Offset 0x0796 - TCSS USB Port Enable +/** Offset 0x078E - TCSS USB Port Enable Bitmap for per port enabling **/ UINT8 UsbTcPortEnPreMem; -/** Offset 0x0797 - Reserved +/** Offset 0x078F - Reserved **/ UINT8 Reserved38[35]; -/** Offset 0x07BA - Command Pins Mapping +/** Offset 0x07B2 - Command Pins Mapping BitMask where bits [3:0] are Controller 0 Channel [3:0] and bits [7:4] are Controller 1 Channel [3:0]. 0 = CCC pin mapping is Ascending, 1 = CCC pin mapping is Descending. **/ UINT8 Lp5CccConfig; -/** Offset 0x07BB - Reserved +/** Offset 0x07B3 - Reserved **/ UINT8 Reserved39[14]; -/** Offset 0x07C9 - Skip external display device scanning +/** Offset 0x07C1 - Skip external display device scanning Enable: Do not scan for external display device, Disable (Default): Scan external display devices $EN_DIS **/ UINT8 SkipExtGfxScan; -/** Offset 0x07CA - Reserved +/** Offset 0x07C2 - Reserved **/ UINT8 Reserved40; -/** Offset 0x07CB - Lock PCU Thermal Management registers +/** Offset 0x07C3 - Lock PCU Thermal Management registers Lock PCU Thermal Management registers. Enable(Default)=1, Disable=0 $EN_DIS **/ UINT8 LockPTMregs; -/** Offset 0x07CC - Reserved +/** Offset 0x07C4 - Reserved **/ UINT8 Reserved41[129]; -/** Offset 0x084D - Skip CPU replacement check +/** Offset 0x0845 - Skip CPU replacement check Test, 0: disable, 1: enable, Setting this option to skip CPU replacement check $EN_DIS **/ UINT8 SkipCpuReplacementCheck; -/** Offset 0x084E - Reserved +/** Offset 0x0846 - Reserved **/ UINT8 Reserved42[292]; -/** Offset 0x0972 - Serial Io Uart Debug Mode +/** Offset 0x096A - Serial Io Uart Debug Mode Select SerialIo Uart Controller mode 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom, 4:SerialIoUartSkipInit **/ UINT8 SerialIoUartDebugMode; -/** Offset 0x0973 - Reserved +/** Offset 0x096B - Reserved **/ UINT8 Reserved43[183]; -/** Offset 0x0A2A - GPIO Override +/** Offset 0x0A22 - GPIO Override Gpio Override Level - FSP will not configure any GPIOs and rely on GPIO setings before moved to FSP. Available configurations 0: Disable; 1: Level 1 - Skips GPIO configuration in PEI/FSPM/FSPT phase;2: Level 2 - Reserved for future use **/ UINT8 GpioOverride; -/** Offset 0x0A2B - Reserved +/** Offset 0x0A23 - Reserved **/ UINT8 Reserved44[349]; } FSP_M_CONFIG; @@ -962,12 +962,11 @@ typedef struct { **/ FSP_M_CONFIG FspmConfig; - -/** Offset 0x0B88 +/** Offset 0x0B80 **/ - UINT8 UnusedUpdSpace32[6]; + UINT8 UnusedUpdSpace29[6]; -/** Offset 0x0B8E +/** Offset 0x0B86 **/ UINT16 UpdTerminator; } FSPM_UPD; diff --git a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h index 38945d0d2c..14d29dbcaa 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/alderlake/FspsUpd.h @@ -865,7 +865,7 @@ typedef struct { /** Offset 0x1200 **/ - UINT8 UnusedUpdSpace46[6]; + UINT8 UnusedUpdSpace44[6]; /** Offset 0x1206 **/ From 59f06ada68db1775c0578035405d93ec666a04b5 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 25 Nov 2020 13:55:42 +0100 Subject: [PATCH 03/45] drivers/intel/fsp2_0: introduce possibility of using a full FD binary MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Currently, setting a custom FSP binary is only possible by using split FSP-T/M/S FD files. This change introduces the possibility to pass a combined FD file (the "standard" FSP format). This is done by adding a new boolean Kconfig FSP_FULL_FD, specifying that the FSP is a single FD file instead of split FSP-T/M/S FD files, and making FSP_FD_PATH user-visible when the option is chosen. In this case, the other options for split files get hidden. When the user chooses to use a full FD file instead of the split ones, the FD file gets split during build, just like it is done when selecting the Github FSP repo (FSP_USE_REPO). Test: Supermicro X11SSM-F builds and boots fine with custom FSP FD set. Signed-off-by: Michael Niewöhner Change-Id: I1cb98c1ff319823a2a8a95444c9b4f3d96162a02 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47993 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/drivers/intel/fsp2_0/Kconfig | 25 ++++++++++++++++--------- src/drivers/intel/fsp2_0/Makefile.inc | 2 +- 2 files changed, 17 insertions(+), 10 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index f12ff6e6a7..ecff4c73d7 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -41,6 +41,7 @@ config HAVE_INTEL_FSP_REPO config FSP_USE_REPO bool "Use binaries of the Intel FSP repository on GitHub" depends on HAVE_INTEL_FSP_REPO + select FSP_FULL_FD default y help Select this option to use the default FSP headers and binaries @@ -56,11 +57,10 @@ config FSP_HEADER_PATH Include directory with the FSP ABI header files. config FSP_FD_PATH - string - depends on FSP_USE_REPO + string "Location of FSP FD file" if FSP_FULL_FD && !FSP_USE_REPO help Path to the FSP FD file that contains the individual FSP-T, FSP-M - and FSP-S binaries. + and FSP-S binaries. The file gets split at build-time. config ADD_FSP_BINARIES bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO @@ -81,25 +81,32 @@ config FSP_M_CBFS string "Name of FSP-M in CBFS" default "fspm.bin" +config FSP_FULL_FD + bool "Use a combined FSP FD file" if !FSP_USE_REPO + depends on ADD_FSP_BINARIES + help + Use a combined FSP FD file instead of specifying individual, already split + binaries and split the file at build-time. + config FSP_T_FILE - string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_USE_REPO + string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD depends on ADD_FSP_BINARIES depends on FSP_CAR - default "\$(obj)/Fsp_T.fd" if FSP_USE_REPO + default "\$(obj)/Fsp_T.fd" if FSP_FULL_FD help The path and filename of the Intel FSP-T binary for this platform. config FSP_M_FILE - string "Intel FSP-M (memory init) binary path and filename" if !FSP_USE_REPO + string "Intel FSP-M (memory init) binary path and filename" if !FSP_FULL_FD depends on ADD_FSP_BINARIES - default "\$(obj)/Fsp_M.fd" if FSP_USE_REPO + default "\$(obj)/Fsp_M.fd" if FSP_FULL_FD help The path and filename of the Intel FSP-M binary for this platform. config FSP_S_FILE - string "Intel FSP-S (silicon init) binary path and filename" if !FSP_USE_REPO + string "Intel FSP-S (silicon init) binary path and filename" if !FSP_FULL_FD depends on ADD_FSP_BINARIES - default "\$(obj)/Fsp_S.fd" if FSP_USE_REPO + default "\$(obj)/Fsp_S.fd" if FSP_FULL_FD help The path and filename of the Intel FSP-S binary for this platform. diff --git a/src/drivers/intel/fsp2_0/Makefile.inc b/src/drivers/intel/fsp2_0/Makefile.inc index 46299ee470..298198d063 100644 --- a/src/drivers/intel/fsp2_0/Makefile.inc +++ b/src/drivers/intel/fsp2_0/Makefile.inc @@ -72,7 +72,7 @@ ifeq ($(CONFIG_FSP_COMPRESS_FSP_S_LZ4),y) $(FSP_S_CBFS)-compression := LZ4 endif -ifeq ($(CONFIG_FSP_USE_REPO),y) +ifeq ($(CONFIG_FSP_FULL_FD),y) $(obj)/Fsp_M.fd: $(call strip_quotes,$(CONFIG_FSP_FD_PATH)) python2 3rdparty/fsp/Tools/SplitFspBin.py split -f $(CONFIG_FSP_FD_PATH) -o "$(obj)" -n "Fsp.fd" From 3044d708f8f06f3f5f5404de47f6eed47f1dfdae Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 25 Nov 2020 15:07:47 +0100 Subject: [PATCH 04/45] drivers/intel/fsp2_0: move the FSP FD PATH option down in menuconfig MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move the FSP FD PATH option down, so it gets shown in place of the split FD files, when the users chooses to use a full FD binary. Change-Id: Ie03a418fab30a908d020abf94becbaedf54fbb99 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/47999 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Tim Wawrzynczak --- src/drivers/intel/fsp2_0/Kconfig | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/fsp2_0/Kconfig b/src/drivers/intel/fsp2_0/Kconfig index ecff4c73d7..03b9c2b98e 100644 --- a/src/drivers/intel/fsp2_0/Kconfig +++ b/src/drivers/intel/fsp2_0/Kconfig @@ -56,12 +56,6 @@ config FSP_HEADER_PATH help Include directory with the FSP ABI header files. -config FSP_FD_PATH - string "Location of FSP FD file" if FSP_FULL_FD && !FSP_USE_REPO - help - Path to the FSP FD file that contains the individual FSP-T, FSP-M - and FSP-S binaries. The file gets split at build-time. - config ADD_FSP_BINARIES bool "Add Intel FSP 2.0 binaries to CBFS" if !FSP_USE_REPO default y if FSP_USE_REPO @@ -88,6 +82,12 @@ config FSP_FULL_FD Use a combined FSP FD file instead of specifying individual, already split binaries and split the file at build-time. +config FSP_FD_PATH + string "Location of FSP FD file" if FSP_FULL_FD && !FSP_USE_REPO + help + Path to the FSP FD file that contains the individual FSP-T, FSP-M + and FSP-S binaries. The file gets split at build-time. + config FSP_T_FILE string "Intel FSP-T (temp RAM init) binary path and filename" if !FSP_FULL_FD depends on ADD_FSP_BINARIES From 99eed832aedf8557082bb647b5c8e6cdb016f23a Mon Sep 17 00:00:00 2001 From: Idwer Vollering Date: Mon, 16 Dec 2019 15:36:46 +0100 Subject: [PATCH 05/45] util/inteltool: drop OS-specific rdmsr/wrmsr prototypes The previous commit (that was not touching inteltool.h) marking internal functions as static is commit 6faccd1f00 Tested on: FreeBSD 13.0-CURRENT r355582 Change-Id: I4aba72f39b528fd70451a4656fd6c835ff766e49 Signed-off-by: Idwer Vollering Reviewed-on: https://review.coreboot.org/c/coreboot/+/37767 Tested-by: build bot (Jenkins) Reviewed-by: Jacob Garber Reviewed-by: Angel Pons --- util/inteltool/inteltool.h | 2 -- 1 file changed, 2 deletions(-) diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index 77ad61f410..b3253e7d9c 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -380,8 +380,6 @@ typedef struct { uint32_t hi, lo; } msr_t; #define rdmsr freebsd_rdmsr #define wrmsr freebsd_wrmsr typedef struct { uint32_t hi, lo; } msr_t; -msr_t freebsd_rdmsr(int addr); -int freebsd_wrmsr(int addr, msr_t msr); #endif typedef struct { uint16_t addr; int size; char *name; } io_register_t; typedef struct { From f71572605a2b5438da3f0bacd99bd97a491d4620 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Thu, 12 Nov 2020 16:29:24 +0530 Subject: [PATCH 06/45] soc/intel/jasperlake: Enable VT-d and generate DMAR Table Update UPDs required for the creation of DMAR table. By default coreboot was not generating DMAR table for IOMMU which was resulting in below error message in kernel: DMAR: [Firmware Bug]: No DRHD structure found in DMAR table DMAR: No DMAR devices found These changes will publish DMAR table through ACPI and will not result in the above error. BUG=b:170261791 BRANCH=dedede TEST=Build Dedede, boot to kernel and check dmesg if DMAR table exists. Signed-off-by: Meera Ravindranath Change-Id: I97a9f2df185002a4e58eaa910f867acd0b97ec2b Reviewed-on: https://review.coreboot.org/c/coreboot/+/47506 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian Reviewed-by: Maulik V Vaghela --- src/soc/intel/jasperlake/romstage/fsp_params.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/src/soc/intel/jasperlake/romstage/fsp_params.c b/src/soc/intel/jasperlake/romstage/fsp_params.c index 528ef0fd21..cd70807516 100644 --- a/src/soc/intel/jasperlake/romstage/fsp_params.c +++ b/src/soc/intel/jasperlake/romstage/fsp_params.c @@ -4,6 +4,7 @@ #include #include #include +#include #include #include #include @@ -81,6 +82,18 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, /* VT-d config */ m_cfg->VtdDisable = 0; + m_cfg->VtdIopEnable = 0x1; + + if (m_cfg->InternalGfx) { + m_cfg->VtdIgdEnable = 0x1; + m_cfg->VtdBaseAddress[0] = GFXVT_BASE_ADDRESS; + } + + if (m_cfg->SaIpuEnable) { + m_cfg->VtdIpuEnable = 0x1; + m_cfg->VtdBaseAddress[1] = IPUVT_BASE_ADDRESS; + } + m_cfg->VtdBaseAddress[2] = VTVC0_BASE_ADDRESS; m_cfg->SerialIoUartDebugControllerNumber = CONFIG_UART_FOR_CONSOLE; m_cfg->SerialIoUartDebugMode = config->SerialIoUartMode[CONFIG_UART_FOR_CONSOLE]; From 0f34054964a55707af963e86675f6341f506fd47 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Wed, 14 Oct 2020 16:35:11 +0200 Subject: [PATCH 07/45] Makefile.inc: Move adding mcu FIT entries MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This can be done using in the INTERMEDIATE target in the proper place. Change-Id: I28a7764205e0510be89c131058ec56861a479699 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/46453 Reviewed-by: Michael Niewöhner Reviewed-by: Christian Walter Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- Makefile.inc | 39 ++++------------------------------ src/cpu/intel/fit/Makefile.inc | 28 ++++++++++++++++++++++++ 2 files changed, 32 insertions(+), 35 deletions(-) diff --git a/Makefile.inc b/Makefile.inc index 9273961570..fafb9ecd0d 100644 --- a/Makefile.inc +++ b/Makefile.inc @@ -1121,8 +1121,6 @@ $(REFCODE_BLOB): $(RMODTOOL) $(RMODTOOL) -i $(CONFIG_REFCODE_BLOB_FILE) -o $@ endif -FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG)) - ifeq ($(CONFIG_HAVE_RAMSTAGE),y) RAMSTAGE=$(objcbfs)/ramstage.elf else @@ -1136,42 +1134,13 @@ $(obj)/coreboot.rom: $(obj)/coreboot.pre $(RAMSTAGE) $(CBFSTOOL) $$(INTERMEDIATE dd if=/dev/zero bs=$(call _toint,$(CONFIG_ROM_SIZE)) count=1 2> /dev/null | tr '\000' '\377' > $@.tmp dd if=$(obj)/coreboot.pre of=$@.tmp bs=8192 conv=notrunc 2> /dev/null ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y) -ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) - @printf " UPDATE-FIT\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - -r COREBOOT -endif -ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y) - @printf " UPDATE-FIT\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - -r COREBOOT -endif +# Print final FIT table $(IFITTOOL) -f $@.tmp -D -r COREBOOT - -# Second FIT in TOP_SWAP bootblock +# Print final TS BOOTBLOCK FIT table ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) -# INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG adds a region as first ucode into the seconds bootblock -ifneq ($(FIT_ENTRY),) - @printf " UPDATE-FIT2\n" - $(IFITTOOL) -f $@.tmp -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - $(TS_OPTIONS) -r COREBOOT -endif -ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y) - @printf " UPDATE-FIT2\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - $(TS_OPTIONS) -r COREBOOT -endif -ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y) - @printf " UPDATE-FIT2\n" - $(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \ - $(TS_OPTIONS) -r COREBOOT -endif + @printf " TOP SWAP FIT table\n" $(IFITTOOL) -f $@.tmp -D $(TS_OPTIONS) -r COREBOOT - -endif - -endif # !CONFIG_UPDATE_IMAGE +endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK endif # CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE mv $@.tmp $@ @printf " CBFSLAYOUT $(subst $(obj)/,,$(@))\n\n" diff --git a/src/cpu/intel/fit/Makefile.inc b/src/cpu/intel/fit/Makefile.inc index 4b540ba5df..98666843e9 100644 --- a/src/cpu/intel/fit/Makefile.inc +++ b/src/cpu/intel/fit/Makefile.inc @@ -1 +1,29 @@ bootblock-y += fit.S + +FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG)) + +ifneq ($(CONFIG_UPDATE_IMAGE),y) # never update the bootblock + +ifneq ($(CONFIG_CPU_MICROCODE_CBFS_NONE),y) + +INTERMEDIATE+=add_mcu_fit +add_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) + @printf " UPDATE-FIT Microcode\n" + $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) -r COREBOOT + +# Second FIT in TOP_SWAP bootblock +ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y) + +INTERMEDIATE+=add_ts_mcu_fit +add_ts_mcu_fit: $(obj)/coreboot.pre $(IFITTOOL) + @printf " UPDATE-FIT Top Swap: Microcode\n" +ifneq ($(FIT_ENTRY),) + $(IFITTOOL) -f $< -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT +endif # FIT_ENTRY + $(IFITTOOL) -f $< -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) $(TS_OPTIONS) -r COREBOOT + +endif # CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK + +endif # CONFIG_CPU_MICROCODE_CBFS_NONE + +endif # CONFIG_UPDATE_IMAGE From ce04a42db9192aece8fc2d27a91fa498bcc2a698 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 26 Nov 2020 19:43:08 +0100 Subject: [PATCH 08/45] docs/mb/supermicro/x11ssm-f: Update board documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Drop vanished issue on PCIe warning - Drop TODO section, since the TODOs are done - Document the jumper J6, that was not documented by the vendor. Its function has been determined by dissecting a dead board. - The flash is not socketed anymore. Drop that note and compress the whole paragraph. Also add a note about flashing via the BMC web interface. Change-Id: I2b5a08a6b6d80717621d6a30f31829fe4b84891a Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/48125 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Felix Singer --- .../x11-lga1151-series/x11ssm-f/x11ssm-f.md | 17 ++++++++--------- 1 file changed, 8 insertions(+), 9 deletions(-) diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md index 5213bce6de..9f18b79cd8 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssm-f/x11ssm-f.md @@ -4,11 +4,11 @@ This section details how to run coreboot on the [Supermicro X11SSM-F]. ## Flashing coreboot -The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. +The board can be flashed externally. FTDI FT2232H and FT232H based programmers worked. For this, +one needs to add a diode between VCC and the flash chip. The flash IC [MX25L12873F] can be found +near PCH PCIe Slot 4. -The flash IC [MX25L12873F] can be found near PCH PCIe Slot 4. It is socketed on retail boards. - -For doing ISP (In-System-Programming) one needs to add a diode between VCC and the flash chip. +Flashing is also possible through the BMC web interface, when a valid license was entered. ## BMC (IPMI) @@ -16,6 +16,10 @@ This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC 32 MiB SOIC-16 chip in the corner of the mainboard near the PCH PCIe Slot 4. This chip is a [MX25L25635F]. +## Disabling LAN firmware + +To disable the proprietary LAN firmware, the undocumented jumper J6 can be set to 2-3. + ## Tested and working - GRUB2 payload with Debian testing and kernel 5.2 @@ -32,14 +36,9 @@ This board has an ASPEED [AST2400], which has BMC/[IPMI] functionality. The BMC ## Known issues - See general issue section -- "only partially covers this bridge" info from Linux kernel (what does that mean?) - LNXTHERM missing - S3 resume not working -## ToDo - -- Fix TODOs mentioned in code - ## Technology ```eval_rst From 4c56d79ba6d1e4d294d39dbbd72d0406f52dc0c4 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 26 Nov 2020 19:43:08 +0100 Subject: [PATCH 09/45] {docs/,}mb/supermicro/x11ssh-tf: drop TODO section MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop the TODO comment, since there is no TODO left. Also drop the now obsolete TODO section from the board documentation. Change-Id: I4192aaedc1429c8ff1bd7c52baa4741e1df0d0c5 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/48126 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Felix Singer --- .../supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md | 4 ---- .../variants/x11ssh-tf/include/variant/gpio.h | 1 - 2 files changed, 5 deletions(-) diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md index 1caa34b3f7..1616676453 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11ssh-tf/x11ssh-tf.md @@ -33,10 +33,6 @@ in a 32 MiB SOIC-16 chip in the corner of the mainboard near the [AST2400]. This See general issue section. -## ToDo - -- Fix TODOs mentioned in code - ## Technology ```eval_rst diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h index a6db277891..486caf4185 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h @@ -226,7 +226,6 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), }; -/*** XXX TODO XXX */ static const struct pad_config early_gpio_table[] = { /* Early LPC configuration in romstage */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), From 43dd2e458f75b5d398553611f2efc818c6b18c89 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Thu, 26 Nov 2020 19:43:08 +0100 Subject: [PATCH 10/45] docs/mb/supermicro/x11-lga-series: Update documentation MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit - Drop issue about non-working TianoCore with Aspeed NGI. see CB:35726 - Add missing reference to X11SSH-F - Drop TODO reference; there are no TODOs left Change-Id: I5becfa9ea01a0d9d651c6b51b30ebfcedb6412a5 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/48101 Reviewed-by: Patrick Rudolph Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- .../supermicro/x11-lga1151-series/x11-lga1151-series.md | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md index 2cb945ae14..03bebad0ed 100644 --- a/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md +++ b/Documentation/mainboard/supermicro/x11-lga1151-series/x11-lga1151-series.md @@ -7,6 +7,7 @@ Controller etc. ## Supported boards - [X11SSH-TF](x11ssh-tf/x11ssh-tf.md) +- [X11SSH-F](x11ssh-f/x11ssh-f.md) - [X11SSM-F](x11ssm-f/x11ssm-f.md) ## Required proprietary blobs @@ -30,14 +31,12 @@ Look at the [flashing tutorial] and the board-specific section. These issues apply to all boards. Have a look at the board-specific issues, too. -- TianoCore doesn't work with Aspeed NGI, as it's text mode only (Fix is WIP CB:35726) - MRC caching does not work on cold boot with Intel SPS (see [Intel FSP2.0]) ## ToDo - Fix issues above - Fix issues in board specific sections -- Fix TODOs mentioned in code - Add more boards! :-) ## Technology From 84fde762e7c4e1a8e43194a9444b10b681e1cb50 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Wed, 25 Nov 2020 16:36:18 +0100 Subject: [PATCH 11/45] soc/intel/skl: correct OC pin skip value for disabled usb ports MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Commit 056d552 introduced a bug where 0xFF gets set as OC pin value to supposedly skip programming an OC pin for a disabled USB port. While the value is correct for the other platforms, Skylake uses 0x08 for this purpose. Correct this by using the enum value OC_SKIP (0x08) instead. Change-Id: I41a8df3dce3712b4ab27c4e6e10160b2207406d1 Signed-off-by: Michael Niewöhner Reviewed-on: https://review.coreboot.org/c/coreboot/+/48003 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/soc/intel/skylake/chip.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index e2aee07114..ada06f217d 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -26,6 +26,7 @@ #include #include #include +#include #include #include "chip.h" @@ -151,16 +152,16 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) if (config->usb2_ports[i].enable) params->Usb2OverCurrentPin[i] = config->usb2_ports[i].ocpin; else - params->Usb2OverCurrentPin[i] = 0xff; + params->Usb2OverCurrentPin[i] = OC_SKIP; } for (i = 0; i < ARRAY_SIZE(config->usb3_ports); i++) { params->PortUsb30Enable[i] = config->usb3_ports[i].enable; - if (config->usb3_ports[i].enable) { + if (config->usb3_ports[i].enable) params->Usb3OverCurrentPin[i] = config->usb3_ports[i].ocpin; - } else { - params->Usb3OverCurrentPin[i] = 0xff; - } + else + params->Usb3OverCurrentPin[i] = OC_SKIP; + if (config->usb3_ports[i].tx_de_emp) { params->Usb3HsioTxDeEmphEnable[i] = 1; params->Usb3HsioTxDeEmph[i] = From ddd44f4fe9f45dfcdb2467073b4faf1fdb03ce47 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 24 Nov 2020 01:23:28 +0100 Subject: [PATCH 12/45] mb/supermicro/x11-lga1151-series: restructure and clean up devicetree MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Drop zero-value devicetree options and move PcieRpEnable options down to the corresponding devices. Test: built with TIMELESS=1; binaries remain identical Signed-off-by: Michael Niewöhner Change-Id: I9285d786e973621a732e2627c734adc930e54207 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48082 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer Reviewed-by: Arthur Heymans --- .../x11-lga1151-series/devicetree.cb | 21 ------------------- .../variants/x11ssh-tf/overridetree.cb | 17 ++++----------- .../variants/x11ssm-f/overridetree.cb | 12 +++++------ 3 files changed, 9 insertions(+), 41 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb index e7b26dc5de..c021372fb9 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/devicetree.cb @@ -1,10 +1,6 @@ chip soc/intel/skylake - register "deep_s5_enable_ac" = "0" - register "deep_s5_enable_dc" = "0" - # FSP Configuration - register "ScsEmmcHs400Enabled" = "0" register "SkipExtGfxScan" = "1" register "SaGv" = "SaGv_Disabled" @@ -22,20 +18,6 @@ chip soc/intel/skylake [7] = 1, \ }" - register "SataPortsDevSlp" = "{\ - [0] = 0, \ - [1] = 0, \ - [2] = 0, \ - [3] = 0, \ - [4] = 0, \ - [5] = 0, \ - [6] = 0, \ - [7] = 0, \ - }" - - # superspeed_inter-chip_supplement (SSIC) disabled - register "SsicPortEnable" = "0" - # LPC register "serirq_mode" = "SERIRQ_CONTINUOUS" @@ -46,9 +28,6 @@ chip soc/intel/skylake register "PmConfigSlpSusMinAssert" = "SLP_SUS_MIN_ASSERT_4S" register "PmConfigSlpAMinAssert" = "SLP_A_MIN_ASSERT_2S" - # No extra VR mailbox command - register "SendVrMbxCmd" = "0" - # Lock Down register "common_soc_config" = "{ .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb index 7996791a69..093786cbd5 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/overridetree.cb @@ -11,19 +11,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # PCIe configuration - # Enable JPCIE1 - register "PcieRpEnable[0]" = "1" - - # Enable ASpeed PCI bridge - register "PcieRpEnable[2]" = "1" - - # Enable X550T (10GbE) - register "PcieRpEnable[4]" = "1" - - # Enable M.2 - register "PcieRpEnable[8]" = "1" - # FIXME: find out why FSP crashes without this register "PchHdaVcType" = "Vc1" @@ -66,9 +53,11 @@ chip soc/intel/skylake device domain 0 on device pci 01.0 on end # unused device pci 01.1 on # PCIE Slot (JPCIE1) + register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT6 PCI-E 3.0 X8" "SlotDataBusWidth4X" end device pci 1c.0 on # PCI Express Port 1 (Slot JPCIE1) + register "PcieRpEnable[2]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X4" "SlotLengthLong" "PCH SLOT4 PCI-E 3.0 X2(IN X4)" "SlotDataBusWidth2X" end device pci 1c.2 on # PCI Express Port 3 @@ -77,10 +66,12 @@ chip soc/intel/skylake end end device pci 1c.4 on # PCI Express Port 5 + register "PcieRpEnable[4]" = "1" device pci 00.0 on end # 10GbE device pci 00.1 on end # 10GbE end device pci 1d.0 on # PCI Express Port 9 + register "PcieRpEnable[8]" = "1" smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2 2280" "SlotDataBusWidth4X" end device pci 1f.0 on # LPC Interface diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb index 8b0a2a0bd1..d7f187356f 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/overridetree.cb @@ -11,13 +11,6 @@ chip soc/intel/skylake register "gen1_dec" = "0x007c0a01" # Super IO SWC register "gen2_dec" = "0x000c0ca1" # IPMI KCS - # PCIe configuration - register "PcieRpEnable[0]" = "1" # Enable PCH PCIe Port 1 / PCH SLOT4 - register "PcieRpEnable[4]" = "1" # Enable PCH PCIe Port 5 / PCH SLOT5 - register "PcieRpEnable[8]" = "1" # Enable PCH PCIe Port 9 / GbE 1 - register "PcieRpEnable[9]" = "1" # Enable PCH PCIe Port 10 / GbE 2 - register "PcieRpEnable[10]" = "1" # Enable PCH PCIe Port 11 / Aspeed 2400 VGA - # USB configuration # USB0/1 register "usb2_ports[5]" = "USB2_PORT_MID(OC2)" @@ -58,18 +51,23 @@ chip soc/intel/skylake smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "CPU SLOT7 PCI-E 3.0 X8" "SlotDataBusWidth8X" end device pci 1c.0 on # PCH PCIe Port 1 / PCIe Slot 4 (JPCIE4) + register "PcieRpEnable[0]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT4 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1c.4 on # PCH PCIe Port 5 / PCIe Slot 5 (JPCIE5) + register "PcieRpEnable[4]" = "1" smbios_slot_desc "SlotTypePciExpressGen3X8" "SlotLengthShort" "PCH SLOT5 PCI-E 3.0 X4(IN X8)" "SlotDataBusWidth4X" end device pci 1d.0 on # PCH PCIe Port 9 + register "PcieRpEnable[8]" = "1" device pci 00.0 on end # GbE 1 end device pci 1d.1 on # PCH PCIe Port 10 + register "PcieRpEnable[9]" = "1" device pci 00.1 on end # GbE 2 end device pci 1d.2 on # PCH PCIe Port 11 + register "PcieRpEnable[10]" = "1" device pci 00.0 on # Aspeed PCI Bridge device pci 00.0 on end # Aspeed 2400 VGA end From 1b0d75177724ae00df399ffca36fd716b294063f Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 24 Nov 2020 13:57:48 +0100 Subject: [PATCH 13/45] mb/supermicro/x11-lga1151-series: configure gpios in mainboard init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Move gpio configuration from the Fsp callback to mainboard init. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner Change-Id: If2a54c75c5243d94cdc025c597ee347820b35d32 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48086 Reviewed-by: Felix Singer Tested-by: build bot (Jenkins) --- .../supermicro/x11-lga1151-series/Makefile.inc | 2 +- .../supermicro/x11-lga1151-series/mainboard.c | 4 +++- .../supermicro/x11-lga1151-series/ramstage.c | 11 ----------- 3 files changed, 4 insertions(+), 13 deletions(-) delete mode 100644 src/mainboard/supermicro/x11-lga1151-series/ramstage.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index d64fcb35ec..f9b4e9890b 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -2,7 +2,7 @@ bootblock-y += bootblock.c -ramstage-y += ramstage.c +ramstage-y += mainboard.c CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 0380c9848c..92718e8c0d 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -2,6 +2,8 @@ #include #include +#include +#include __weak void variant_mainboard_init(struct device *dev) { @@ -10,7 +12,7 @@ __weak void variant_mainboard_init(struct device *dev) static void mainboard_init(struct device *dev) { /* do common init */ - // placeholder for common mainboard initialization + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); /* do variant init */ variant_mainboard_init(dev); diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c deleted file mode 100644 index 9262e2ec1d..0000000000 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ /dev/null @@ -1,11 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include -#include - -void mainboard_silicon_init_params(FSP_SIL_UPD *params) -{ - /* Configure pads prior to SiliconInit() in case there's any - dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); -} From dc811c9ea3937b4265ce94c72e7dcba9fb122105 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 24 Nov 2020 01:01:05 +0100 Subject: [PATCH 14/45] mb/supermicro/x11ssm-f: drop unneeded ITSS override MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The ITSS override is not needed for LPC_CLKOUT* pads. Drop it. Signed-off-by: Michael Niewöhner Change-Id: I3dbbc8944751779151dcd4f92fb870d937801d69 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48084 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- .../x11-lga1151-series/variants/x11ssm-f/mainboard.c | 10 ---------- 1 file changed, 10 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c index 6f99d0760f..0b26e06aa4 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c @@ -2,21 +2,11 @@ #include #include -#include #include -#include #include void variant_mainboard_init(struct device *dev) { - /* TODO: - * Find out why the polarities from gpio.h gets overwritten by FSP. - * This sets irq polarity to the same values as vendor - * but I do not know if this is really needed.... - */ - itss_set_irq_polarity(33, 0); - itss_set_irq_polarity(34, 0); - // TODO: NMI; is this needed? vendor sets it pcr_write32(0xae, 0x01e4, 0x00000004); pcr_write32(0xae, 0x01e8, 0x00000040); From e88dacfa433840339355b7a634cd63f3fd22c5f7 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Mon, 23 Nov 2020 13:36:52 +0100 Subject: [PATCH 15/45] mb/supermicro/x11-lga1151-series: switch from dev.init to mb_ops.init MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit GPIO needs to be initialized before the IPMI device gets initialized, so the GPIOs can be read/set by the code in CB:48096 and CB:48094. Thus, use mainboard_ops.init for GPIO configuration instead of using the indirection via a mainboard_enable function. To make it more visible, that we use chip.init, rename `mainboard_init` to `mainboard_chip_init`. Tested successfully on X11SSM-F including the IPMI changes. Signed-off-by: Michael Niewöhner Change-Id: I192e69a34fa262b38bc40a95fb11c22a4041d0ae Reviewed-on: https://review.coreboot.org/c/coreboot/+/48083 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- .../x11-lga1151-series/include/mainboard.h | 2 +- .../supermicro/x11-lga1151-series/mainboard.c | 13 ++++--------- .../variants/x11ssm-f/mainboard.c | 2 +- 3 files changed, 6 insertions(+), 11 deletions(-) diff --git a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h index c63b434597..cad75f4baf 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h +++ b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard.h @@ -5,6 +5,6 @@ #include -void variant_mainboard_init(struct device *dev); +void variant_mainboard_init(void *chip_info); #endif /* _BASEBOARD_X11_LGA1151_SERIES_H */ diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 92718e8c0d..1377a874fe 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -5,24 +5,19 @@ #include #include -__weak void variant_mainboard_init(struct device *dev) +__weak void variant_mainboard_init(void *chip_info) { } -static void mainboard_init(struct device *dev) +static void mainboard_chip_init(void *chip_info) { /* do common init */ gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); /* do variant init */ - variant_mainboard_init(dev); -} - -static void mainboard_enable(struct device *dev) -{ - dev->ops->init = mainboard_init; + variant_mainboard_init(chip_info); } struct chip_operations mainboard_ops = { - .enable_dev = mainboard_enable, + .init = mainboard_chip_init, }; diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c index 0b26e06aa4..75351eb6de 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/mainboard.c @@ -5,7 +5,7 @@ #include #include -void variant_mainboard_init(struct device *dev) +void variant_mainboard_init(void *chip_info) { // TODO: NMI; is this needed? vendor sets it pcr_write32(0xae, 0x01e4, 0x00000004); From c1d1dddbccba1d1468b75bc8d4685bd8e7184264 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 24 Nov 2020 13:49:11 +0100 Subject: [PATCH 16/45] mb/supermicro/x11-lga1151-series: rework gpio setup to not use headers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Rework gpio setup for the board series to not use headers but stage-specific compilation units. Tested successfully on X11SSM-F. Signed-off-by: Michael Niewöhner Change-Id: Ic62ce4335af605c081ef288e892441585ff2bd3e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48087 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- .../x11-lga1151-series/Makefile.inc | 11 +++++----- .../supermicro/x11-lga1151-series/bootblock.c | 13 ++--------- .../include/mainboard/gpio.h | 9 ++++++++ .../supermicro/x11-lga1151-series/mainboard.c | 5 ++--- .../{include/variant/gpio.h => gpio.c} | 22 +++++-------------- .../variants/x11ssh-f/gpio_early.c | 22 +++++++++++++++++++ .../{include/variant/gpio.h => gpio.c} | 22 +++++-------------- .../variants/x11ssh-tf/gpio_early.c | 22 +++++++++++++++++++ .../{include/variant/gpio.h => gpio.c} | 22 +++++-------------- .../variants/x11ssm-f/gpio_early.c | 22 +++++++++++++++++++ 10 files changed, 100 insertions(+), 70 deletions(-) create mode 100644 src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h rename src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/{include/variant/gpio.h => gpio.c} (92%) create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c rename src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/{include/variant/gpio.h => gpio.c} (92%) create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c rename src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/{include/variant/gpio.h => gpio.c} (93%) create mode 100644 src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index f9b4e9890b..035dd281bb 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -1,10 +1,11 @@ ## SPDX-License-Identifier: GPL-2.0-only -bootblock-y += bootblock.c - -ramstage-y += mainboard.c - CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include +bootblock-y += bootblock.c +bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c + +ramstage-y += mainboard.c +ramstage-y += variants/$(VARIANT_DIR)/gpio.c + subdirs-y += variants/$(VARIANT_DIR) -CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include diff --git a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c index 3e5751c3d7..b137c75589 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/bootblock.c +++ b/src/mainboard/supermicro/x11-lga1151-series/bootblock.c @@ -1,20 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include -#include +#include #include #include #include -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't do. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); -} - static void early_config_superio(void) { const pnp_devfn_t serial_dev = PNP_DEV(0x2e, AST2400_SUART1); @@ -23,6 +14,6 @@ static void early_config_superio(void) void bootblock_mainboard_early_init(void) { - early_config_gpio(); + mainboard_configure_early_gpios(); early_config_superio(); } diff --git a/src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h new file mode 100644 index 0000000000..c6393beebb --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/include/mainboard/gpio.h @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +void mainboard_configure_early_gpios(void); +void mainboard_configure_gpios(void); + +#endif diff --git a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c index 1377a874fe..0f8dbed2ed 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/mainboard.c +++ b/src/mainboard/supermicro/x11-lga1151-series/mainboard.c @@ -2,8 +2,7 @@ #include #include -#include -#include +#include __weak void variant_mainboard_init(void *chip_info) { @@ -12,7 +11,7 @@ __weak void variant_mainboard_init(void *chip_info) static void mainboard_chip_init(void *chip_info) { /* do common init */ - gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + mainboard_configure_gpios(); /* do variant init */ variant_mainboard_init(chip_info); diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c similarity index 92% rename from src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h rename to src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c index 449349dc6c..e37e008285 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _GPIO_X11SSH_F_H -#define _GPIO_X11SSH_F_H - +#include #include #include @@ -226,17 +224,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), }; -static const struct pad_config early_gpio_table[] = { - /* Early LPC configuration in romstage */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -}; - -#endif /* _GPIO_X11SSH_F_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c new file mode 100644 index 0000000000..3ea21e0321 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-f/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c similarity index 92% rename from src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h rename to src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c index 486caf4185..06d3bd43c3 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _GPIO_X11SSH_TF_H -#define _GPIO_X11SSH_TF_H - +#include #include #include @@ -226,17 +224,7 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), }; -static const struct pad_config early_gpio_table[] = { - /* Early LPC configuration in romstage */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), -}; - -#endif /* _GPIO_X11SSH_TF_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c new file mode 100644 index 0000000000..3ea21e0321 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssh-tf/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c similarity index 93% rename from src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h rename to src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c index 8c9d08e5ef..dc41573224 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/include/variant/gpio.h +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio.c @@ -1,8 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef _GPIO_X11SSM_F_H -#define _GPIO_X11SSM_F_H - +#include #include #include @@ -232,17 +230,7 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPD11, NONE), }; -static const struct pad_config early_gpio_table[] = { - /* Early LPC configuration in romstage */ - PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), - PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), -}; - -#endif /* _GPIO_X11SSM_F_H */ +void mainboard_configure_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c new file mode 100644 index 0000000000..3ea21e0321 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/variants/x11ssm-f/gpio_early.c @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +static const struct pad_config early_gpio_table[] = { + /* Early LPC configuration in romstage */ + PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), +}; + +void mainboard_configure_early_gpios(void) +{ + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); +} From f79f00991cd708dd426e5509cbd398e2c1b244ed Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Michael=20Niew=C3=B6hner?= Date: Tue, 24 Nov 2020 14:33:15 +0100 Subject: [PATCH 17/45] mb/supermicro/x11-lga1151-series: set FADT PM profile to ENTERPRISE_SERVER MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Set the FADT PM profile to ENTERPRISE_SERVER, since the currently supported X11 boards are server boards. Signed-off-by: Michael Niewöhner Change-Id: I8fb5c7c262fbd3f3c085d7c2e2ef3d6ff6ce73eb Reviewed-on: https://review.coreboot.org/c/coreboot/+/48088 Reviewed-by: Patrick Rudolph Tested-by: build bot (Jenkins) --- src/mainboard/supermicro/x11-lga1151-series/Makefile.inc | 1 + src/mainboard/supermicro/x11-lga1151-series/fadt.c | 9 +++++++++ 2 files changed, 10 insertions(+) create mode 100644 src/mainboard/supermicro/x11-lga1151-series/fadt.c diff --git a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc index 035dd281bb..a4ebe461b0 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc +++ b/src/mainboard/supermicro/x11-lga1151-series/Makefile.inc @@ -7,5 +7,6 @@ bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c ramstage-y += mainboard.c ramstage-y += variants/$(VARIANT_DIR)/gpio.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += fadt.c subdirs-y += variants/$(VARIANT_DIR) diff --git a/src/mainboard/supermicro/x11-lga1151-series/fadt.c b/src/mainboard/supermicro/x11-lga1151-series/fadt.c new file mode 100644 index 0000000000..6306e03e30 --- /dev/null +++ b/src/mainboard/supermicro/x11-lga1151-series/fadt.c @@ -0,0 +1,9 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include + +void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ + fadt->preferred_pm_profile = PM_ENTERPRISE_SERVER; +} From 3a873b5c9a70ec41488161b491ffe5ac94bb554e Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Fri, 27 Nov 2020 00:20:18 +0530 Subject: [PATCH 18/45] mb/intel/adlrvp: Disable dq_pins_interleaved for DDR4/5 RVP TEST=Able to pass MRC training on DDR4/5 SKUs Change-Id: I38fcb17a1be5a8544a17cef8255631b6abef0741 Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/48078 Tested-by: build bot (Jenkins) Reviewed-by: Sridhar Siricilla Reviewed-by: V Sowmya Reviewed-by: Angel Pons --- src/mainboard/intel/adlrvp/memory.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c index cab4ef93f3..5d374db2a6 100644 --- a/src/mainboard/intel/adlrvp/memory.c +++ b/src/mainboard/intel/adlrvp/memory.c @@ -12,7 +12,7 @@ static const struct mb_cfg ddr4_mem_config = { /* Baseboard Rcomp target values */ .rcomp_targets = {40, 30, 33, 33, 30}, - .dq_pins_interleaved = true, + .dq_pins_interleaved = false, .ect = true, /* Early Command Training */ @@ -61,7 +61,7 @@ static const struct mb_cfg ddr5_mem_config = { /* Baseboard Rcomp target values */ .rcomp_targets = {50, 30, 30, 30, 27}, - .dq_pins_interleaved = true, + .dq_pins_interleaved = false, .ect = true, /* Early Command Training */ From 95ee5996f70c67c926e907d37f8f1f040fbcb3a6 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Mon, 9 Nov 2020 12:13:22 +0530 Subject: [PATCH 19/45] soc/intel/alderlake: Add lp5_ccc_config to the board memory configuration TEST=Able to pass LPDDR5 MRC training with Lp5CccConfig override. Signed-off-by: Sridhar Siricilla Change-Id: I24b1cf50c1b0b945fce75239bac38e40aeb8a83a Reviewed-on: https://review.coreboot.org/c/coreboot/+/47436 Reviewed-by: V Sowmya Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/include/soc/meminit.h | 8 ++++++++ src/soc/intel/alderlake/meminit.c | 1 + 2 files changed, 9 insertions(+) diff --git a/src/soc/intel/alderlake/include/soc/meminit.h b/src/soc/intel/alderlake/include/soc/meminit.h index 5fed5680c6..36d0750d37 100644 --- a/src/soc/intel/alderlake/include/soc/meminit.h +++ b/src/soc/intel/alderlake/include/soc/meminit.h @@ -90,6 +90,14 @@ struct mb_cfg { /* Board type */ uint8_t UserBd; + + /* + * Command pins mapping for Controller Channel (ccc) + * lp5_ccc_config: Bitmask where bits [3:0] are Controller 0 Channel [3:0] and + * bits [7:4] are Controller 1 Channel [3:0] + * Bit value: 0 = ccc pin mapping is ascending, 1 = ccc pin mapping is descending. + */ + uint8_t lp5_ccc_config; }; /* diff --git a/src/soc/intel/alderlake/meminit.c b/src/soc/intel/alderlake/meminit.c index f5f747d79b..8473ad8a48 100644 --- a/src/soc/intel/alderlake/meminit.c +++ b/src/soc/intel/alderlake/meminit.c @@ -178,6 +178,7 @@ void memcfg_init(FSP_M_CONFIG *mem_cfg, meminit_channels(mem_cfg, board_cfg, spd_data_ptr, half_populated); } + mem_cfg->Lp5CccConfig = board_cfg->lp5_ccc_config; mem_cfg->ECT = board_cfg->ect; mem_cfg->UserBd = board_cfg->UserBd; mem_cfg->DqPinsInterleaved = board_cfg->dq_pins_interleaved; From d149bfa17fb1fca7e0a388fd6c0cbb088069d0d5 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Sun, 22 Nov 2020 20:00:28 -0800 Subject: [PATCH 20/45] soc/intel: Configure P2SB before other PCH controllers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This change updates bootblock_pch_early_init() to perform P2SB configuration before any other PCH controllers are initialized. This is done because the other controllers might perform PCR settings which requires the PCR base address to be configured. As the PCR base address configuration happens during P2SB initialization, this change moves the p2sb init calls before any other PCH controller initialization. BUG=b:171534504 Change-Id: I485556be003ff5338b4e2046768fe4f6d8a619a3 Signed-off-by: Furquan Shaikh Reviewed-on: https://review.coreboot.org/c/coreboot/+/47885 Reviewed-by: Michael Niewöhner Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/bootblock/pch.c | 9 +++++++-- src/soc/intel/cannonlake/bootblock/pch.c | 9 +++++++-- src/soc/intel/elkhartlake/bootblock/pch.c | 9 +++++++-- src/soc/intel/icelake/bootblock/pch.c | 9 +++++++-- src/soc/intel/jasperlake/bootblock/pch.c | 9 +++++++-- src/soc/intel/skylake/bootblock/pch.c | 7 ++++++- src/soc/intel/tigerlake/bootblock/pch.c | 9 +++++++-- 7 files changed, 48 insertions(+), 13 deletions(-) diff --git a/src/soc/intel/alderlake/bootblock/pch.c b/src/soc/intel/alderlake/bootblock/pch.c index b7d2c15d3c..bc921e3a4a 100644 --- a/src/soc/intel/alderlake/bootblock/pch.c +++ b/src/soc/intel/alderlake/bootblock/pch.c @@ -65,11 +65,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/cannonlake/bootblock/pch.c b/src/soc/intel/cannonlake/bootblock/pch.c index 242aa71141..8ebfb3dcf3 100644 --- a/src/soc/intel/cannonlake/bootblock/pch.c +++ b/src/soc/intel/cannonlake/bootblock/pch.c @@ -77,11 +77,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/elkhartlake/bootblock/pch.c b/src/soc/intel/elkhartlake/bootblock/pch.c index 9224c486ec..e1b7d85c5a 100644 --- a/src/soc/intel/elkhartlake/bootblock/pch.c +++ b/src/soc/intel/elkhartlake/bootblock/pch.c @@ -62,11 +62,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/icelake/bootblock/pch.c b/src/soc/intel/icelake/bootblock/pch.c index f36bd31e3b..a6b6b20e67 100644 --- a/src/soc/intel/icelake/bootblock/pch.c +++ b/src/soc/intel/icelake/bootblock/pch.c @@ -58,11 +58,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/jasperlake/bootblock/pch.c b/src/soc/intel/jasperlake/bootblock/pch.c index f59d9c909f..96a7dc2b32 100644 --- a/src/soc/intel/jasperlake/bootblock/pch.c +++ b/src/soc/intel/jasperlake/bootblock/pch.c @@ -62,11 +62,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. diff --git a/src/soc/intel/skylake/bootblock/pch.c b/src/soc/intel/skylake/bootblock/pch.c index c6b2ad966a..38ae916dad 100644 --- a/src/soc/intel/skylake/bootblock/pch.c +++ b/src/soc/intel/skylake/bootblock/pch.c @@ -29,9 +29,14 @@ void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + + fast_spi_early_init(SPI_BASE_ADDRESS); } static void soc_config_acpibase(void) diff --git a/src/soc/intel/tigerlake/bootblock/pch.c b/src/soc/intel/tigerlake/bootblock/pch.c index 18ca5e51af..5c4d1d5fb7 100644 --- a/src/soc/intel/tigerlake/bootblock/pch.c +++ b/src/soc/intel/tigerlake/bootblock/pch.c @@ -67,11 +67,16 @@ static void soc_config_pwrmbase(void) void bootblock_pch_early_init(void) { - fast_spi_early_init(SPI_BASE_ADDRESS); - gspi_early_bar_init(); + /* + * Perform P2SB configuration before any another controller initialization as the + * controller might want to perform PCR settings. + */ p2sb_enable_bar(); p2sb_configure_hpet(); + fast_spi_early_init(SPI_BASE_ADDRESS); + gspi_early_bar_init(); + /* * Enabling PWRM Base for accessing * Global Reset Cause Register. From c97a1c0ac8e3fe2900eb296a7a2d05578d358bf0 Mon Sep 17 00:00:00 2001 From: Scott Chao Date: Thu, 26 Nov 2020 13:06:03 +0800 Subject: [PATCH 21/45] mb/google/volteer: eldrid: use devtree aliases for PMC MUX connectors Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. BUG=b:172528109 BRANCH=firmware-volteer-13521.B TEST=built and USB3.0, type-c display work. Signed-off-by: Scott Chao Change-Id: Iedf9b972b341064ff62a4443bfa83f69c8c60108 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48066 Reviewed-by: Zhuohao Lee Tested-by: build bot (Jenkins) --- .../google/volteer/variants/eldrid/overridetree.cb | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 51bc99159b..129d70482e 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -168,6 +168,13 @@ chip soc/intel/tigerlake device i2c 15 on end end end + device ref pch_espi on + chip ec/google/chromeec + use conn0 as mux_conn[0] + use conn1 as mux_conn[1] + device pnp 0c09.0 on end + end + end device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A"" @@ -185,14 +192,14 @@ chip soc/intel/tigerlake register "usb2_port_number" = "9" register "usb3_port_number" = "1" # SBU & HSL follow CC - device generic 0 on end + device generic 0 alias conn0 on end end chip drivers/intel/pmc_mux/conn register "usb2_port_number" = "4" register "usb3_port_number" = "2" # SBU is fixed, HSL follows CC register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL" - device generic 1 on end + device generic 1 alias conn1 on end end end end From a9db4bd9899feb8f6b464a9ee2cc88c4ed91d6fc Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 10 Nov 2020 18:17:10 +0100 Subject: [PATCH 22/45] mb/siemens/mc_apl1/mainboard.c: Refactor loop body Break down multi-line compound conditions into multiple if-statements, and leverage `continue` statements to avoid nesting multiple checks. Change-Id: I5edc279a57e25a0dff1a4b42f0bbc88c0659b476 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47403 Tested-by: build bot (Jenkins) Tested-by: siemens-bot Reviewed-by: Werner Zeh Reviewed-by: Uwe Poeche --- src/mainboard/siemens/mc_apl1/mainboard.c | 21 ++++++++++----------- 1 file changed, 10 insertions(+), 11 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 0d93563ccf..5b8f70f353 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -85,19 +85,18 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) /* Open main hwinfo block */ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) return CB_ERR; - /* Now try to find a valid MAC address in hwinfo for this mapping.*/ + /* Now try to find a valid MAC address in hwinfo for this mapping. */ for (i = 0; i < MAX_NUM_MAPPINGS; i++) { - if ((hwilib_get_field(XMac1Mapping + i, buf, 16) == 16) && - !(memcmp(buf, mapping, chain_len + 4))) { - /* There is a matching mapping available, get MAC address. */ - if ((hwilib_get_field(XMac1 + i, mac, 6) == 6) && - (is_mac_adr_valid(mac))) { - return CB_SUCCESS; - } else { - return CB_ERR; - } - } else + if (hwilib_get_field(XMac1Mapping + i, buf, 16) != 16) continue; + if (memcmp(buf, mapping, chain_len + 4)) + continue; + /* There is a matching mapping available, get MAC address. */ + if (hwilib_get_field(XMac1 + i, mac, 6) == 6) { + if (is_mac_adr_valid(mac)) + return CB_SUCCESS; + } + return CB_ERR; } /* No MAC address found for */ return CB_ERR; From c19a9a52783f7ed14fbe5beb7f1be15706222578 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 10 Nov 2020 17:08:11 +0100 Subject: [PATCH 23/45] drivers/intel/i210: Define MAC_ADDR_LEN Define and use the MAC_ADDR_LEN macro in place of the `6` magic value. Change-Id: Icfa2ad9bca6668bea3d84b10f613d01e437ac6a2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47404 Tested-by: siemens-bot Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh --- src/drivers/intel/i210/i210.h | 5 +++-- src/mainboard/siemens/mc_apl1/mainboard.c | 8 ++++---- 2 files changed, 7 insertions(+), 6 deletions(-) diff --git a/src/drivers/intel/i210/i210.h b/src/drivers/intel/i210/i210.h index 718992e477..1cc6a28a0b 100644 --- a/src/drivers/intel/i210/i210.h +++ b/src/drivers/intel/i210/i210.h @@ -27,9 +27,10 @@ #define I210_CHECKSUM_ERROR 0x00000010 #define I210_FLASH_UPDATE_ERROR 0x00000020 +#define MAC_ADDR_LEN 6 + /* We need one function we can call to get a MAC address to use */ /* This function can be coded somewhere else but must exist. */ -extern enum cb_err mainboard_get_mac_address(struct device *dev, - uint8_t mac[6]); +extern enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN]); #endif /* _INTEL_I210_H_ */ diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 5b8f70f353..ff0cc597bc 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -33,9 +33,9 @@ * @param mac Buffer to the MAC address to check * @return 0 if address is not valid, otherwise 1 */ -static uint8_t is_mac_adr_valid(uint8_t mac[6]) +static uint8_t is_mac_adr_valid(uint8_t mac[MAC_ADDR_LEN]) { - uint8_t buf[6]; + uint8_t buf[MAC_ADDR_LEN]; memset(buf, 0, sizeof(buf)); if (!memcmp(buf, mac, sizeof(buf))) @@ -52,7 +52,7 @@ static uint8_t is_mac_adr_valid(uint8_t mac[6]) * @param mac buffer where to store the MAC address * @return cb_err CB_ERR or CB_SUCCESS */ -enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) +enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[MAC_ADDR_LEN]) { struct bus *parent = dev->bus; uint8_t buf[16], mapping[16], i = 0, chain_len = 0; @@ -92,7 +92,7 @@ enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6]) if (memcmp(buf, mapping, chain_len + 4)) continue; /* There is a matching mapping available, get MAC address. */ - if (hwilib_get_field(XMac1 + i, mac, 6) == 6) { + if (hwilib_get_field(XMac1 + i, mac, MAC_ADDR_LEN) == MAC_ADDR_LEN) { if (is_mac_adr_valid(mac)) return CB_SUCCESS; } From afb60e7112d44d7b38226554bef366503f59d5c5 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 10 Nov 2020 17:10:01 +0100 Subject: [PATCH 24/45] mb/siemens/mc_apl1: Simplify is_mac_adr_valid() logic A MAC address that is neither 00:00:00:00:00:00 nor ff:ff:ff:ff:ff:ff is considered valid. Instead of using a temporary buffer and memcmp(), use a single loop that exits as soon as the MAC cannot possibly be invalid. Change-Id: I2b15b510092860fbbefd150c9060da38aeb13311 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47405 Tested-by: build bot (Jenkins) Reviewed-by: Werner Zeh Reviewed-by: Mario Scheithauer Reviewed-by: Uwe Poeche --- src/mainboard/siemens/mc_apl1/mainboard.c | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index ff0cc597bc..9540d6dca2 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -35,15 +35,13 @@ */ static uint8_t is_mac_adr_valid(uint8_t mac[MAC_ADDR_LEN]) { - uint8_t buf[MAC_ADDR_LEN]; - - memset(buf, 0, sizeof(buf)); - if (!memcmp(buf, mac, sizeof(buf))) - return 0; - memset(buf, 0xff, sizeof(buf)); - if (!memcmp(buf, mac, sizeof(buf))) - return 0; - return 1; + for (size_t i = 0; i < MAC_ADDR_LEN; i++) { + if (mac[i] != 0x00 && mac[i] != 0xff) + return 1; + if (mac[i] != mac[0]) + return 1; + } + return 0; } /** \brief This function will search for a MAC address which can be assigned From 45eeae4f8f3846a44b48b4334988e94c2776898d Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 10 Nov 2020 16:57:44 +0100 Subject: [PATCH 25/45] mb/siemens/mc_apl1: Deduplicate wait_for_legacy_dev() There's one copy of this function for all variants except mc_apl4. Move one copy into common mainboard.c and exit early if running on mc_apl4. Change-Id: I4e35b58adc074831ccec433b8e014db0695b955e Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47402 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/siemens/mc_apl1/mainboard.c | 32 +++++++++++++++++++ .../mc_apl1/variants/mc_apl1/mainboard.c | 28 ---------------- .../mc_apl1/variants/mc_apl2/mainboard.c | 29 ----------------- .../mc_apl1/variants/mc_apl3/mainboard.c | 28 ---------------- .../mc_apl1/variants/mc_apl5/mainboard.c | 28 ---------------- .../mc_apl1/variants/mc_apl6/mainboard.c | 28 ---------------- 6 files changed, 32 insertions(+), 141 deletions(-) diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c index 9540d6dca2..b2cd449b87 100644 --- a/src/mainboard/siemens/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/mainboard.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include #include #include #include @@ -13,6 +14,7 @@ #include #include #include +#include #include #include @@ -222,3 +224,33 @@ struct chip_operations mainboard_ops = { .init = mainboard_init, .final = mainboard_final, }; + +static void wait_for_legacy_dev(void *unused) +{ + uint32_t legacy_delay, us_since_boot; + struct stopwatch sw; + + if (CONFIG(BOARD_SIEMENS_MC_APL4)) + return; + + /* Open main hwinfo block. */ + if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) + return; + + /* Get legacy delay parameter from hwinfo. */ + if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, + sizeof(legacy_delay)) != sizeof(legacy_delay)) + return; + + us_since_boot = get_us_since_boot(); + /* No need to wait if the time since boot is already long enough.*/ + if (us_since_boot > legacy_delay) + return; + stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); + printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", + legacy_delay - us_since_boot, legacy_delay); + stopwatch_wait_until_expired(&sw); + printk(BIOS_NOTICE, "done!\n"); +} + +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c index e60ea647a9..5dbc4b9dec 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl1/mainboard.c @@ -9,8 +9,6 @@ #include #include #include -#include -#include #include #include @@ -51,36 +49,10 @@ void variant_mainboard_final(void) pcr_rmw32(PID_MODPHY, TX_DWORD3, (0x00 << 16), (0x4a << 16)); } -static void wait_for_legacy_dev(void *unused) -{ - uint32_t legacy_delay, us_since_boot; - struct stopwatch sw; - - /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) - return; - - /* Get legacy delay parameter from hwinfo. */ - if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, - sizeof(legacy_delay)) != sizeof(legacy_delay)) - return; - - us_since_boot = get_us_since_boot(); - /* No need to wait if the time since boot is already long enough.*/ - if (us_since_boot > legacy_delay) - return; - stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); - printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", - legacy_delay - us_since_boot, legacy_delay); - stopwatch_wait_until_expired(&sw); - printk(BIOS_NOTICE, "done!\n"); -} - static void finalize_boot(void *unused) { /* Set coreboot ready LED. */ gpio_output(CNV_RGI_DT, 1); } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c index 000ee0806c..9cfd86f287 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl2/mainboard.c @@ -7,8 +7,6 @@ #include #include #include -#include -#include #include #include #include @@ -23,30 +21,3 @@ void variant_mainboard_final(void) pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } } - -static void wait_for_legacy_dev(void *unused) -{ - uint32_t legacy_delay, us_since_boot; - struct stopwatch sw; - - /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) - return; - - /* Get legacy delay parameter from hwinfo. */ - if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, - sizeof(legacy_delay)) != sizeof(legacy_delay)) - return; - - us_since_boot = get_us_since_boot(); - /* No need to wait if the time since boot is already long enough.*/ - if (us_since_boot > legacy_delay) - return; - stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); - printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", - legacy_delay - us_since_boot, legacy_delay); - stopwatch_wait_until_expired(&sw); - printk(BIOS_NOTICE, "done!\n"); -} - -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c index 8b1a0e169f..22d2388a69 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c @@ -12,8 +12,6 @@ #include #include #include -#include -#include #include #include @@ -70,36 +68,10 @@ void variant_mainboard_final(void) outb(FULL_RST, RST_CNT); } -static void wait_for_legacy_dev(void *unused) -{ - uint32_t legacy_delay, us_since_boot; - struct stopwatch sw; - - /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) - return; - - /* Get legacy delay parameter from hwinfo. */ - if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, - sizeof(legacy_delay)) != sizeof(legacy_delay)) - return; - - us_since_boot = get_us_since_boot(); - /* No need to wait if the time since boot is already long enough.*/ - if (us_since_boot > legacy_delay) - return; - stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); - printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", - legacy_delay - us_since_boot, legacy_delay); - stopwatch_wait_until_expired(&sw); - printk(BIOS_NOTICE, "done!\n"); -} - static void finalize_boot(void *unused) { /* Set coreboot ready LED. */ gpio_output(CNV_RGI_DT, 1); } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c index c0a7d53f31..5a4c01fad2 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl5/mainboard.c @@ -10,8 +10,6 @@ #include #include #include -#include -#include #include #include @@ -69,36 +67,10 @@ void variant_mainboard_final(void) } } -static void wait_for_legacy_dev(void *unused) -{ - uint32_t legacy_delay, us_since_boot; - struct stopwatch sw; - - /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) - return; - - /* Get legacy delay parameter from hwinfo. */ - if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, - sizeof(legacy_delay)) != sizeof(legacy_delay)) - return; - - us_since_boot = get_us_since_boot(); - /* No need to wait if the time since boot is already long enough.*/ - if (us_since_boot > legacy_delay) - return; - stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); - printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", - legacy_delay - us_since_boot, legacy_delay); - stopwatch_wait_until_expired(&sw); - printk(BIOS_NOTICE, "done!\n"); -} - static void finalize_boot(void *unused) { /* Set coreboot ready LED. */ gpio_output(CNV_RGI_DT, 1); } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); diff --git a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c index f9345f499f..15c170b4ba 100644 --- a/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c +++ b/src/mainboard/siemens/mc_apl1/variants/mc_apl6/mainboard.c @@ -12,8 +12,6 @@ #include #include #include -#include -#include #include #include @@ -70,36 +68,10 @@ void variant_mainboard_final(void) outb(FULL_RST, RST_CNT); } -static void wait_for_legacy_dev(void *unused) -{ - uint32_t legacy_delay, us_since_boot; - struct stopwatch sw; - - /* Open main hwinfo block. */ - if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS) - return; - - /* Get legacy delay parameter from hwinfo. */ - if (hwilib_get_field(LegacyDelay, (uint8_t *) &legacy_delay, - sizeof(legacy_delay)) != sizeof(legacy_delay)) - return; - - us_since_boot = get_us_since_boot(); - /* No need to wait if the time since boot is already long enough.*/ - if (us_since_boot > legacy_delay) - return; - stopwatch_init_msecs_expire(&sw, (legacy_delay - us_since_boot) / 1000); - printk(BIOS_NOTICE, "Wait remaining %d of %d us for legacy devices...", - legacy_delay - us_since_boot, legacy_delay); - stopwatch_wait_until_expired(&sw); - printk(BIOS_NOTICE, "done!\n"); -} - static void finalize_boot(void *unused) { /* Set coreboot ready LED. */ gpio_output(CNV_RGI_DT, 1); } -BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, wait_for_legacy_dev, NULL); BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_BOOT, BS_ON_ENTRY, finalize_boot, NULL); From 5ad4206e72a315c70904716c461cc1d8c7a855df Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 10 Nov 2020 16:25:47 +0100 Subject: [PATCH 26/45] drivers/intel/i210: Request Bus Master in .final ops Commit bd31642ad8 (intel/i210: Set bus master bit in command register) is only necessary because a buggy OS expects Bus Master to be set, not because the hardware requires Bus Master during initialization. It is thus safe to defer the Bus Master request into the .final callback. Change-Id: Iecfa6366eb4b1438fd12cd9ebb1a77ada97fa2f6 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47401 Reviewed-by: Felix Held Reviewed-by: Felix Singer Reviewed-by: Werner Zeh Tested-by: build bot (Jenkins) Tested-by: siemens-bot --- src/drivers/intel/i210/i210.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/drivers/intel/i210/i210.c b/src/drivers/intel/i210/i210.c index 852f368e5c..8caa194a9e 100644 --- a/src/drivers/intel/i210/i210.c +++ b/src/drivers/intel/i210/i210.c @@ -206,17 +206,17 @@ static void init(struct device *dev) return; } -static void set_resources(struct device *dev) +static void enable_bus_master(struct device *dev) { - pci_dev_set_resources(dev); - dev->command |= PCI_COMMAND_MASTER; + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); } static struct device_operations i210_ops = { .read_resources = pci_dev_read_resources, - .set_resources = set_resources, + .set_resources = pci_dev_set_resources, .enable_resources = pci_dev_enable_resources, .init = init, + .final = enable_bus_master, }; static const unsigned short i210_device_ids[] = { 0x1537, 0x1538, 0x1533, 0 }; From 63d36bc733a97ebf2a1c2f088d2fe834896d2087 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 23 Nov 2020 15:54:28 +0100 Subject: [PATCH 27/45] soc/amd/common/block/cpu: move CAR-specific Makefile to sub-directory Since there are sub-directories for both the cache-as-RAM case and the non-CAR case where the RAM is already initialized when the x86 cores are released from reset, move the CAR-specific parts of the Makefile.inc to another Makefile.inc in the car sub-directory. Further patches will add a Makefile.inc to the non-CAR directory. Change-Id: I43a3039237d96e02baa33488e71c5f24effe8359 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47875 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/cpu/Makefile.inc | 9 +-------- src/soc/amd/common/block/cpu/car/Makefile.inc | 8 ++++++++ 2 files changed, 9 insertions(+), 8 deletions(-) create mode 100644 src/soc/amd/common/block/cpu/car/Makefile.inc diff --git a/src/soc/amd/common/block/cpu/Makefile.inc b/src/soc/amd/common/block/cpu/Makefile.inc index 395ab084a3..df2ccfaa2e 100644 --- a/src/soc/amd/common/block/cpu/Makefile.inc +++ b/src/soc/amd/common/block/cpu/Makefile.inc @@ -1,8 +1 @@ -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/cache_as_ram.S -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/ap_exit_car.S -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S - -postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S - -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/ap_exit_car.S -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car/exit_car.S +subdirs-$(CONFIG_SOC_AMD_COMMON_BLOCK_CAR) += car diff --git a/src/soc/amd/common/block/cpu/car/Makefile.inc b/src/soc/amd/common/block/cpu/car/Makefile.inc new file mode 100644 index 0000000000..639914040f --- /dev/null +++ b/src/soc/amd/common/block/cpu/car/Makefile.inc @@ -0,0 +1,8 @@ +bootblock-y += cache_as_ram.S +bootblock-y += ap_exit_car.S +bootblock-y += exit_car.S + +postcar-y += exit_car.S + +romstage-y += ap_exit_car.S +romstage-y += exit_car.S From 870e44a7b91a5db34123591d2cb99f491a0cb3b1 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 23 Nov 2020 15:58:09 +0100 Subject: [PATCH 28/45] soc/amd/common: simplify conditionals in Makefiles If there are multiple statements that are conditional on the same Kconfig option, group them and move the condition check around the statement. If there's only one statement depending on one condition, use the short form instead. Change-Id: I89cb17954150c146ffc762d8cb2e3b3b374924de Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47876 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/acpi/Makefile.inc | 16 +++++--- .../amd/common/block/acpimmio/Makefile.inc | 28 ++++++++------ src/soc/amd/common/block/alink/Makefile.inc | 16 +++++--- .../amd/common/block/gpio_banks/Makefile.inc | 16 +++++--- src/soc/amd/common/block/lpc/Makefile.inc | 30 +++++++++------ src/soc/amd/common/block/psp/Makefile.inc | 37 ++++++++++++------- src/soc/amd/common/block/spi/Makefile.inc | 8 +--- 7 files changed, 91 insertions(+), 60 deletions(-) diff --git a/src/soc/amd/common/block/acpi/Makefile.inc b/src/soc/amd/common/block/acpi/Makefile.inc index f0b336d46d..10e522f064 100644 --- a/src/soc/amd/common/block/acpi/Makefile.inc +++ b/src/soc/amd/common/block/acpi/Makefile.inc @@ -1,6 +1,10 @@ -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c -postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI) += acpi.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPI),y) + +bootblock-y += acpi.c +verstage_x86-y += acpi.c +romstage-y += acpi.c +ramstage-y += acpi.c +postcar-y += acpi.c +smm-y += acpi.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPI diff --git a/src/soc/amd/common/block/acpimmio/Makefile.inc b/src/soc/amd/common/block/acpimmio/Makefile.inc index 553d9e23ca..6b3e423a76 100644 --- a/src/soc/amd/common/block/acpimmio/Makefile.inc +++ b/src/soc/amd/common/block/acpimmio/Makefile.inc @@ -1,13 +1,17 @@ -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c -postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += mmio_util.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO),y) -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO) += biosram.c +bootblock-y += mmio_util.c +verstage-y += mmio_util.c +romstage-y += mmio_util.c +postcar-y += mmio_util.c +ramstage-y += mmio_util.c +smm-y += mmio_util.c + +bootblock-y += biosram.c +verstage_x86-y += biosram.c +romstage-y += biosram.c +postcar-y += biosram.c +ramstage-y += biosram.c +smm-y += biosram.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_ACPIMMIO diff --git a/src/soc/amd/common/block/alink/Makefile.inc b/src/soc/amd/common/block/alink/Makefile.inc index 9d27aec174..b393c3db13 100644 --- a/src/soc/amd/common/block/alink/Makefile.inc +++ b/src/soc/amd/common/block/alink/Makefile.inc @@ -1,6 +1,10 @@ -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c -verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c -postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK) += alink.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_ALINK),y) + +bootblock-y += alink.c +verstage_x86-y += alink.c +romstage-y += alink.c +postcar-y += alink.c +ramstage-y += alink.c +smm-y += alink.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_ALINK diff --git a/src/soc/amd/common/block/gpio_banks/Makefile.inc b/src/soc/amd/common/block/gpio_banks/Makefile.inc index f1555b12b8..5b738bd371 100644 --- a/src/soc/amd/common/block/gpio_banks/Makefile.inc +++ b/src/soc/amd/common/block/gpio_banks/Makefile.inc @@ -1,6 +1,10 @@ -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c -postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS) += gpio.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS),y) + +bootblock-y += gpio.c +verstage-y += gpio.c +romstage-y += gpio.c +postcar-y += gpio.c +ramstage-y += gpio.c +smm-y += gpio.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_BANKED_GPIOS diff --git a/src/soc/amd/common/block/lpc/Makefile.inc b/src/soc/amd/common/block/lpc/Makefile.inc index 7db176b31d..68e528ffa2 100644 --- a/src/soc/amd/common/block/lpc/Makefile.inc +++ b/src/soc/amd/common/block/lpc/Makefile.inc @@ -1,13 +1,21 @@ -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_LPC),y) -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c -postcar-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_LPC) += lpc_util.c +ramstage-y += lpc.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c -verstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI) += espi_util.c +bootblock-y += lpc_util.c +verstage-y += lpc_util.c +romstage-y += lpc_util.c +postcar-y += lpc_util.c +ramstage-y += lpc_util.c +smm-y += lpc_util.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_LPC + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI),y) + +bootblock-y += espi_util.c +romstage-y += espi_util.c +ramstage-y += espi_util.c +verstage-y += espi_util.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_USE_ESPI diff --git a/src/soc/amd/common/block/psp/Makefile.inc b/src/soc/amd/common/block/psp/Makefile.inc index c2a33354ad..363a0abb7c 100644 --- a/src/soc/amd/common/block/psp/Makefile.inc +++ b/src/soc/amd/common/block/psp/Makefile.inc @@ -1,16 +1,27 @@ -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c -bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP),y) -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c -romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c +bootblock-y += psp.c +romstage-y += psp.c +ramstage-y += psp.c +smm-y += psp.c +smm-y += psp_smm.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c -ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP) += psp_smm.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1) += psp_gen1.c -smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2) += psp_gen2.c +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1),y) + +bootblock-y += psp_gen1.c +romstage-y += psp_gen1.c +ramstage-y += psp_gen1.c +smm-y += psp_gen1.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN1 + +ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2),y) + +bootblock-y += psp_gen2.c +romstage-y += psp_gen2.c +ramstage-y += psp_gen2.c +smm-y += psp_gen2.c + +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PSP_GEN2 diff --git a/src/soc/amd/common/block/spi/Makefile.inc b/src/soc/amd/common/block/spi/Makefile.inc index c8b733fe04..c58df39a3d 100644 --- a/src/soc/amd/common/block/spi/Makefile.inc +++ b/src/soc/amd/common/block/spi/Makefile.inc @@ -5,18 +5,14 @@ romstage-y += fch_spi_ctrl.c verstage-y += fch_spi_ctrl.c postcar-y += fch_spi_ctrl.c ramstage-y += fch_spi_ctrl.c -ifeq ($(CONFIG_SPI_FLASH_SMM),y) -smm-y += fch_spi_ctrl.c -endif +smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi_ctrl.c bootblock-y += fch_spi.c romstage-y += fch_spi.c postcar-y += fch_spi.c ramstage-y += fch_spi.c verstage-y += fch_spi.c -ifeq ($(CONFIG_SPI_FLASH_SMM),y) -smm-y += fch_spi.c -endif +smm-$(CONFIG_SPI_FLASH_SMM) += fch_spi.c bootblock-y += fch_spi_util.c romstage-y += fch_spi_util.c From 41220cd2453b232759aeb7aa7694e9139ede7a50 Mon Sep 17 00:00:00 2001 From: Felix Held Date: Mon, 23 Nov 2020 16:08:54 +0100 Subject: [PATCH 29/45] soc/amd/common: add comments and FIXME to Makefile.inc files Change-Id: Ie347ee508acd900353467b4a3e0a5d1928b110e1 Signed-off-by: Felix Held Reviewed-on: https://review.coreboot.org/c/coreboot/+/47877 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) --- src/soc/amd/common/block/pci/Makefile.inc | 2 +- src/soc/amd/common/block/pi/Makefile.inc | 2 +- src/soc/amd/common/block/s3/Makefile.inc | 2 +- src/soc/amd/common/block/smbus/Makefile.inc | 2 +- 4 files changed, 4 insertions(+), 4 deletions(-) diff --git a/src/soc/amd/common/block/pci/Makefile.inc b/src/soc/amd/common/block/pci/Makefile.inc index baebb6c33f..1fed96e45a 100644 --- a/src/soc/amd/common/block/pci/Makefile.inc +++ b/src/soc/amd/common/block/pci/Makefile.inc @@ -1,6 +1,6 @@ - ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PCI) += amd_pci_util.c +# FIXME: This gets added when CONFIG_SOC_AMD_COMMON is set, which is a bit unexpected. bootblock-y += amd_pci_mmconf.c verstage_x86-y += amd_pci_mmconf.c romstage-y += amd_pci_mmconf.c diff --git a/src/soc/amd/common/block/pi/Makefile.inc b/src/soc/amd/common/block/pi/Makefile.inc index 5afbb3ebdb..7b5d73af9c 100644 --- a/src/soc/amd/common/block/pi/Makefile.inc +++ b/src/soc/amd/common/block/pi/Makefile.inc @@ -14,4 +14,4 @@ ramstage-y += heapmanager.c ramstage-y += image.c ramstage-y += refcode_loader.c -endif +endif # CONFIG_SOC_AMD_COMMON_BLOCK_PI diff --git a/src/soc/amd/common/block/s3/Makefile.inc b/src/soc/amd/common/block/s3/Makefile.inc index 9efc6bc414..03395eca9c 100644 --- a/src/soc/amd/common/block/s3/Makefile.inc +++ b/src/soc/amd/common/block/s3/Makefile.inc @@ -3,4 +3,4 @@ ifeq ($(CONFIG_SOC_AMD_COMMON_BLOCK_S3),y) romstage-y += s3_resume.c ramstage-y += s3_resume.c -endif +endif # CONFIG_SOC_AMD_COMMON_BLOCK_S3 diff --git a/src/soc/amd/common/block/smbus/Makefile.inc b/src/soc/amd/common/block/smbus/Makefile.inc index cfc954ec4f..b9c7f2a51f 100644 --- a/src/soc/amd/common/block/smbus/Makefile.inc +++ b/src/soc/amd/common/block/smbus/Makefile.inc @@ -4,4 +4,4 @@ romstage-y += smbus.c ramstage-y += smbus.c ramstage-y += sm.c -endif +endif # CONFIG_SOC_AMD_COMMON_BLOCK_SMBUS From 1e678169616b959921c38a2f25ca23b7f3e4cc77 Mon Sep 17 00:00:00 2001 From: Pratik Prajapati Date: Thu, 3 Sep 2020 11:28:19 -0700 Subject: [PATCH 30/45] inteltool: Add support to print TME/MKTME status Print whether the SOC supports TME/MKTME. If the SOC supports the feature, print the status of enable and lock bit from TME_ACTIVATE MSR. -t option prints this status. Sample output: If TME/MKTME is supported: ============= Dumping INTEL TME/MKTME status ============= TME supported : YES TME locked : YES TME enabled : YES ==================================================== If TME/MKTME is not supported: ============= Dumping INTEL TME status ============= TME supported : NO ==================================================== Signed-off-by: Pratik Prajapati Change-Id: I584ac4b045ba80998d454283e02d3f28ef45692d Reviewed-on: https://review.coreboot.org/c/coreboot/+/45088 Tested-by: build bot (Jenkins) Reviewed-by: Stefan Reinauer --- util/inteltool/cpu.c | 53 ++++++++++++++++++++++++++++++++++++++ util/inteltool/inteltool.c | 13 ++++++++-- util/inteltool/inteltool.h | 1 + 3 files changed, 65 insertions(+), 2 deletions(-) diff --git a/util/inteltool/cpu.c b/util/inteltool/cpu.c index 284e90b50e..db63d36729 100644 --- a/util/inteltool/cpu.c +++ b/util/inteltool/cpu.c @@ -22,6 +22,10 @@ #define MTRR_CAP_MSR 0xfe #define PRMRR_SUPPORTED (1 << 12) #define SGX_SUPPORTED (1 << 2) +#define IA32_TME_ACTIVATE 0x982 +#define TME_SUPPORTED (1 << 13) +#define TME_LOCKED (1) +#define TME_ENABLED (1 << 1) int fd_msr; @@ -212,6 +216,55 @@ int print_sgx(void) return error; } +static int is_tme_supported() +{ + cpuid_result_t cpuid_regs; + + /* + * CPUID leaf 0x7 subleaf 0x0 to detect TME support + * https://software.intel.com/sites/default/files/managed/a5/16/Multi-Key + * -Total-Memory-Encryption-Spec.pdf + */ + + cpuid_regs = cpuid_ext(0x7, 0x0); + return (cpuid_regs.ecx & TME_SUPPORTED); +} + +static msr_t read_tme_activate_msr(){ + return rdmsr_from_cpu(0, IA32_TME_ACTIVATE); +} + +static int is_tme_locked() +{ + msr_t data = read_tme_activate_msr(); + return (data.lo & TME_LOCKED); +} + +static int is_tme_enabled() +{ + msr_t data = read_tme_activate_msr(); + return (data.lo & TME_ENABLED); +} + +void print_tme(void) +{ +#ifndef __DARWIN__ + int tme_supported = is_tme_supported(); + + printf("\n============= Dumping INTEL TME status =============\n"); + + printf("TME supported : %s\n", tme_supported ? "YES" : "NO"); + + if (tme_supported) { + printf("TME locked : %s\n", is_tme_locked() ? "YES" : "NO"); + printf("TME enabled : %s\n", is_tme_enabled() ? "YES" : "NO"); + } + printf("====================================================\n"); +#else + printf("Not Implemented\n"); +#endif +} + int print_intel_core_msrs(void) { unsigned int i, core, id, core_num = get_number_of_cores(); diff --git a/util/inteltool/inteltool.c b/util/inteltool/inteltool.c index 5ecd8cacb8..d7415b07d2 100644 --- a/util/inteltool/inteltool.c +++ b/util/inteltool/inteltool.c @@ -515,6 +515,7 @@ static void print_usage(const char *name) " -M | --msrs: dump CPU MSRs\n" " -A | --ambs: dump AMB registers\n" " -x | --sgx: dump SGX status\n" + " -t | --tme: dump TME status\n" " -a | --all: dump all known (safe) registers\n" " --pcr=PORT_ID: dump all registers of a PCR port\n" " (may be specified max %d times)\n" @@ -575,7 +576,7 @@ int main(int argc, char *argv[]) int dump_gpios = 0, dump_mchbar = 0, dump_rcba = 0; int dump_pmbase = 0, dump_epbar = 0, dump_dmibar = 0; int dump_pciexbar = 0, dump_coremsrs = 0, dump_ambs = 0; - int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0; + int dump_spi = 0, dump_gfx = 0, dump_ahci = 0, dump_sgx = 0, dump_tme = 0; int dump_lpc = 0; int show_gpio_diffs = 0; size_t pcr_count = 0; @@ -602,10 +603,11 @@ int main(int argc, char *argv[]) {"ahci", 0, 0, 'R'}, {"sgx", 0, 0, 'x'}, {"pcr", required_argument, 0, LONG_OPT_PCR}, + {"tme", 0, 0, 't'}, {0, 0, 0, 0} }; - while ((opt = getopt_long(argc, argv, "vh?gGrplmedPMaAsfRS:x", + while ((opt = getopt_long(argc, argv, "vh?gGrplmedPMaAsfRS:xt", long_options, &option_index)) != EOF) { switch (opt) { case 'v': @@ -667,6 +669,7 @@ int main(int argc, char *argv[]) dump_spi = 1; dump_ahci = 1; dump_sgx = 1; + dump_tme = 1; break; case 'A': dump_ambs = 1; @@ -677,6 +680,9 @@ int main(int argc, char *argv[]) case 'x': dump_sgx = 1; break; + case 't': + dump_tme = 1; + break; case LONG_OPT_PCR: if (pcr_count < MAX_PCR_PORTS) { errno = 0; @@ -869,6 +875,9 @@ int main(int argc, char *argv[]) if (dump_sgx) print_sgx(); + if (dump_tme) + print_tme(); + if (pcr_count) print_pcr_ports(sb, dump_pcr, pcr_count); diff --git a/util/inteltool/inteltool.h b/util/inteltool/inteltool.h index b3253e7d9c..a528485bf0 100644 --- a/util/inteltool/inteltool.h +++ b/util/inteltool/inteltool.h @@ -411,6 +411,7 @@ int print_spi(struct pci_dev *sb); int print_gfx(struct pci_dev *gfx); int print_ahci(struct pci_dev *ahci); int print_sgx(void); +void print_tme(void); void ivybridge_dump_timings(const char *dump_spd_file); #endif From 329ebb340b157bc64065473a960a97eae0e30914 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 24 Nov 2020 15:03:38 +0100 Subject: [PATCH 31/45] mb/prodrive/hermes: Use C-style comments Most of the existing comments are C-style already. Change-Id: I9ca4779f5b0560320e9bce4f33e54766522689f9 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47957 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/mainboard/prodrive/hermes/eeprom.c | 6 +++--- src/mainboard/prodrive/hermes/ramstage.c | 4 ++-- src/mainboard/prodrive/hermes/romstage.c | 2 +- src/mainboard/prodrive/hermes/variants/baseboard/gpio.c | 2 +- .../prodrive/hermes/variants/baseboard/include/eeprom.h | 2 +- 5 files changed, 8 insertions(+), 8 deletions(-) diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index bd5db5c851..94811f68d1 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -14,7 +14,7 @@ int check_signature(u8 addr) u8 blob[8] = {0}; if (!read_write_config(addr, blob, EEPROM_OFFSET_FSP_SIGNATURE, 0, ARRAY_SIZE(blob))) { - // Check Signature + /* Check signature */ if (*(uint64_t *)blob == FSP_UPD_SIGNATURE) { printk(BIOS_DEBUG, "CFG EEPROM: Signature valid.\n"); return 1; @@ -25,7 +25,7 @@ int check_signature(u8 addr) return 0; } -// Read data from offset and write it to offset in UPD +/* Read data from offset and write it to offset in UPD */ bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_offset, size_t size) { @@ -52,7 +52,7 @@ bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_off if (ret < 0) break; - // Write to UPD + /* Write to UPD */ uint8_t *writePointer = (uint8_t *)blob + write_offset + i; if (size > 1 && (size % 2 == 0)) memcpy(writePointer, tmp, 2); diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index 18fc915018..135d7754aa 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -5,7 +5,7 @@ #include "variants/baseboard/include/eeprom.h" static fsp_params parmas_list[] = { - // FIXME: Fill with additional options + /* FIXME: Fill with additional options */ }; void mainboard_silicon_init_params(FSP_S_CONFIG *params) @@ -19,7 +19,7 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params) params->SataLedEnable = 1; - // Overwrite params + /* Overwrite params */ if (!check_signature(I2C_ADDR_EEPROM)) return; diff --git a/src/mainboard/prodrive/hermes/romstage.c b/src/mainboard/prodrive/hermes/romstage.c index a25c43a743..2bcd27ace0 100644 --- a/src/mainboard/prodrive/hermes/romstage.c +++ b/src/mainboard/prodrive/hermes/romstage.c @@ -18,7 +18,7 @@ void mainboard_memory_init_params(FSPM_UPD *memupd) memupd->FspmConfig.IedSize = 0x400000; cannonlake_memcfg_init(&memupd->FspmConfig, variant_memcfg_config()); - // Overwrite memupd + /* Overwrite memupd */ if (!check_signature(I2C_ADDR_EEPROM)) return; diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c index 9c01d2470d..8735a9ef4b 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c +++ b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c @@ -194,7 +194,7 @@ static const struct pad_config gpio_table[] = { /* GPP_K20 - CPU_CATERR_PCH_n */ PAD_CFG_GPI(GPP_K20, NONE, DEEP), /* GPP_K21 - TPM_INT_n */ - PAD_CFG_GPI_INT(GPP_K21, NONE, DEEP, OFF), // Trigger? + PAD_CFG_GPI_INT(GPP_K21, NONE, DEEP, OFF), /* Trigger? */ /* GPP_K22 - NC */ PAD_NC(GPP_K22, NONE), /* GPP_K23 - NC */ diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h index c41ead28ab..79fda3c755 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/eeprom.h @@ -21,7 +21,7 @@ #define EEPROM_OFFSET_FSP_CONFIG (EEPROM_OFFSET_FSP_SIGNATURE + sizeof(FSP_UPD_HEADER)) #define GET_VALUE(x) {.offset = offsetof(FSP_S_CONFIG, x), \ .size = member_size(FSP_S_CONFIG, x)} -#endif // ENV_ROMSTAGE +#endif /* ENV_ROMSTAGE */ typedef struct { size_t offset; From fe17a8cd6a2e734bd1bb8be45a41b3e1d46ab904 Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 24 Nov 2020 15:26:10 +0100 Subject: [PATCH 32/45] mb/prodrive/hermes: Encapsulate GPIO setup Having variants' gpio.c call the `gpio_configure_pads` function results in an API that does not need to pass data around, which is much simpler. Change-Id: I1064dc6258561bcf83f0e249d65b823368cf0d31 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47958 Tested-by: build bot (Jenkins) Reviewed-by: Felix Singer --- src/mainboard/prodrive/hermes/bootblock.c | 16 ++++------------ src/mainboard/prodrive/hermes/ramstage.c | 5 +---- .../prodrive/hermes/variants/baseboard/gpio.c | 12 ++++++------ .../variants/baseboard/include/variant/gpio.h | 7 ++----- 4 files changed, 13 insertions(+), 27 deletions(-) diff --git a/src/mainboard/prodrive/hermes/bootblock.c b/src/mainboard/prodrive/hermes/bootblock.c index 1426a552d4..40fd0b48a3 100644 --- a/src/mainboard/prodrive/hermes/bootblock.c +++ b/src/mainboard/prodrive/hermes/bootblock.c @@ -6,20 +6,12 @@ #include #include "gpio.h" -static void early_config_gpio(void) -{ - /* This is a hack for FSP because it does things in MemoryInit() - * which it shouldn't do. We have to prepare certain gpios here - * because of the brokenness in FSP. */ - size_t num = 0; - const struct pad_config *early_gpio_table = get_early_gpio_table(&num); - - gpio_configure_pads(early_gpio_table, num); -} - void bootblock_mainboard_early_init(void) { - early_config_gpio(); + /* This is a hack for FSP because it does things in MemoryInit() + which it shouldn't do. We have to prepare certain gpios here + because of the brokenness in FSP. */ + program_early_gpio_pads(); } void bootblock_mainboard_init(void) diff --git a/src/mainboard/prodrive/hermes/ramstage.c b/src/mainboard/prodrive/hermes/ramstage.c index 135d7754aa..e3dfffc2b3 100644 --- a/src/mainboard/prodrive/hermes/ramstage.c +++ b/src/mainboard/prodrive/hermes/ramstage.c @@ -10,12 +10,9 @@ static fsp_params parmas_list[] = { void mainboard_silicon_init_params(FSP_S_CONFIG *params) { - size_t num = 0; - const struct pad_config *gpio_table = get_gpio_table(&num); - /* Configure pads prior to SiliconInit() in case there's any dependencies during hardware initialization. */ - gpio_configure_pads(gpio_table, num); + program_gpio_pads(); params->SataLedEnable = 1; diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c index 8735a9ef4b..096dc35785 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c +++ b/src/mainboard/prodrive/hermes/variants/baseboard/gpio.c @@ -2,6 +2,8 @@ #include "include/variant/gpio.h" #include +#include +#include /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { @@ -389,14 +391,12 @@ const struct pad_config early_gpio_table[] = { PAD_CFG_GPO(GPP_H5, 0, DEEP), /* PCH_HBLED_n */ }; -const struct pad_config *get_gpio_table(size_t *num) +void program_gpio_pads(void) { - *num = ARRAY_SIZE(gpio_table); - return gpio_table; + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); } -const struct pad_config *get_early_gpio_table(size_t *num) +void program_early_gpio_pads(void) { - *num = ARRAY_SIZE(early_gpio_table); - return early_gpio_table; + gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table)); } diff --git a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h index 50d18018f0..8fce3c8b39 100644 --- a/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h +++ b/src/mainboard/prodrive/hermes/variants/baseboard/include/variant/gpio.h @@ -3,10 +3,7 @@ #ifndef PCH_GPIO_H #define PCH_GPIO_H -#include -#include - -const struct pad_config *get_gpio_table(size_t *num); -const struct pad_config *get_early_gpio_table(size_t *num); +void program_gpio_pads(void); +void program_early_gpio_pads(void); #endif /* PCH_GPIO_H */ From 13c50005c5e11bdf132e43dd72df0b8d263c7deb Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Tue, 24 Nov 2020 15:39:26 +0100 Subject: [PATCH 33/45] mb/prodrive/hermes: Use PCH_DEV_SMBUS definition This allows dropping ugly preprocessor usage from this file. Change-Id: Idb66d295129d98725f38d11ac162978418bd94c2 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/47959 Tested-by: build bot (Jenkins) Reviewed-by: Patrick Georgi --- src/mainboard/prodrive/hermes/eeprom.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/src/mainboard/prodrive/hermes/eeprom.c b/src/mainboard/prodrive/hermes/eeprom.c index 94811f68d1..fee40a0783 100644 --- a/src/mainboard/prodrive/hermes/eeprom.c +++ b/src/mainboard/prodrive/hermes/eeprom.c @@ -31,14 +31,8 @@ bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_off { int ret = 0; -#if ENV_ROMSTAGE - pci_devfn_t dev = PCI_DEV(0, PCH_DEV_SLOT_LPC, 4); -#else - const struct device *dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 4); -#endif - - u32 smb_ctrl_reg = pci_read_config32(dev, HOSTC); - pci_write_config32(dev, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN); + u32 smb_ctrl_reg = pci_read_config32(PCH_DEV_SMBUS, HOSTC); + pci_write_config32(PCH_DEV_SMBUS, HOSTC, smb_ctrl_reg | HOSTC_I2C_EN); printk(BIOS_SPEW, "%s\tOffset: %04zx\tSize: %02zx\n", __func__, read_offset, size); @@ -61,7 +55,7 @@ bool read_write_config(u8 addr, void *blob, size_t read_offset, size_t write_off } /* Restore I2C_EN bit */ - pci_write_config32(dev, HOSTC, smb_ctrl_reg); + pci_write_config32(PCH_DEV_SMBUS, HOSTC, smb_ctrl_reg); return ret; } From ace29dff9e96bc7868581deefea1840bc0857c6b Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 24 Nov 2020 21:32:18 +0000 Subject: [PATCH 34/45] lp4x: Add new memory parts and generate SPDs Add MT53D512M64D4NW-046 WT:F memory part to LP4x global list of available LP4x parts and to the global JSON file containing LP4x parts and their characteristics. BUG=b:172993397 TEST=none Change-Id: I09c6eab640c169dbdb451964967d14a31e314496 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/47980 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh Reviewed-by: Rob Barnes --- .../tigerlake/spd/lp4x_spd_manifest.generated.txt | 1 + util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt | 12 ++++++++++++ 2 files changed, 13 insertions(+) diff --git a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt index c7e969084f..f09a27f7f7 100644 --- a/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt +++ b/src/soc/intel/tigerlake/spd/lp4x_spd_manifest.generated.txt @@ -16,3 +16,4 @@ MT53E1G64D8NW-046 WT:E,lp4x-spd-3.hex H9HCNNNCRMBLPR-NEE,lp4x-spd-1.hex H9HCNNNFBMBLPR-NEE,lp4x-spd-3.hex MT53D1G64D4NW-046 WT:A,lp4x-spd-4.hex +MT53D512M64D4NW-046 WT:F,lp4x-spd-1.hex diff --git a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt index 91062d0000..ffb08c728d 100644 --- a/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt +++ b/util/spd_tools/lp4x/global_lp4x_mem_parts.json.txt @@ -217,6 +217,18 @@ "ranksPerChannel": 1, "speedMbps": 4267 } + }, + { + "name": "MT53D512M64D4NW-046 WT:F", + "attribs": { + "densityPerChannelGb": 8, + "banks": 8, + "channelsPerDie": 2, + "diesPerPackage": 2, + "bitWidthPerChannel": 16, + "ranksPerChannel": 1, + "speedMbps": 4267 + } } ] } From b38ca863d9a41dd6ab9881a00fe6eda8c5108e75 Mon Sep 17 00:00:00 2001 From: Nick Vaccaro Date: Tue, 24 Nov 2020 21:40:50 +0000 Subject: [PATCH 35/45] mb/google/volteer/variant/copano: Add memory part support Add support for the following 5 LPDDR4x memory parts: - MT53E512M64D4NW-046 WT:E - H9HCNNNCRMBLPR-NEE - MT53D1G64D4NW-046 WT:A - H9HCNNNFBMBLPR-NEE - MT53D512M64D4NW-046 WT:F DRAM Part Name ID to assign ------------------------------------------- MT53E512M64D4NW-046 WT:E 0 (0000) H9HCNNNCRMBLPR-NEE 0 (0000) MT53D1G64D4NW-046 WT:A 1 (0001) H9HCNNNFBMBLPR-NEE 2 (0010) MT53D512M64D4NW-046 WT:F 0 (0000) BUG=b:172993397 TEST=none Change-Id: Iff8f6257c6cff77fc3f0bda7e75434f9f4de1777 Signed-off-by: Nick Vaccaro Reviewed-on: https://review.coreboot.org/c/coreboot/+/47981 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/volteer/variants/copano/memory/Makefile.inc | 7 +++++++ .../volteer/variants/copano/memory/dram_id.generated.txt | 6 ++++++ .../volteer/variants/copano/memory/mem_list_variant.txt | 5 +++++ 3 files changed, 18 insertions(+) create mode 100644 src/mainboard/google/volteer/variants/copano/memory/Makefile.inc create mode 100644 src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt diff --git a/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc b/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc new file mode 100644 index 0000000000..511ab5b234 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/Makefile.inc @@ -0,0 +1,7 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! + +SPD_SOURCES = +SPD_SOURCES += lp4x-spd-1.hex # ID = 0(0b0000) Parts = MT53E512M64D4NW-046 WT:E, H9HCNNNCRMBLPR-NEE, MT53D512M64D4NW-046 WT:F +SPD_SOURCES += lp4x-spd-4.hex # ID = 1(0b0001) Parts = MT53D1G64D4NW-046 WT:A +SPD_SOURCES += lp4x-spd-3.hex # ID = 2(0b0010) Parts = H9HCNNNFBMBLPR-NEE diff --git a/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt b/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt new file mode 100644 index 0000000000..a8b78f5625 --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/dram_id.generated.txt @@ -0,0 +1,6 @@ +DRAM Part Name ID to assign +MT53E512M64D4NW-046 WT:E 0 (0000) +H9HCNNNCRMBLPR-NEE 0 (0000) +MT53D1G64D4NW-046 WT:A 1 (0001) +H9HCNNNFBMBLPR-NEE 2 (0010) +MT53D512M64D4NW-046 WT:F 0 (0000) diff --git a/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt b/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt new file mode 100644 index 0000000000..4afc39046c --- /dev/null +++ b/src/mainboard/google/volteer/variants/copano/memory/mem_list_variant.txt @@ -0,0 +1,5 @@ +MT53E512M64D4NW-046 WT:E +H9HCNNNCRMBLPR-NEE +MT53D1G64D4NW-046 WT:A +H9HCNNNFBMBLPR-NEE +MT53D512M64D4NW-046 WT:F From f90056268fe0280da600703baebf5a0623f019e1 Mon Sep 17 00:00:00 2001 From: Frans Hendriks Date: Wed, 25 Nov 2020 12:19:51 +0100 Subject: [PATCH 36/45] util/docker/Makefile: Add missing separator Build using docker results in error: Makefile:86: *** missing separator. Add space after ifeq. Tested: Building Facebook FBG1701 binary. Change-Id: Ib42abe966e67dac380173ec982c9f6bd4cf074cc Signed-off-by: Frans Hendriks Reviewed-on: https://review.coreboot.org/c/coreboot/+/47992 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Wim Vervoorn Reviewed-by: Angel Pons --- util/docker/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/util/docker/Makefile b/util/docker/Makefile index 8b1d0efb8d..cf14c0d5b4 100644 --- a/util/docker/Makefile +++ b/util/docker/Makefile @@ -83,7 +83,7 @@ docker-clean: clean-coreboot-containers @$(MAKE) clean-coreboot-images docker-cleanall: test-docker -ifeq($(Y),1) +ifeq ($(Y),1) @if [ -n "$$($(DOCKER) ps -a | grep -v "CONTAINER")" ]; then \ $(DOCKER) kill $$($(DOCKER) ps | grep -v "CONTAINER" | sed 's|\s.*$$||') ; \ $(DOCKER) rm $$($(DOCKER) ps -a | grep -v "CONTAINER" | sed 's|\s.*$$||'); \ From f1b4a7c9d4e8eb5884efab2d29f49812326f66e2 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 10 Nov 2020 09:55:57 -0700 Subject: [PATCH 37/45] elog: Add new wake source codes Tiger Lake introduces new wake-capable devices, including thunderbolt ports, TCSS XHCI & XDCI as well as DMA ports. Add new ELOG_WAKE_SOURCE macros for each of these types of devices. Signed-off-by: Tim Wawrzynczak Change-Id: Ie5dae6514c2776b30418a390c4da53bda0b2d456 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47395 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/include/elog.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/include/elog.h b/src/include/elog.h index 8c50e00ba5..3071271b3e 100644 --- a/src/include/elog.h +++ b/src/include/elog.h @@ -120,6 +120,10 @@ #define ELOG_WAKE_SOURCE_PME_PCIE23 0x2a #define ELOG_WAKE_SOURCE_PME_PCIE24 0x2b #define ELOG_WAKE_SOURCE_GPIO 0x2c +#define ELOG_WAKE_SOURCE_PME_TBT 0x2d +#define ELOG_WAKE_SOURCE_PME_TCSS_XHCI 0x2e +#define ELOG_WAKE_SOURCE_PME_TCSS_XDCI 0x2f +#define ELOG_WAKE_SOURCE_PME_TCSS_DMA 0x30 struct elog_event_data_wake { u8 source; From c67e3c1a905fea91e8ac0973857ad142b0337a00 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 10 Nov 2020 11:56:18 -0700 Subject: [PATCH 38/45] soc/intel/tigerlake: Add some helper macros for accessing TCSS DMA devices Change-Id: I6289d2049fbbb6bb532be3d9e2355c563ec98d1b Signed-off-by: Tim Wawrzynczak Reviewed-on: https://review.coreboot.org/c/coreboot/+/47410 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- src/soc/intel/tigerlake/include/soc/pci_devs.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/tigerlake/include/soc/pci_devs.h b/src/soc/intel/tigerlake/include/soc/pci_devs.h index cfb70cdb9f..ac0498fe26 100644 --- a/src/soc/intel/tigerlake/include/soc/pci_devs.h +++ b/src/soc/intel/tigerlake/include/soc/pci_devs.h @@ -50,10 +50,12 @@ #define SA_DEV_TBT3 PCI_DEV(0, SA_DEV_SLOT_TBT, 3) #define SA_DEV_SLOT_TCSS 0x0d +#define NUM_TCSS_DMA_FUNCTIONS 2 +#define SA_DEVFN_TCSS_DMA(x) PCI_DEVFN(SA_DEV_SLOT_TCSS, ((x) + 2)) #define SA_DEVFN_TCSS_XHCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 0) #define SA_DEVFN_TCSS_XDCI PCI_DEVFN(SA_DEV_SLOT_TCSS, 1) -#define SA_DEVFN_TCSS_DMA0 PCI_DEVFN(SA_DEV_SLOT_TCSS, 2) -#define SA_DEVFN_TCSS_DMA1 PCI_DEVFN(SA_DEV_SLOT_TCSS, 3) +#define SA_DEVFN_TCSS_DMA0 SA_DEVFN_TCSS_DMA(0) +#define SA_DEVFN_TCSS_DMA1 SA_DEVFN_TCSS_DMA(1) #define SA_DEV_TCSS_XHCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 0) #define SA_DEV_TCSS_XDCI PCI_DEV(0, SA_DEV_SLOT_TCSS, 1) #define SA_DEV_TCSS_DMA0 PCI_DEV(0, SA_DEV_SLOT_TCSS, 2) From 2821cb498b6d85548e42852b6e1ad25cb648c44d Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Wed, 25 Nov 2020 16:38:08 -0800 Subject: [PATCH 39/45] include/device/pci_ids.h: Fix device id for gspi2 Device ID for "D18:F6 - GSPI #2" shoud be 0xA0FB BUG=none TEST=Boot to OS, verify SSDT Signed-off-by: Selma BENSAID Signed-off-by: Bora Guvendik Change-Id: I0d814170d24ff1b989eceb1d9ebdf6134df85e2e Reviewed-on: https://review.coreboot.org/c/coreboot/+/48060 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/include/device/pci_ids.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/include/device/pci_ids.h b/src/include/device/pci_ids.h index c123002b75..51c0abf5f3 100644 --- a/src/include/device/pci_ids.h +++ b/src/include/device/pci_ids.h @@ -3563,7 +3563,7 @@ #define PCI_DEVICE_ID_INTEL_TGP_SPI0 0xa0a4 #define PCI_DEVICE_ID_INTEL_TGP_GSPI0 0xa0aa #define PCI_DEVICE_ID_INTEL_TGP_GSPI1 0xa0ab -#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0x34fb +#define PCI_DEVICE_ID_INTEL_TGP_GSPI2 0xa0fb #define PCI_DEVICE_ID_INTEL_TGP_GSPI3 0xa0fd #define PCI_DEVICE_ID_INTEL_TGP_GSPI4 0xa0fe #define PCI_DEVICE_ID_INTEL_TGP_GSPI5 0xa0de From 092813a50ce4198d622daa809181216b6ffd1bd4 Mon Sep 17 00:00:00 2001 From: Tim Wawrzynczak Date: Tue, 24 Nov 2020 13:48:56 -0700 Subject: [PATCH 40/45] soc/intel/alderlake: Add initial chipset.cb Similar to the chipset.cb for TGL, this patch gives alias names to all of the published PCI devices. Signed-off-by: Tim Wawrzynczak Change-Id: I6576ef4237c1fc8439795ad5b64b1840504edf73 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48009 Reviewed-by: Furquan Shaikh Reviewed-by: EricR Lai Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/soc/intel/alderlake/Kconfig | 4 ++ src/soc/intel/alderlake/chipset.cb | 67 ++++++++++++++++++++++++++++++ 2 files changed, 71 insertions(+) create mode 100644 src/soc/intel/alderlake/chipset.cb diff --git a/src/soc/intel/alderlake/Kconfig b/src/soc/intel/alderlake/Kconfig index 0aab3c582f..7e693cb373 100644 --- a/src/soc/intel/alderlake/Kconfig +++ b/src/soc/intel/alderlake/Kconfig @@ -92,6 +92,10 @@ config FSP_TEMP_RAM_SIZE Refer to Platform FSP integration guide document to know the exact FSP requirement for Heap setup. +config CHIPSET_DEVICETREE + string + default "soc/intel/alderlake/chipset.cb" + config IFD_CHIPSET string default "adl" diff --git a/src/soc/intel/alderlake/chipset.cb b/src/soc/intel/alderlake/chipset.cb new file mode 100644 index 0000000000..ff81560261 --- /dev/null +++ b/src/soc/intel/alderlake/chipset.cb @@ -0,0 +1,67 @@ +chip soc/intel/alderlake + device domain 0 on + device pci 00.0 alias system_agent on end + device pci 01.0 alias pcie5 off end + device pci 02.0 alias igpu off end + device pci 04.0 alias dtt off end + device pci 06.0 alias pcie4_0 off end + device pci 06.2 alias pcie4_1 off end + device pci 07.0 alias tbt_pcie_rp0 off end + device pci 07.1 alias tbt_pcie_rp1 off end + device pci 07.2 alias tbt_pcie_rp2 off end + device pci 07.3 alias tbt_pcie_rp3 off end + device pci 08.0 alias gna off end + device pci 09.0 alias north_tracehub off end + device pci 0a.0 alias crashlog off end + device pci 0d.0 alias north_xhci off end + device pci 0d.1 alias north_xdci off end + device pci 0d.2 alias tbt_dma0 off end + device pci 0d.3 alias tbt_dma1 off end + device pci 0e.0 alias vmd off end + device pci 10.6 alias thc0 off end + device pci 10.7 alias thc1 off end + device pci 12.0 alias ish off end + device pci 12.6 alias gspi2 off end + device pci 13.0 alias gspi3 off end + device pci 14.0 alias south_xhci off end + device pci 14.1 alias south_xdci off end + device pci 14.2 alias shared_sram off end + device pci 14.3 alias cnvi_wifi off end + device pci 15.0 alias i2c0 off end + device pci 15.1 alias i2c1 off end + device pci 15.2 alias i2c2 off end + device pci 15.3 alias i2c3 off end + device pci 16.0 alias heci1 off end + device pci 16.1 alias heci2 off end + device pci 16.4 alias heci3 off end + device pci 16.5 alias heci4 off end + device pci 17.0 alias sata off end + device pci 19.0 alias i2c4 off end + device pci 19.1 alias i2c5 off end + device pci 19.2 alias uart2 off end + device pci 1c.0 alias pcie_rp1 off end + device pci 1c.1 alias pcie_rp2 off end + device pci 1c.2 alias pcie_rp3 off end + device pci 1c.3 alias pcie_rp4 off end + device pci 1c.4 alias pcie_rp5 off end + device pci 1c.5 alias pcie_rp6 off end + device pci 1c.6 alias pcie_rp7 off end + device pci 1c.7 alias pcie_rp8 off end + device pci 1d.0 alias pcie_rp9 off end + device pci 1d.1 alias pcie_rp10 off end + device pci 1d.2 alias pcie_rp11 off end + device pci 1d.3 alias pcie_rp12 off end + device pci 1e.0 alias uart0 off end + device pci 1e.1 alias uart1 off end + device pci 1e.2 alias gspi0 off end + device pci 1e.3 alias gspi1 off end + device pci 1f.0 alias pch_espi on end + device pci 1f.1 alias p2sb off end + device pci 1f.2 alias pmc hidden end + device pci 1f.3 alias hda off end + device pci 1f.4 alias smbus off end + device pci 1f.5 alias fast_spi on end + device pci 1f.6 alias gbe off end + device pci 1f.7 alias south_tracehub off end + end +end From ae99ea5f08ffa3f59864c5ed7f06e00db31218fd Mon Sep 17 00:00:00 2001 From: Frank Chu Date: Thu, 19 Nov 2020 15:13:45 +0800 Subject: [PATCH 41/45] mb/google/volteer/variants/delbin: Enhance I2C5 bus freq closer 400 kHz The current I2C5 bus frequency is 367 kHZ, which does not meet the spec. This change updates scl_lcnt, scl_hcnt, scl_hcnt value for I2C5 to bring the bus frequency closer to 400kHz. BUG=b:173670150 TEST=Verified that I2C5 frequency is between 386-387kHz. Signed-off-by: Frank Chu Change-Id: I6d60abe15645dc51ed9ee30975d2521b8940c2d0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47736 Reviewed-by: Zhuohao Lee Reviewed-by: Zhuohao Lee Tested-by: build bot (Jenkins) --- .../volteer/variants/delbin/overridetree.cb | 43 +++++++++++++++++++ 1 file changed, 43 insertions(+) diff --git a/src/mainboard/google/volteer/variants/delbin/overridetree.cb b/src/mainboard/google/volteer/variants/delbin/overridetree.cb index bd4bf8041e..904f3e0e2e 100644 --- a/src/mainboard/google/volteer/variants/delbin/overridetree.cb +++ b/src/mainboard/google/volteer/variants/delbin/overridetree.cb @@ -2,6 +2,49 @@ chip soc/intel/tigerlake register "DdiPort1Hpd" = "0" register "DdiPort2Hpd" = "0" + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Audio | + #| I2C1 | Touchscreen | + #| I2C2 | WLAN, SAR0 | + #| I2C3 | Camera, SAR1 | + #| I2C5 | Trackpad | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[5] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 163, + .scl_hcnt = 75, + .sda_hold = 36, + }, + }, + }" + # Acoustic settings register "AcousticNoiseMitigation" = "1" register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" From 4ae881a576cae1af70cd9d979aa401c140f14ed3 Mon Sep 17 00:00:00 2001 From: Mike Banon Date: Tue, 24 Nov 2020 17:41:52 +0300 Subject: [PATCH 42/45] lenovo/g505s: remove the unused and not present devices Remove the devices unused or not present on this laptop. Signed-off-by: Mike Banon Change-Id: I0decad499dfbb5f1e0a189d21f0fca47c80bd490 Reviewed-on: https://review.coreboot.org/c/coreboot/+/47913 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/mainboard/lenovo/g505s/acpi/routing.asl | 146 -------------------- src/mainboard/lenovo/g505s/mptable.c | 37 ----- 2 files changed, 183 deletions(-) diff --git a/src/mainboard/lenovo/g505s/acpi/routing.asl b/src/mainboard/lenovo/g505s/acpi/routing.asl index bf6a881405..6f91672106 100644 --- a/src/mainboard/lenovo/g505s/acpi/routing.asl +++ b/src/mainboard/lenovo/g505s/acpi/routing.asl @@ -19,12 +19,6 @@ Package(){0x0002FFFF, 2, INTA, 0 }, Package(){0x0002FFFF, 3, INTB, 0 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, INTD, 0 }, - Package(){0x0003FFFF, 1, INTA, 0 }, - Package(){0x0003FFFF, 2, INTB, 0 }, - Package(){0x0003FFFF, 3, INTC, 0 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, INTA, 0 }, Package(){0x0004FFFF, 1, INTB, 0 }, @@ -37,20 +31,6 @@ Package(){0x0005FFFF, 2, INTD, 0 }, Package(){0x0005FFFF, 3, INTA, 0 }, - /* Bus 0, Dev 6 - PCIe Bridge for Ethernet Chip */ - Package(){0x0006FFFF, 0, INTC, 0 }, - Package(){0x0006FFFF, 1, INTD, 0 }, - Package(){0x0006FFFF, 2, INTA, 0 }, - Package(){0x0006FFFF, 3, INTB, 0 }, - - /* Bus 0, Dev 7 - PCIe Bridge for x1 PCIe Slot */ - Package(){0x0007FFFF, 0, INTD, 0 }, - Package(){0x0007FFFF, 1, INTA, 0 }, - Package(){0x0007FFFF, 2, INTB, 0 }, - Package(){0x0007FFFF, 3, INTC, 0 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI,F1:IDE;F2:HDAudio;F3:LPC;F4:PCIBridge;F5:USB */ Package(){0x0014FFFF, 0, INTA, 0 }, Package(){0x0014FFFF, 1, INTB, 0 }, @@ -75,12 +55,6 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, INTD, 0 }, - - /* Bus 0, Dev 21 PCIe Bridge */ - Package(){0x0015FFFF, 0, INTA, 0 }, - Package(){0x0015FFFF, 1, INTB, 0 }, - Package(){0x0015FFFF, 2, INTC, 0 }, - Package(){0x0015FFFF, 3, INTD, 0 }, }) Name(APR0, Package(){ @@ -97,12 +71,6 @@ Package(){0x0002FFFF, 2, 0, 16 }, Package(){0x0002FFFF, 3, 0, 17 }, - /* Bus 0, Dev 3 - PCIe graphics port 1 bridge */ - Package(){0x0003FFFF, 0, 0, 19 }, - Package(){0x0003FFFF, 1, 0, 16 }, - Package(){0x0003FFFF, 2, 0, 17 }, - Package(){0x0003FFFF, 3, 0, 18 }, - /* Bus 0, Dev 4 - PCIe Bridge for Express Card Slot */ Package(){0x0004FFFF, 0, 0, 16 }, Package(){0x0004FFFF, 1, 0, 17 }, @@ -115,20 +83,6 @@ Package(){0x0005FFFF, 2, 0, 19 }, Package(){0x0005FFFF, 3, 0, 16 }, - /* Bus 0, Dev 6 - General purpose PCIe bridge 6 */ - Package(){0x0006FFFF, 0, 0, 18 }, - Package(){0x0006FFFF, 1, 0, 19 }, - Package(){0x0006FFFF, 2, 0, 16 }, - Package(){0x0006FFFF, 3, 0, 17 }, - - /* Bus 0, Dev 7 - PCIe Bridge for network card */ - Package(){0x0007FFFF, 0, 0, 19 }, - Package(){0x0007FFFF, 1, 0, 16 }, - Package(){0x0007FFFF, 2, 0, 17 }, - Package(){0x0007FFFF, 3, 0, 18 }, - - /* Bus 0, Dev 8 - Southbridge port (normally hidden) */ - /* Bus 0, Dev 20 - F0:SMBus/ACPI, F1:IDE; F2:HDAudio; F3:LPC; F4:PCIBridge; F5:USB */ Package(){0x0014FFFF, 0, 0, 16 }, Package(){0x0014FFFF, 1, 0, 17 }, @@ -153,12 +107,6 @@ /* Bus 0, Dev 17 - SATA controller */ Package(){0x0011FFFF, 0, 0, 19 }, - - /* Bus0, Dev 21 PCIE Bridge */ - Package(){0x0015FFFF, 0, 0, 16 }, - Package(){0x0015FFFF, 1, 0, 17 }, - Package(){0x0015FFFF, 2, 0, 18 }, - Package(){0x0015FFFF, 3, 0, 19 }, }) Name(PS2, Package(){ @@ -205,107 +153,13 @@ Package(){0x0000FFFF, 2, 0, 19 }, Package(){0x0000FFFF, 3, 0, 16 }, }) - Name(PS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, }) Name(APS6, Package(){ - /* PCIe slot - Hooked to PCIe slot 6 */ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, }) - Name(PS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, }) Name(APS7, Package(){ - /* The onboard Ethernet chip - Dev 7 Parmer Hooked to RTK8111E Ethernet Card x1 Device7-GPP3 J16B*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, }) - - Name(PE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, INTA, 0 }, - Package(){0x0000FFFF, 1, INTB, 0 }, - Package(){0x0000FFFF, 2, INTC, 0 }, - Package(){0x0000FFFF, 3, INTD, 0 }, - }) - Name(APE0, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 0*/ - Package(){0x0000FFFF, 0, 0, 16 }, - Package(){0x0000FFFF, 1, 0, 17 }, - Package(){0x0000FFFF, 2, 0, 18 }, - Package(){0x0000FFFF, 3, 0, 19 }, - }) - - Name(PE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, INTB, 0 }, - Package(){0x0000FFFF, 1, INTC, 0 }, - Package(){0x0000FFFF, 2, INTD, 0 }, - Package(){0x0000FFFF, 3, INTA, 0 }, - }) - Name(APE1, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 1*/ - Package(){0x0000FFFF, 0, 0, 17 }, - Package(){0x0000FFFF, 1, 0, 18 }, - Package(){0x0000FFFF, 2, 0, 19 }, - Package(){0x0000FFFF, 3, 0, 16 }, - }) - - Name(PE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, INTC, 0 }, - Package(){0x0000FFFF, 1, INTD, 0 }, - Package(){0x0000FFFF, 2, INTA, 0 }, - Package(){0x0000FFFF, 3, INTB, 0 }, - }) - Name(APE2, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 2*/ - Package(){0x0000FFFF, 0, 0, 18 }, - Package(){0x0000FFFF, 1, 0, 19 }, - Package(){0x0000FFFF, 2, 0, 16 }, - Package(){0x0000FFFF, 3, 0, 17 }, - }) - - Name(PE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3 */ - Package(){0x0000FFFF, 0, INTD, 0 }, - Package(){0x0000FFFF, 1, INTA, 0 }, - Package(){0x0000FFFF, 2, INTB, 0 }, - Package(){0x0000FFFF, 3, INTC, 0 }, - }) - Name(APE3, Package(){ - /* PCIe slot - Hooked to PCIe Bridge 3*/ - Package(){0x0000FFFF, 0, 0, 19 }, - Package(){0x0000FFFF, 1, 0, 16 }, - Package(){0x0000FFFF, 2, 0, 17 }, - Package(){0x0000FFFF, 3, 0, 18 }, - }) - - /* SB PCI Bridge J21, J22 */ Name(PCIB, Package(){ - /* PCI slots: slot 0, slot 1, slot 2 behind Dev14, Fun4. */ - Package(){0x0005FFFF, 0, 0, 0x14 }, - Package(){0x0005FFFF, 1, 0, 0x15 }, - Package(){0x0005FFFF, 2, 0, 0x16 }, - Package(){0x0005FFFF, 3, 0, 0x17 }, - - Package(){0x0006FFFF, 0, 0, 0x15 }, - Package(){0x0006FFFF, 1, 0, 0x16 }, - Package(){0x0006FFFF, 2, 0, 0x17 }, - Package(){0x0006FFFF, 3, 0, 0x14 }, }) diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index bc1759a5c1..5d8eb4d3aa 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -124,43 +124,6 @@ static void *smp_write_config_table(void *v) PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]); PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]); - /* on board NIC & Slot PCIE. */ - - /* PCI slots */ - struct device *dev = pcidev_on_root(0x14, 4); - if (dev && dev->enabled) { - u8 bus_pci = dev->link_list->secondary; - /* PCI_SLOT 0. */ - PCI_INT(bus_pci, 0x5, 0x0, 0x14); - PCI_INT(bus_pci, 0x5, 0x1, 0x15); - PCI_INT(bus_pci, 0x5, 0x2, 0x16); - PCI_INT(bus_pci, 0x5, 0x3, 0x17); - - /* PCI_SLOT 1. */ - PCI_INT(bus_pci, 0x6, 0x0, 0x15); - PCI_INT(bus_pci, 0x6, 0x1, 0x16); - PCI_INT(bus_pci, 0x6, 0x2, 0x17); - PCI_INT(bus_pci, 0x6, 0x3, 0x14); - - /* PCI_SLOT 2. */ - PCI_INT(bus_pci, 0x7, 0x0, 0x16); - PCI_INT(bus_pci, 0x7, 0x1, 0x17); - PCI_INT(bus_pci, 0x7, 0x2, 0x14); - PCI_INT(bus_pci, 0x7, 0x3, 0x15); - } - - /* PCIe Lan*/ - PCI_INT(0x0, 0x06, 0x0, 0x13); - - /* FCH PCIe PortA */ - PCI_INT(0x0, 0x15, 0x0, 0x10); - /* FCH PCIe PortB */ - PCI_INT(0x0, 0x15, 0x1, 0x11); - /* FCH PCIe PortC */ - PCI_INT(0x0, 0x15, 0x2, 0x12); - /* FCH PCIe PortD */ - PCI_INT(0x0, 0x15, 0x3, 0x13); - /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */ IO_LOCAL_INT(mp_ExtINT, 0, MP_APIC_ALL, 0x0); IO_LOCAL_INT(mp_NMI, 0, MP_APIC_ALL, 0x1); From eee1f4387aa603eaa5b98f4437ff29f47296b8db Mon Sep 17 00:00:00 2001 From: Raymond Chung Date: Fri, 27 Nov 2020 12:53:38 +0800 Subject: [PATCH 43/45] mb/google/dedede: Create sasuke variant Create the sasuke variant of the waddledoo reference board by copying the template files to a new directory named for the variant. (Auto-Generated by create_coreboot_variant.sh version 4.3.1). BUG=b:172104731 BRANCH=None TEST=util/abuild/abuild -p none -t google/dedede -x -a make sure the build includes GOOGLE_SASUKE Signed-off-by: Raymond Chung Change-Id: I29405d63fd266224807e535c3f86a2ad5ab8cdf3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48112 Tested-by: build bot (Jenkins) Reviewed-by: Henry Sun Reviewed-by: SH Kim Reviewed-by: Paul Fagerburg --- src/mainboard/google/dedede/Kconfig | 2 + src/mainboard/google/dedede/Kconfig.name | 7 +++ .../variants/sasuke/include/variant/ec.h | 8 +++ .../variants/sasuke/include/variant/gpio.h | 8 +++ .../variants/sasuke/memory/Makefile.inc | 5 ++ .../sasuke/memory/dram_id.generated.txt | 1 + .../variants/sasuke/memory/mem_parts_used.txt | 6 ++ .../dedede/variants/sasuke/overridetree.cb | 58 +++++++++++++++++++ 8 files changed, 95 insertions(+) create mode 100644 src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h create mode 100644 src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h create mode 100644 src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc create mode 100644 src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt create mode 100644 src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt create mode 100644 src/mainboard/google/dedede/variants/sasuke/overridetree.cb diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 9f662a493c..86921a2cc1 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -97,6 +97,7 @@ config MAINBOARD_PART_NUMBER default "Metaknight" if BOARD_GOOGLE_METAKNIGHT default "Lantis" if BOARD_GOOGLE_LANTIS default "Galtic" if BOARD_GOOGLE_GALTIC + default "Sasuke" if BOARD_GOOGLE_SASUKE config MAX_CPUS int @@ -129,5 +130,6 @@ config VARIANT_DIR default "metaknight" if BOARD_GOOGLE_METAKNIGHT default "lantis" if BOARD_GOOGLE_LANTIS default "galtic" if BOARD_GOOGLE_GALTIC + default "sasuke" if BOARD_GOOGLE_SASUKE endif #BOARD_GOOGLE_BASEBOARD_DEDEDE diff --git a/src/mainboard/google/dedede/Kconfig.name b/src/mainboard/google/dedede/Kconfig.name index c8ce0030d8..cba8c9fb3b 100644 --- a/src/mainboard/google/dedede/Kconfig.name +++ b/src/mainboard/google/dedede/Kconfig.name @@ -83,3 +83,10 @@ config BOARD_GOOGLE_GALTIC bool "-> Galtic" select BOARD_GOOGLE_BASEBOARD_DEDEDE select BASEBOARD_DEDEDE_LAPTOP + +config BOARD_GOOGLE_SASUKE + bool "-> Sasuke" + select BOARD_GOOGLE_BASEBOARD_DEDEDE + select BASEBOARD_DEDEDE_LAPTOP + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 diff --git a/src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h b/src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h b/src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc b/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc new file mode 100644 index 0000000000..b0ca2223a8 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/memory/Makefile.inc @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later +## This is an auto-generated file. Do not edit!! +## Add memory parts in mem_parts_used.txt and run spd_tools to regenerate. + +SPD_SOURCES = placeholder.spd.hex diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt b/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt new file mode 100644 index 0000000000..fa247902ee --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/memory/dram_id.generated.txt @@ -0,0 +1 @@ +DRAM Part Name ID to assign diff --git a/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt new file mode 100644 index 0000000000..59381dcf5b --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/memory/mem_parts_used.txt @@ -0,0 +1,6 @@ +# This is a CSV file containing a list of memory parts used by this variant. +# Generate an updated Makefile.inc and dram_id.generated.txt by running the +# gen_part_id tool from util/spd_tools/lp4x +# See util/spd_tools/lp4x/README.md for more details and instructions. + +# Part Name diff --git a/src/mainboard/google/dedede/variants/sasuke/overridetree.cb b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb new file mode 100644 index 0000000000..69ea1e16f2 --- /dev/null +++ b/src/mainboard/google/dedede/variants/sasuke/overridetree.cb @@ -0,0 +1,58 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }, + }" + device domain 0 on + device pci 14.0 on end + device pci 15.0 on end + device pci 15.2 on end + device pci 1c.7 on end + device pci 19.0 on end + device pci 1f.3 on end + end +end From 2ac88f2347352c5dff0af18d5130dbdd6f032930 Mon Sep 17 00:00:00 2001 From: Meera Ravindranath Date: Thu, 26 Nov 2020 13:08:51 +0530 Subject: [PATCH 44/45] mb/google/dedede: Update Imon slope and Offset Value for Drawcia Updating Imon slope and offset values as per recommendation of ODM based on calibaration. Updating Imon slope to 1.0 and offset to 1.4 BUG=b:167294777 BRANCH=dedede TEST=Boot dedede platform and confirm values in FSP. Change-Id: I3eb32218040163f0abef9b8dd4c52efb16289fe7 Signed-off-by: Meera Ravindranath Reviewed-on: https://review.coreboot.org/c/coreboot/+/48072 Tested-by: build bot (Jenkins) Reviewed-by: Vinay Kumar Reviewed-by: Sumeet R Pawnikar --- src/mainboard/google/dedede/variants/drawcia/overridetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb index 45d0b32d62..dcb46cc650 100644 --- a/src/mainboard/google/dedede/variants/drawcia/overridetree.cb +++ b/src/mainboard/google/dedede/variants/drawcia/overridetree.cb @@ -63,6 +63,8 @@ chip soc/intel/jasperlake }" register "tcc_offset" = "20" # TCC of 85C + register "ImonOffset" = "1400" # Imon Offset = 1.4 + register "ImonSlope" = "100" # Imon Slope = 1.0 device domain 0 on device pci 05.0 on # IPU - MIPI Camera From 4b84a2c8a2db0998406abd5ed304814a5f2110a3 Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Fri, 27 Nov 2020 15:04:45 +0100 Subject: [PATCH 45/45] drivers/intel/fsp2_0: Remove console in weak function This pollutes the log on all platforms not implementing an override. Change-Id: I0d8371447ee7820cd8e86e9d3d5e70fcf4f91e34 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/48128 Reviewed-by: Frans Hendriks Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/intel/fsp2_0/util.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/drivers/intel/fsp2_0/util.c b/src/drivers/intel/fsp2_0/util.c index 490816d343..866db586e2 100644 --- a/src/drivers/intel/fsp2_0/util.c +++ b/src/drivers/intel/fsp2_0/util.c @@ -241,5 +241,4 @@ void lb_string_platform_blob_version(struct lb_header *header) __weak void soc_validate_fsp_version(const struct fsp_header *hdr) { - printk(BIOS_DEBUG, "%s not implemented.\n", __func__); }