From bfb21044f456bb2a143af92ec7eaec09a52f16db Mon Sep 17 00:00:00 2001
From: Tim Crawford <tcrawford@system76.com>
Date: Mon, 6 Feb 2023 10:47:17 -0700
Subject: [PATCH] mb/system76/adl: oryp10: Enable dGPU

I forgot this when performing the rebase.

Change-Id: I855968469ed339bdf2a5a40d5d91878a262ce954
Signed-off-by: Tim Crawford <tcrawford@system76.com>
---
 .../adl/variants/oryp10/include/variant/gpio.h      | 13 +++++++++++++
 .../system76/adl/variants/oryp10/overridetree.cb    |  2 +-
 .../system76/adl/variants/oryp10/romstage.c         | 10 ++++++++++
 3 files changed, 24 insertions(+), 1 deletion(-)
 create mode 100644 src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h

diff --git a/src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h b/src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h
new file mode 100644
index 0000000000..489487ba7b
--- /dev/null
+++ b/src/mainboard/system76/adl/variants/oryp10/include/variant/gpio.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef VARIANT_GPIO_H
+#define VARIANT_GPIO_H
+
+#include <soc/gpio.h>
+
+#define DGPU_RST_N	GPP_B2
+#define DGPU_PWR_EN	GPP_A14
+#define DGPU_GC6	GPP_A7
+#define DGPU_SSID	0x65f51558
+
+#endif
diff --git a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb
index dac2f53ba1..ddf5876f67 100644
--- a/src/mainboard/system76/adl/variants/oryp10/overridetree.cb
+++ b/src/mainboard/system76/adl/variants/oryp10/overridetree.cb
@@ -18,7 +18,7 @@ chip soc/intel/alderlake
 	device domain 0 on
 		subsystemid 0x1558 0x65f5 inherit
 
-		device ref pcie5_0 off
+		device ref pcie5_0 on
 			# CPU PCIe RP#2 x8, Clock 3 (DGPU)
 			register "cpu_pcie_rp[CPU_RP(2)]" = "{
 				.clk_src = 3,
diff --git a/src/mainboard/system76/adl/variants/oryp10/romstage.c b/src/mainboard/system76/adl/variants/oryp10/romstage.c
index 48714e0c85..082d0cbd10 100644
--- a/src/mainboard/system76/adl/variants/oryp10/romstage.c
+++ b/src/mainboard/system76/adl/variants/oryp10/romstage.c
@@ -1,7 +1,9 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
+#include <drivers/gfx/nvidia/gpu.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
+#include <variant/gpio.h>
 
 void mainboard_memory_init_params(FSPM_UPD *mupd)
 {
@@ -20,6 +22,14 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	};
 	const bool half_populated = false;
 
+	const struct nvidia_gpu_config config = {
+		.power_gpio = DGPU_PWR_EN,
+		.reset_gpio = DGPU_RST_N,
+		.enable = true,
+	};
+	// Enable dGPU power
+	nvidia_set_power(&config);
+
 	// Set primary display to internal graphics
 	mupd->FspmConfig.PrimaryDisplay = 0;