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intel/sandybridge post-car: Redo MTRR settings and stack selection

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Adapt implementation from haswell to prepare for removal of HIGH_MEMORY_SAVE
and moving on to RELOCATABLE_RAMSTAGE. With the change, CBMEM and SMM regions
are set to WRBACK with MTRRs and romstage ram stack is moved to CBMEM.

Also fixes regression of slower S3 resume path after commit
   9b99152 intel/sandybridge: Use common ACPI S3 recovery

Skipping low memory backup and using stage cache for ramstage decreases
time spent on S3 resume path by 50 ms on samsung/lumpy.

Change-Id: I2afee3662e73e8e629188258b2f4119e02d60305
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/15790
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Kyösti Mälkki
2016-07-22 22:48:35 +03:00
parent de01136484
commit bfca67078c
4 changed files with 112 additions and 34 deletions
Download Patch File Download Diff File Expand all files Collapse all files

54
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@@ -174,10 +174,9 @@ before_romstage:
post_code(0x29)
/* Call romstage.c main function. */
call romstage_main
/* Save return value from romstage_main. It contains the stack to use
* after cache-as-ram is torn down.
*/
* after cache-as-ram is torn down. It also contains the information
* for setting up MTRRs. */
movl %eax, %esp
post_code(0x30)
@@ -210,14 +209,6 @@ before_romstage:
andl $~1, %eax
wrmsr
/* Clear MTRR that was used to cache MRC */
xorl %eax, %eax
xorl %edx, %edx
movl $MTRR_PHYS_BASE(2), %ecx
wrmsr
movl $MTRR_PHYS_MASK(2), %ecx
wrmsr
post_code(0x33)
/* Enable cache. */
@@ -234,32 +225,31 @@ before_romstage:
post_code(0x38)
/* Enable Write Back and Speculative Reads for the first MB
* and ramstage.
*/
/* Get number of MTRRs. */
popl %ebx
movl $MTRR_PHYS_BASE(0), %ecx
movl $(0x00000000 | MTRR_TYPE_WRBACK), %eax
xorl %edx, %edx
wrmsr
movl $MTRR_PHYS_MASK(0), %ecx
movl $(~(CACHE_TMP_RAMTOP - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx // 36bit address space
wrmsr
1:
testl %ebx, %ebx
jz 1f
#if CACHE_ROM_SIZE
/* Enable Caching and speculative Reads for the
* complete ROM now that we actually have RAM.
*/
movl $MTRR_PHYS_BASE(1), %ecx
movl $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax
xorl %edx, %edx
/* Low 32 bits of MTRR base. */
popl %eax
/* Upper 32 bits of MTRR base. */
popl %edx
/* Write MTRR base. */
wrmsr
movl $MTRR_PHYS_MASK(1), %ecx
movl $(~(CACHE_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID), %eax
movl $CPU_PHYSMASK_HI, %edx
inc %ecx
/* Low 32 bits of MTRR mask. */
popl %eax
/* Upper 32 bits of MTRR mask. */
popl %edx
/* Write MTRR mask. */
wrmsr
#endif
inc %ecx
dec %ebx
jmp 1b
1:
post_code(0x39)
/* And enable cache again after setting MTRRs. */