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printk_foo -> printk(BIOS_FOO, ...)

Browse Source 
Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Ronald G. Minnich <rminnich@gmail.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5266 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-03-22 11:42:32 +00:00
committed by Stefan Reinauer
parent 27852aba67
commit c02b4fc9db
539 changed files with 3744 additions and 3759 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/cpu/amd/car/post_cache_as_ram.c
View File

@@ -5,7 +5,7 @@
static inline void print_debug_pcar(const char *strval, uint32_t val)
{
printk_debug("%s%08x\r\n", strval, val);
printk(BIOS_DEBUG, "%s%08x\r\n", strval, val);
}
/* from linux kernel 2.6.32 asm/string_32.h */

6
src/cpu/amd/dualcore/amd_sibling.c
View File

@@ -109,7 +109,7 @@ unsigned get_apicid_base(unsigned ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
printk_info("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n");
printk(BIOS_INFO, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in romstage.c so you can spare 16 id for ioapic\r\n");
enable_apic_ext_id(nodes);
}
@@ -140,7 +140,7 @@ void amd_sibling_init(device_t cpu)
}
#if 1
printk_debug("CPU: %u %d siblings\n",
printk(BIOS_DEBUG, "CPU: %u %d siblings\n",
cpu->path.apic.apic_id,
siblings);
#endif
@@ -191,7 +191,7 @@ void amd_sibling_init(device_t cpu)
new->path.apic.core_id = i;
#if 1
printk_debug("CPU: %u has sibling %u\n",
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#endif

10
src/cpu/amd/microcode/microcode.c
View File

@@ -61,8 +61,8 @@ static int need_apply_patch(struct microcode *m, u32 equivalent_processor_rev_id
{
if (m->processor_rev_id != equivalent_processor_rev_id) {
printk_err("microcode: rev id (%x) does not match this patch.\n", m->processor_rev_id);
printk_err("microcode: Not updated! Fix microcode_updates[] \n");
printk(BIOS_ERR, "microcode: rev id (%x) does not match this patch.\n", m->processor_rev_id);
printk(BIOS_ERR, "microcode: Not updated! Fix microcode_updates[] \n");
return 0;
}
if (m->nb_dev_id) {
@@ -93,7 +93,7 @@ void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_
msr = rdmsr(0x8b);
patch_id = msr.lo;
printk_debug("microcode: equivalent rev id = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id);
printk(BIOS_DEBUG, "microcode: equivalent rev id = 0x%04x, current patch id = 0x%08x\n", equivalent_processor_rev_id, patch_id);
m = microcode_updates;
@@ -107,13 +107,13 @@ void amd_update_microcode(void *microcode_updates, u32 equivalent_processor_rev_
wrmsr(0xc0010020, msr);
printk_debug("microcode: patch id to apply = 0x%08x\n", m->patch_id);
printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n", m->patch_id);
//read the patch_id again
msr = rdmsr(0x8b);
new_patch_id = msr.lo;
printk_debug("microcode: updated to patch id = 0x%08x %s\n", new_patch_id , (new_patch_id == m->patch_id)?" success\n":" fail\n" );
printk(BIOS_DEBUG, "microcode: updated to patch id = 0x%08x %s\n", new_patch_id , (new_patch_id == m->patch_id)?" success\n":" fail\n" );
break;
}
c += 2048;

24
src/cpu/amd/model_10xxx/fidvid.c
View File

@@ -28,21 +28,21 @@
static void print_debug_fv(const char *str, u32 val)
{
#if FAM10_SET_FIDVID_DEBUG == 1
printk_debug("%s%x\n", str, val);
printk(BIOS_DEBUG, "%s%x\n", str, val);
#endif
}
static void print_debug_fv_8(const char *str, u8 val)
{
#if FAM10_SET_FIDVID_DEBUG == 1
printk_debug("%s%02x\n", str, val);
printk(BIOS_DEBUG, "%s%02x\n", str, val);
#endif
}
static void print_debug_fv_64(const char *str, u32 val, u32 val2)
{
#if FAM10_SET_FIDVID_DEBUG == 1
printk_debug("%s%x%x\n", str, val, val2);
printk(BIOS_DEBUG, "%s%x%x\n", str, val, val2);
#endif
}
@@ -68,7 +68,7 @@ static void enable_fid_change(u8 fid)
dword |= (u32) fid & 0x1F;
dword |= 1 << 5; // enable
pci_write_config32(dev, 0xd4, dword);
printk_debug("FID Change Node:%02x, F3xD4: %08x \n", i, dword);
printk(BIOS_DEBUG, "FID Change Node:%02x, F3xD4: %08x \n", i, dword);
}
}
@@ -186,7 +186,7 @@ static void prep_fid_change(void)
nodes = get_nodes();
for(i = 0; i < nodes; i++) {
printk_debug("Prep FID/VID Node:%02x \n", i);
printk(BIOS_DEBUG, "Prep FID/VID Node:%02x \n", i);
dev = NODE_PCI(i,3);
dword = pci_read_config32(dev, 0xd8);
@@ -286,15 +286,15 @@ static void prep_fid_change(void)
pci_write_config32(dev, 0x80, dword);
dword = pci_read_config32(dev, 0x80);
printk_debug(" F3x80: %08x \n", dword);
printk(BIOS_DEBUG, " F3x80: %08x \n", dword);
dword = pci_read_config32(dev, 0x84);
printk_debug(" F3x84: %08x \n", dword);
printk(BIOS_DEBUG, " F3x84: %08x \n", dword);
dword = pci_read_config32(dev, 0xD4);
printk_debug(" F3xD4: %08x \n", dword);
printk(BIOS_DEBUG, " F3xD4: %08x \n", dword);
dword = pci_read_config32(dev, 0xD8);
printk_debug(" F3xD8: %08x \n", dword);
printk(BIOS_DEBUG, " F3xD8: %08x \n", dword);
dword = pci_read_config32(dev, 0xDC);
printk_debug(" F3xDC: %08x \n", dword);
printk(BIOS_DEBUG, " F3xDC: %08x \n", dword);
}
@@ -495,7 +495,7 @@ static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid)
u8 nodes;
u8 i;
printk_debug("FIDVID on AP: %02x\n", apicid);
printk(BIOS_DEBUG, "FIDVID on AP: %02x\n", apicid);
/* Steps 1-6 of BIOS NB COF and VID Configuration
* for SVI and Single-Plane PVI Systems.
@@ -773,7 +773,7 @@ static int init_fidvid_bsp(u32 bsp_apicid, u32 nodes)
u32 reg1fc;
u8 pvimode;
printk_debug("FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
printk(BIOS_DEBUG, "FIDVID on BSP, APIC_id: %02x\n", bsp_apicid);
/* FIXME: The first half of this function is nearly the same as
* init_fidvid_bsp() and the code could be combined.
*/

36
src/cpu/amd/model_10xxx/init_cpus.c
View File

@@ -32,24 +32,24 @@
static void print_initcpu8 (const char *strval, u8 val)
{
printk_debug("%s%02x\n", strval, val);
printk(BIOS_DEBUG, "%s%02x\n", strval, val);
}
static void print_initcpu8_nocr (const char *strval, u8 val)
{
printk_debug("%s%02x", strval, val);
printk(BIOS_DEBUG, "%s%02x", strval, val);
}
static void print_initcpu16 (const char *strval, u16 val)
{
printk_debug("%s%04x\n", strval, val);
printk(BIOS_DEBUG, "%s%04x\n", strval, val);
}
static void print_initcpu(const char *strval, u32 val)
{
printk_debug("%s%08x\n", strval, val);
printk(BIOS_DEBUG, "%s%08x\n", strval, val);
}
@@ -223,7 +223,7 @@ static void init_fidvid_ap(u32 bsp_apicid, u32 apicid, u32 nodeid, u32 coreid);
static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(u32 apicid, struct node_core_id id, const char *str)
{
printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\n", str, apicid, id.nodeid, id.coreid);
}
@@ -406,10 +406,10 @@ static u32 init_cpus(u32 cpu_init_detectedx)
{
// check warm(bios) reset to call stage2 otherwise do stage1
if (warm_reset_detect(id.nodeid)) {
printk_debug("init_fidvid_stage2 apicid: %02x\n", apicid);
printk(BIOS_DEBUG, "init_fidvid_stage2 apicid: %02x\n", apicid);
init_fidvid_stage2(apicid, id.nodeid);
} else {
printk_debug("init_fidvid_ap(stage1) apicid: %02x\n", apicid);
printk(BIOS_DEBUG, "init_fidvid_ap(stage1) apicid: %02x\n", apicid);
init_fidvid_ap(bsp_apicid, apicid, id.nodeid, id.coreid);
}
}
@@ -424,7 +424,7 @@ static u32 init_cpus(u32 cpu_init_detectedx)
set_var_mtrr(0, 0x00000000, CONFIG_RAMTOP, MTRR_TYPE_WRBACK);
STOP_CAR_AND_CPU();
printk_debug("\nAP %02x should be halted but you are reading this....\n", apicid);
printk(BIOS_DEBUG, "\nAP %02x should be halted but you are reading this....\n", apicid);
}
return bsp_apicid;
@@ -449,12 +449,12 @@ static void wait_all_core0_started(void)
u32 i;
u32 nodes = get_nodes();
printk_debug("Wait all core0s started \n");
printk(BIOS_DEBUG, "Wait all core0s started \n");
for(i=1;i<nodes;i++) { // skip bsp, because it is running on bsp
while(!is_core0_started(i)) {}
print_initcpu8(" Core0 started on node: ", i);
}
printk_debug("Wait all core0s started done\n");
printk(BIOS_DEBUG, "Wait all core0s started done\n");
}
#if CONFIG_MAX_PHYSICAL_CPUS > 1
/**
@@ -471,7 +471,7 @@ static void start_node(u8 node)
u32 val;
/* Enable routing table */
printk_debug("Start node %02x", node);
printk(BIOS_DEBUG, "Start node %02x", node);
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
/* For FAM10 support, we need to set Dram base/limit for the new node */
@@ -484,7 +484,7 @@ static void start_node(u8 node)
val &= ~(1 << 1);
pci_write_config32(NODE_HT(node), 0x6c, val);
printk_debug(" done.\n");
printk(BIOS_DEBUG, " done.\n");
}
@@ -514,7 +514,7 @@ static void setup_remote_node(u8 node)
};
u16 i;
printk_debug("setup_remote_node: %02x", node);
printk(BIOS_DEBUG, "setup_remote_node: %02x", node);
/* copy the default resource map from node 0 */
for(i = 0; i < ARRAY_SIZE(pci_reg); i++) {
@@ -525,7 +525,7 @@ static void setup_remote_node(u8 node)
pci_write_config32(NODE_MP(node), reg, value);
}
printk_debug(" done\n");
printk(BIOS_DEBUG, " done\n");
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
@@ -845,7 +845,7 @@ void cpuSetAMDMSR(void)
u8 i;
u32 revision, platform;
printk_debug("cpuSetAMDMSR ");
printk(BIOS_DEBUG, "cpuSetAMDMSR ");
revision = mctGetLogicalCPUID(0xFF);
platform = get_platform_type();
@@ -863,7 +863,7 @@ void cpuSetAMDMSR(void)
}
AMD_Errata298();
printk_debug(" done\n");
printk(BIOS_DEBUG, " done\n");
}
@@ -879,7 +879,7 @@ void cpuSetAMDPCI(u8 node)
u32 val;
u8 offset;
printk_debug("cpuSetAMDPCI %02d", node);
printk(BIOS_DEBUG, "cpuSetAMDPCI %02d", node);
revision = mctGetLogicalCPUID(node);
@@ -933,7 +933,7 @@ void cpuSetAMDPCI(u8 node)
if (revision & (AMD_DR_B2 | AMD_DR_B3))
dctPhyDiag(); */
printk_debug(" done\n");
printk(BIOS_DEBUG, " done\n");
}

4
src/cpu/amd/model_10xxx/model_10xxx_init.c
View File

@@ -77,7 +77,7 @@ void model_10xxx_init(device_t dev)
#endif
id = get_node_core_id(read_nb_cfg_54()); /* nb_cfg_54 can not be set */
printk_debug("nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
printk(BIOS_DEBUG, "nodeid = %02d, coreid = %02d\n", id.nodeid, id.coreid);
/* Turn on caching if we haven't already */
x86_enable_cache();
@@ -114,7 +114,7 @@ void model_10xxx_init(device_t dev)
msr.hi |= 1 << (33-32);
wrmsr_amd(CPU_ID_EXT_FEATURES_MSR, msr);
}
printk_debug("siblings = %02d, ", siblings);
printk(BIOS_DEBUG, "siblings = %02d, ", siblings);
#endif
/* DisableCf8ExtCfg */

2
src/cpu/amd/model_10xxx/processor_name.c
View File

@@ -226,7 +226,7 @@ done:
strcpymax(&program_string[j], processor_name_string,
sizeof(program_string) - j);
printk_debug("CPU model: %s\n", program_string);
printk(BIOS_DEBUG, "CPU model: %s\n", program_string);
for (i = 0; i < 6; i++) {
msr.lo = p_program_string[(2 * i) + 0];

2
src/cpu/amd/model_10xxx/update_microcode.c
View File

@@ -97,7 +97,7 @@ void update_microcode(u32 cpu_deviceid)
if (equivalent_processor_rev_id != 0) {
amd_update_microcode((void *) microcode_updates, equivalent_processor_rev_id);
} else {
printk_debug("microcode: rev id not found. Skipping microcode patch!\n");
printk(BIOS_DEBUG, "microcode: rev id not found. Skipping microcode patch!\n");
}
}

24
src/cpu/amd/model_fxx/fidvid.c
View File

@@ -15,21 +15,21 @@
static inline void print_debug_fv(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
printk_debug("%s%x\r\n", str, val);
printk(BIOS_DEBUG, "%s%x\r\n", str, val);
#endif
}
static inline void print_debug_fv_8(const char *str, unsigned val)
{
#if K8_SET_FIDVID_DEBUG == 1
printk_debug("%s%02x\r\n", str, val);
printk(BIOS_DEBUG, "%s%02x\r\n", str, val);
#endif
}
static inline void print_debug_fv_64(const char *str, unsigned val, unsigned val2)
{
#if K8_SET_FIDVID_DEBUG == 1
printk_debug("%s%x%x\r\n", str, val, val2);
printk(BIOS_DEBUG, "%s%x%x\r\n", str, val, val2);
#endif
}
@@ -131,7 +131,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
apicidx = lapicid();
if (apicid != apicidx) {
printk_err("wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx);
printk(BIOS_ERR, "wrong apicid, we want change %x, but it is %x\r\n", apicid, apicidx);
return fidvid;
}
@@ -201,8 +201,8 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
* transition to target fid
*/
printk_debug("Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, fid_max);
printk_debug("Requested fid_new: 0x%x\n", fid_new);
printk(BIOS_DEBUG, "Current fid_cur: 0x%x, fid_max: 0x%x\n", fid_cur, fid_max);
printk(BIOS_DEBUG, "Requested fid_new: 0x%x\n", fid_new);
step_limit = 8; /* max 8 steps just in case... */
while ((fid_cur != fid_new) && (step_limit--)) {
@@ -218,7 +218,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
/* If 200Mhz step OR past 3200 max table value */
if ((step == 2) || (fid_new >= 0x18 || fid_cur >= 0x18)) {
printk_debug("200MHZ step ");
printk(BIOS_DEBUG, "200MHZ step ");
/* Step +/- 200MHz at a time */
if (fid_cur < fid_new)
@@ -231,7 +231,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
int temp;
/* look it up in the table */
printk_debug("FidVid table step ");
printk(BIOS_DEBUG, "FidVid table step ");
temp = next_fid_200[((fid_new/2) * 13) + (fid_cur/2)];
@@ -243,7 +243,7 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
break; /* table error */
} else { /* step < 2 (100MHZ) */
printk_debug("100MHZ step ");
printk(BIOS_DEBUG, "100MHZ step ");
/* The table adjust in 200MHz increments. If requested,
* do the 100MHz increment if the CPU supports it.*/
@@ -251,17 +251,17 @@ static u32 set_fidvid(unsigned apicid, unsigned fidvid, int showmessage)
fid_temp = fid_cur + 1;
} else {
/* 100 MHZ not supported. Get out of the loop */
printk_debug("is not supported.\n");
printk(BIOS_DEBUG, "is not supported.\n");
break;
}
}
if(fid_temp > fid_max) {
printk_debug("fid_temp 0x%x > fid_max 0x%x\n", fid_temp, fid_max);
printk(BIOS_DEBUG, "fid_temp 0x%x > fid_max 0x%x\n", fid_temp, fid_max);
break;
}
printk_debug("fidvid: 0x%x\n", fid_temp);
printk(BIOS_DEBUG, "fidvid: 0x%x\n", fid_temp);
/* set target fid */
msr.hi = 0x190; /* 2 us for AMD NPT Family 0Fh Processors */

10
src/cpu/amd/model_fxx/init_cpus.c
View File

@@ -16,23 +16,23 @@
static inline void print_initcpu8 (const char *strval, unsigned val)
{
printk_debug("%s%02x\r\n", strval, val);
printk(BIOS_DEBUG, "%s%02x\r\n", strval, val);
}
static inline void print_initcpu8_nocr (const char *strval, unsigned val)
{
printk_debug("%s%02x", strval, val);
printk(BIOS_DEBUG, "%s%02x", strval, val);
}
static inline void print_initcpu16 (const char *strval, unsigned val)
{
printk_debug("%s%04x\r\n", strval, val);
printk(BIOS_DEBUG, "%s%04x\r\n", strval, val);
}
static inline void print_initcpu(const char *strval, unsigned val)
{
printk_debug("%s%08x\r\n", strval, val);
printk(BIOS_DEBUG, "%s%08x\r\n", strval, val);
}
typedef void (*process_ap_t)(unsigned apicid, void *gp);
@@ -155,7 +155,7 @@ static void init_fidvid_ap(unsigned bsp_apicid, unsigned apicid);
static inline __attribute__((always_inline)) void print_apicid_nodeid_coreid(unsigned apicid, struct node_core_id id, const char *str)
{
printk_debug("%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
printk(BIOS_DEBUG, "%s --- { APICID = %02x NODEID = %02x COREID = %02x} ---\r\n", str, apicid, id.nodeid, id.coreid);
}

20
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@@ -150,16 +150,16 @@ static void print_mtrr_state(struct mtrr_state *state)
{
int i;
for(i = 0; i < MTRR_COUNT; i++) {
printk_debug("var mtrr %d: %08x%08x mask: %08x%08x\n",
printk(BIOS_DEBUG, "var mtrr %d: %08x%08x mask: %08x%08x\n",
i,
state->mtrrs[i].base.hi, state->mtrrs[i].base.lo,
state->mtrrs[i].mask.hi, state->mtrrs[i].mask.lo);
}
printk_debug("top_mem: %08x%08x\n",
printk(BIOS_DEBUG, "top_mem: %08x%08x\n",
state->top_mem.hi, state->top_mem.lo);
printk_debug("top_mem2: %08x%08x\n",
printk(BIOS_DEBUG, "top_mem2: %08x%08x\n",
state->top_mem2.hi, state->top_mem2.lo);
printk_debug("def_type: %08x%08x\n",
printk(BIOS_DEBUG, "def_type: %08x%08x\n",
state->def_type.hi, state->def_type.lo);
}
#endif
@@ -214,7 +214,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
enable_lapic();
/* Print a status message */
printk_debug("%c", (basek >= TOLM_KB)?'+':'-');
printk(BIOS_DEBUG, "%c", (basek >= TOLM_KB)?'+':'-');
/* Return to the initialization state */
set_init_ecc_mtrrs();
@@ -232,7 +232,7 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
size = (limitk - basek) << 10;
addr = map_2M_page(basek >> 11);
if (addr == MAPPING_ERROR) {
printk_err("Cannot map page: %lx\n", basek >> 11);
printk(BIOS_ERR, "Cannot map page: %lx\n", basek >> 11);
return;
}
@@ -276,14 +276,14 @@ static void init_ecc_memory(unsigned node_id)
} else {
pci_write_config32(f3_dev, SCRUB_CONTROL,
(SCRUB_NONE << 16) | (SCRUB_NONE << 8) | (SCRUB_NONE << 0));
printk_debug("Scrubbing Disabled\n");
printk(BIOS_DEBUG, "Scrubbing Disabled\n");
}
/* If ecc support is not enabled don't touch memory */
dcl = pci_read_config32(f2_dev, DRAM_CONFIG_LOW);
if (!(dcl & DCL_DimmEccEn)) {
printk_debug("ECC Disabled\n");
printk(BIOS_DEBUG, "ECC Disabled\n");
return;
}
@@ -313,7 +313,7 @@ static void init_ecc_memory(unsigned node_id)
begink = (CONFIG_RAMTOP >>10);
}
printk_debug("Clearing memory %luK - %luK: ", begink, endk);
printk(BIOS_DEBUG, "Clearing memory %luK - %luK: ", begink, endk);
/* Save the normal state */
save_mtrr_state(&mtrr_state);
@@ -362,7 +362,7 @@ static void init_ecc_memory(unsigned node_id)
(SCRUB_84ms << 16) | (SCRUB_84ms << 8) | (SCRUB_84ms << 0));
}
printk_debug(" done\n");
printk(BIOS_DEBUG, " done\n");
}

16
src/cpu/amd/model_fxx/powernow_acpi.c
View File

@@ -156,14 +156,14 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
v[10] = cpuid1.ecx;
v[11] = cpuid1.edx;
processor_brand[48] = 0;
printk_info("processor_brand=%s\n", processor_brand);
printk(BIOS_INFO, "processor_brand=%s\n", processor_brand);
/*
* Based on the CPU socket type,cmp_cap and pwr_lmt , get the power limit.
* socket_type : 0x10 SocketF; 0x11 AM2/ASB1 ; 0x12 S1G1
* cmp_cap : 0x0 SingleCore ; 0x1 DualCore
*/
printk_info("Pstates Algorithm ...\n");
printk(BIOS_INFO, "Pstates Algorithm ...\n");
cmp_cap =
(pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x18, 3)), 0xE8) &
0x3000) >> 12;
@@ -181,7 +181,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
/* See if the CPUID(0x80000007) returned EDX[2:1]==11b */
cpuid1 = cpuid(0x80000007);
if ((cpuid1.edx & 0x6) != 0x6) {
printk_info("No valid set of P-states\n");
printk(BIOS_INFO, "No valid set of P-states\n");
goto write_pstates;
}
@@ -204,7 +204,7 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
PstateStep_coef = 2;
if (IntPstateSup == 0) {
printk_info("No intermediate P-states are supported\n");
printk(BIOS_INFO, "No intermediate P-states are supported\n");
goto write_pstates;
}
@@ -352,12 +352,12 @@ static int pstates_algorithm(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
/* Print Pstate freq,vid,volt,power */
for (index = 0; index < Pstate_num; index++) {
printk_info("Pstate_freq[%d] = %dMHz\t", index,
printk(BIOS_INFO, "Pstate_freq[%d] = %dMHz\t", index,
Pstate_feq[index]);
printk_info("Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
printk_info("Pstate_volt[%d] = %dmv\t", index,
printk(BIOS_INFO, "Pstate_vid[%d] = %d\t", index, Pstate_vid[index]);
printk(BIOS_INFO, "Pstate_volt[%d] = %dmv\t", index,
Pstate_volt[index]);
printk_info("Pstate_power[%d] = %dmw\n", index,
printk(BIOS_INFO, "Pstate_power[%d] = %dmw\n", index,
Pstate_power[index]);
}

2
src/cpu/amd/model_fxx/processor_name.c
View File

@@ -443,7 +443,7 @@ int init_processor_name(void)
}
}
printk_debug("CPU model %s\n", program_string);
printk(BIOS_DEBUG, "CPU model %s\n", program_string);
for (i=0; i<6; i++) {
progmsr.lo = program_values[(2*i)+0];

10
src/cpu/amd/model_gx2/cpubug.c
View File

@@ -169,7 +169,7 @@ eng2900(void)
{
msr_t msr;
printk_debug("CPU_BUG:%s\n", __func__);
printk(BIOS_DEBUG, "CPU_BUG:%s\n", __func__);
/* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
msr = rdmsr(0x3003);
msr.hi &= 0xFFFFF7FF;
@@ -356,10 +356,10 @@ cpubug(void)
rev = msr.lo & 0xff;
if (rev < 0x20) {
printk_err("%s: rev < 0x20! bailing!\n");
printk(BIOS_ERR, "%s: rev < 0x20! bailing!\n");
return;
}
printk_debug("Doing cpubug fixes for rev 0x%x\n", rev);
printk(BIOS_DEBUG, "Doing cpubug fixes for rev 0x%x\n", rev);
switch(rev)
{
case 0x20:
@@ -379,11 +379,11 @@ cpubug(void)
case 0x30:
break;
default:
printk_err("unknown rev %x, bailing\n", rev);
printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);
return;
}
bug784();
bug118253();
disablememoryreadorder();
printk_debug("Done cpubug fixes \n");
printk(BIOS_DEBUG, "Done cpubug fixes \n");
}

4
src/cpu/amd/model_gx2/model_gx2_init.c
View File

@@ -19,7 +19,7 @@ static void vsm_end_post_smi(void)
static void model_gx2_init(device_t dev)
{
printk_debug("model_gx2_init\n");
printk(BIOS_DEBUG, "model_gx2_init\n");
/* Turn on caching if we haven't already */
x86_enable_cache();
@@ -29,7 +29,7 @@ static void model_gx2_init(device_t dev)
vsm_end_post_smi();
printk_debug("model_gx2_init DONE\n");
printk(BIOS_DEBUG, "model_gx2_init DONE\n");
};
static struct device_operations cpu_dev_ops = {

10
src/cpu/amd/model_gx2/vsmsetup.c
View File

@@ -187,16 +187,16 @@ void do_vsmbios(void)
unsigned char *buf;
int i;
printk_err( "do_vsmbios\n");
printk(BIOS_ERR, "do_vsmbios\n");
/* Clear VSM BIOS data area. */
for (i = 0x400; i < 0x500; i++)
*(volatile unsigned char *)i = 0;
if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) {
printk_err("do_vsmbios: Failed to load VSA.\n");
printk(BIOS_ERR, "do_vsmbios: Failed to load VSA.\n");
}
buf = VSA2_BUFFER;
printk_debug("buf[0x20] signature is %x:%x:%x:%x\n",
printk(BIOS_DEBUG, "buf[0x20] signature is %x:%x:%x:%x\n",
buf[0x20], buf[0x21], buf[0x22], buf[0x23]);
/* Check for POST code at start of vsainit.bin. If you don't see it,
* don't bother.
@@ -207,7 +207,7 @@ void do_vsmbios(void)
}
/* ecx gets smm, edx gets sysm. */
printk_err("Call real_mode_switch_call_vsm\n");
printk(BIOS_ERR, "Call real_mode_switch_call_vsm\n");
// real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
/* Restart Timer 1. */
@@ -216,7 +216,7 @@ void do_vsmbios(void)
/* Check that VSA is running OK. */
if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
printk_debug("do_vsmbios: VSA2 VR signature verified\n");
printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n");
else
die("FATAL: VSA2 VR signature not valid, install failed!\n");
}

2
src/cpu/amd/model_lx/cpubug.c
View File

@@ -87,5 +87,5 @@ void cpubug(void)
{
pcideadlock();
disablememoryreadorder();
printk_debug("Done cpubug fixes \n");
printk(BIOS_DEBUG, "Done cpubug fixes \n");
}

8
src/cpu/amd/model_lx/model_lx_init.c
View File

@@ -40,7 +40,7 @@ static void vsm_end_post_smi(void)
static void model_lx_init(device_t dev)
{
printk_debug("model_lx_init\n");
printk(BIOS_DEBUG, "model_lx_init\n");
/* Turn on caching if we haven't already */
x86_enable_cache();
@@ -52,11 +52,11 @@ static void model_lx_init(device_t dev)
vsm_end_post_smi();
// Set gate A20 (legacy vsm disables it in late init)
printk_debug("A20 (0x92): %d\n", inb(0x92));
printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
outb(0x02, 0x92);
printk_debug("A20 (0x92): %d\n", inb(0x92));
printk(BIOS_DEBUG, "A20 (0x92): %d\n", inb(0x92));
printk_debug("CPU model_lx_init DONE\n");
printk(BIOS_DEBUG, "CPU model_lx_init DONE\n");
};
static struct device_operations cpu_dev_ops = {

51
src/cpu/amd/model_lx/vsmsetup.c
View File

@@ -274,7 +274,7 @@ void do_vsmbios(void)
unsigned int size = SMM_SIZE * 1024;
int i;
printk_err("do_vsmbios\n");
printk(BIOS_ERR, "do_vsmbios\n");
/* clear vsm bios data area */
for (i = 0x400; i < 0x500; i++) {
*(volatile unsigned char *)i = 0;
@@ -288,23 +288,23 @@ void do_vsmbios(void)
*/
if ((unsigned int)cbfs_load_stage("vsa") != VSA2_ENTRY_POINT) {
printk_err("do_vsmbios: Failed to load VSA.\n");
printk(BIOS_ERR, "do_vsmbios: Failed to load VSA.\n");
}
buf = (unsigned char *)VSA2_BUFFER;
printk_debug("buf %p *buf %d buf[256k] %d\n",
printk(BIOS_DEBUG, "buf %p *buf %d buf[256k] %d\n",
buf, buf[0], buf[SMM_SIZE * 1024]);
printk_debug("buf[0x20] signature is %x:%x:%x:%x\n",
printk(BIOS_DEBUG, "buf[0x20] signature is %x:%x:%x:%x\n",
buf[0x20], buf[0x21], buf[0x22], buf[0x23]);
/* check for post code at start of vsainit.bin. If you don't see it,
don't bother. */
if ((buf[0x20] != 0xb0) || (buf[0x21] != 0x10) ||
(buf[0x22] != 0xe6) || (buf[0x23] != 0x80)) {
printk_err("do_vsmbios: no vsainit.bin signature, skipping!\n");
printk(BIOS_ERR, "do_vsmbios: no vsainit.bin signature, skipping!\n");
return;
}
/* ecx gets smm, edx gets sysm */
printk_err("Call real_mode_switch_call_vsm\n");
printk(BIOS_ERR, "Call real_mode_switch_call_vsm\n");
real_mode_switch_call_vsm(MSR_GLIU0_SMM, MSR_GLIU0_SYSMEM);
/* restart timer 1 */
@@ -313,10 +313,9 @@ void do_vsmbios(void)
// check that VSA is running OK
if (VSA_vrRead(SIGNATURE) == VSA2_SIGNATURE)
printk_debug("do_vsmbios: VSA2 VR signature verified\n");
printk(BIOS_DEBUG, "do_vsmbios: VSA2 VR signature verified\n");
else
printk_err
("do_vsmbios: VSA2 VR signature not valid, install failed!\n");
printk(BIOS_ERR, "do_vsmbios: VSA2 VR signature not valid, install failed!\n");
}
// we had hoped to avoid this.
@@ -495,30 +494,30 @@ int biosint(unsigned long intnumber,
cs = cs_ip >> 16;
flags = stackflags;
printk_debug("biosint: INT# 0x%lx\n", intnumber);
printk_debug("biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
printk(BIOS_DEBUG, "biosint: INT# 0x%lx\n", intnumber);
printk(BIOS_DEBUG, "biosint: eax 0x%lx ebx 0x%lx ecx 0x%lx edx 0x%lx\n",
eax, ebx, ecx, edx);
printk_debug("biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
printk(BIOS_DEBUG, "biosint: ebp 0x%lx esp 0x%lx edi 0x%lx esi 0x%lx\n",
ebp, esp, edi, esi);
printk_debug("biosint: ip 0x%x cs 0x%x flags 0x%x\n",
printk(BIOS_DEBUG, "biosint: ip 0x%x cs 0x%x flags 0x%x\n",
(u32)ip, (u32)cs, (u32)flags);
printk_debug("biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n",
printk(BIOS_DEBUG, "biosint: gs 0x%x fs 0x%x ds 0x%x es 0x%x\n",
(u16)(gsfs >> 16), (u16)(gsfs & 0xffff), (u16)(dses >> 16), (u16)(dses & 0xffff));
// cases in a good compiler are just as good as your own tables.
switch (intnumber) {
case 0 ... 15:
// These are not BIOS service, but the CPU-generated exceptions
printk_info("biosint: Oops, exception 0x%x\n", (u32)intnumber);
printk(BIOS_INFO, "biosint: Oops, exception 0x%x\n", (u32)intnumber);
if (esp < 0x1000) {
printk_debug("Stack contents: ");
printk(BIOS_DEBUG, "Stack contents: ");
while (esp < 0x1000) {
printk_debug("0x%04x ", *(unsigned short *)esp);
printk(BIOS_DEBUG, "0x%04x ", *(unsigned short *)esp);
esp += 2;
}
printk_debug("\n");
printk(BIOS_DEBUG, "\n");
}
printk_debug("biosint: Bailing out ... not now\n");
printk(BIOS_DEBUG, "biosint: Bailing out ... not now\n");
// "longjmp"
//vga_exit();
break;
@@ -537,7 +536,7 @@ int biosint(unsigned long intnumber,
&ebx, &edx, &ecx, &eax, &flags);
break;
default:
printk_info("BIOSINT: Unsupported int #0x%x\n", (u32)intnumber);
printk(BIOS_INFO, "BIOSINT: Unsupported int #0x%x\n", (u32)intnumber);
break;
}
if (ret)
@@ -648,7 +647,7 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
// devfn is an int, so we mask it off.
busdevfn = (dev->bus->secondary << 8)
| (dev->path.pci.devfn & 0xff);
printk_debug("0x%x: return 0x%x\n", func,
printk(BIOS_DEBUG, "0x%x: return 0x%x\n", func,
busdevfn);
*pebx = busdevfn;
retval = 0;
@@ -675,8 +674,7 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
reg = *pedi;
dev = dev_find_slot(bus, devfn);
if (!dev) {
printk_debug
("0x%x: BAD DEVICE bus %d devfn 0x%x\n",
printk(BIOS_DEBUG, "0x%x: BAD DEVICE bus %d devfn 0x%x\n",
func, bus, devfn);
// idiots. the pcibios guys assumed you'd never pass a bad bus/devfn!
*peax = PCIBIOS_BADREG;
@@ -711,15 +709,14 @@ pcibios(unsigned long *pedi, unsigned long *pesi, unsigned long *pebp,
if (retval)
retval = PCIBIOS_BADREG;
printk_debug
("0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
printk(BIOS_DEBUG, "0x%x: bus %d devfn 0x%x reg 0x%x val 0x%lx\n",
func, bus, devfn, reg, *pecx);
*peax = 0;
retval = 0;
}
break;
default:
printk_err("UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
printk(BIOS_ERR, "UNSUPPORTED PCIBIOS FUNCTION 0x%x\n", func);
break;
}
@@ -731,7 +728,7 @@ int handleint21(unsigned long *edi, unsigned long *esi, unsigned long *ebp,
unsigned long *ecx, unsigned long *eax, unsigned long *flags)
{
int res = -1;
printk_debug("handleint21, eax 0x%x\n", (u32)*eax);
printk(BIOS_DEBUG, "handleint21, eax 0x%x\n", (u32)*eax);
switch (*eax & 0xffff) {
case 0x5f19:
break;

8
src/cpu/amd/mtrr/amd_mtrr.c
View File

@@ -95,7 +95,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
if (start_mtrr >= NUM_FIXED_RANGES) {
return;
}
printk_debug("Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB, RdMEM, WrMEM\n",
start_mtrr, last_mtrr);
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK | MTRR_READ_MEM | MTRR_WRITE_MEM);
@@ -116,9 +116,9 @@ void amd_setup_mtrrs(void)
wrmsr(SYSCFG_MSR, msr);
enable_cache();
printk_debug("\n");
printk(BIOS_DEBUG, "\n");
/* Initialized the fixed_mtrrs to uncached */
printk_debug("Setting fixed MTRRs(%d-%d) type: UC\n",
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) type: UC\n",
0, NUM_FIXED_RANGES);
set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
@@ -130,7 +130,7 @@ void amd_setup_mtrrs(void)
search_global_resources(
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_fixed_mtrr_resource, &state);
printk_debug("DONE fixed MTRRs\n");
printk(BIOS_DEBUG, "DONE fixed MTRRs\n");
if (state.mmio_basek > state.tomk) {
state.mmio_basek = state.tomk;

2
src/cpu/amd/quadcore/amd_sibling.c
View File

@@ -114,7 +114,7 @@ u32 get_apicid_base(u32 ioapic_num)
if((apicid_base+ioapic_num-1)>0xf) {
// We need to enable APIC EXT ID
printk_spew("if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
printk(BIOS_SPEW, "if the IO APIC device doesn't support 256 apic id, \r\n you need to set CONFIG_ENABLE_APIC_EXT_ID in MB Option.lb so you can spare 16 id for ioapic\r\n");
enable_apic_ext_id(sysconf.nodes);
}

6
src/cpu/amd/quadcore/quadcore.c
View File

@@ -59,7 +59,7 @@ static void real_start_other_core(u32 nodeid, u32 cores)
{
u32 dword, i;
printk_debug("Start other core - nodeid: %02x cores: %02x\n", nodeid, cores);
printk(BIOS_DEBUG, "Start other core - nodeid: %02x cores: %02x\n", nodeid, cores);
/* set PCI_DEV(0, 0x18+nodeid, 3), 0x44 bit 27 to redirect all MC4
accesses and error logging to core0 */
@@ -88,7 +88,7 @@ static void start_other_cores(void)
// disable quad_core
if (read_option(CMOS_VSTART_quad_core, CMOS_VLEN_quad_core, 0) != 0) {
printk_debug("Skip additional core init\n");
printk(BIOS_DEBUG, "Skip additional core init\n");
return;
}
@@ -96,7 +96,7 @@ static void start_other_cores(void)
for (nodeid = 0; nodeid < nodes; nodeid++) {
u32 cores = get_core_num_in_bsp(nodeid);
printk_debug("init node: %02x cores: %02x \n", nodeid, cores);
printk(BIOS_DEBUG, "init node: %02x cores: %02x \n", nodeid, cores);
if (cores > 0) {
real_start_other_core(nodeid, cores);
}

40
src/cpu/amd/sc520/sc520.c
View File

@@ -36,9 +36,9 @@ static void cpu_init(device_t dev)
unsigned long *l = (unsigned long *) 0xfffef088;
int i;
for(i = 0; i < 16; i++, l++)
printk_err("Par%d: 0x%lx\n", i, *l);
printk(BIOS_ERR, "Par%d: 0x%lx\n", i, *l);
printk_spew("SC520 random fixup ...\n");
printk(BIOS_SPEW, "SC520 random fixup ...\n");
}
@@ -49,14 +49,14 @@ static void cpu_init(device_t dev)
void sc520_enable_resources(struct device *dev) {
unsigned char command;
printk_spew("%s\n", __func__);
printk(BIOS_SPEW, "%s\n", __func__);
command = pci_read_config8(dev, PCI_COMMAND);
printk_spew("========>%s, command 0x%x\n", __func__, command);
printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
command |= PCI_COMMAND_MEMORY | PCI_COMMAND_PARITY | PCI_COMMAND_SERR;
printk_spew("========>%s, command 0x%x\n", __func__, command);
printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
pci_write_config8(dev, PCI_COMMAND, command);
command = pci_read_config8(dev, PCI_COMMAND);
printk_spew("========>%s, command 0x%x\n", __func__, command);
printk(BIOS_SPEW, "========>%s, command 0x%x\n", __func__, command);
/*
*/
@@ -100,7 +100,7 @@ static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
struct resource *resource;
printk_spew("%s sizek 0x%x\n", __func__, sizek);
printk(BIOS_SPEW, "%s sizek 0x%x\n", __func__, sizek);
if (!sizek) {
return;
}
@@ -126,14 +126,14 @@ static uint32_t find_pci_tolm(struct bus *bus)
{
struct resource *min;
uint32_t tolm;
printk_spew("%s\n", __func__);
printk(BIOS_SPEW, "%s\n", __func__);
min = 0;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
}
printk_spew("%s returns 0x%x\n", __func__, tolm);
printk(BIOS_SPEW, "%s returns 0x%x\n", __func__, tolm);
return tolm;
}
@@ -141,7 +141,7 @@ static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
uint32_t pci_tolm;
printk_spew("%s\n", __func__);
printk(BIOS_SPEW, "%s\n", __func__);
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
@@ -162,10 +162,10 @@ static void pci_domain_set_resources(device_t dev)
if (reg > rambits)
rambits = reg;
if (reg < rambits)
printk_err("ERROR! register 0x%x is not set!\n",
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
tomk = rambits*8*1024;
#endif
tomk = 32 * 1024;
@@ -186,20 +186,20 @@ static void pci_domain_set_resources(device_t dev)
#if 0
void sc520_enable_resources(device_t dev) {
printk_spew("%s\n", __func__);
printk_spew("THIS IS FOR THE SC520 =============================\n");
printk(BIOS_SPEW, "%s\n", __func__);
printk(BIOS_SPEW, "THIS IS FOR THE SC520 =============================\n");
/*
command = pci_read_config8(dev, PCI_COMMAND);
printk_spew("%s, command 0x%x\n", __func__, command);
printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
command |= PCI_COMMAND_MEMORY;
printk_spew("%s, command 0x%x\n", __func__, command);
printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
pci_write_config8(dev, PCI_COMMAND, command);
command = pci_read_config8(dev, PCI_COMMAND);
printk_spew("%s, command 0x%x\n", __func__, command);
printk(BIOS_SPEW, "%s, command 0x%x\n", __func__, command);
*/
enable_childrens_resources(dev);
printk_spew("%s\n", __func__);
printk(BIOS_SPEW, "%s\n", __func__);
}
#endif
@@ -220,7 +220,7 @@ static struct device_operations pci_domain_ops = {
#if 0
static void cpu_bus_init(device_t dev)
{
printk_spew("cpu_bus_init\n");
printk(BIOS_SPEW, "cpu_bus_init\n");
}
static void cpu_bus_noop(device_t dev)
@@ -238,7 +238,7 @@ static struct device_operations cpu_bus_ops = {
static void enable_dev(struct device *dev)
{
printk_spew("%s\n", __func__);
printk(BIOS_SPEW, "%s\n", __func__);
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;

6
src/cpu/emulation/qemu-x86/northbridge.c
View File

@@ -81,14 +81,14 @@ static void cpu_pci_domain_set_resources(device_t dev)
if (reg > rambits)
rambits = reg;
if (reg < rambits)
printk_err("ERROR! register 0x%x is not set!\n",
printk(BIOS_ERR, "ERROR! register 0x%x is not set!\n",
ramregs[i]);
}
if (rambits == 0) {
printk_err("RAM size config registers are empty; defaulting to 64 MBytes\n");
printk(BIOS_ERR, "RAM size config registers are empty; defaulting to 64 MBytes\n");
rambits = 8;
}
printk_debug("I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
printk(BIOS_DEBUG, "I would set ram size to 0x%x Kbytes\n", (rambits)*8*1024);
tomk = rambits*8*1024;
/* Compute the top of Low memory */
tolmk = pci_tolm >> 10;

6
src/cpu/intel/hyperthreading/intel_sibling.c
View File

@@ -31,7 +31,7 @@ void intel_sibling_init(device_t cpu)
}
#if 1
printk_debug("CPU: %u %d siblings\n",
printk(BIOS_DEBUG, "CPU: %u %d siblings\n",
cpu->path.apic.apic_id,
siblings);
#endif
@@ -61,14 +61,14 @@ void intel_sibling_init(device_t cpu)
}
#if 1
printk_debug("CPU: %u has sibling %u\n",
printk(BIOS_DEBUG, "CPU: %u has sibling %u\n",
cpu->path.apic.apic_id,
new->path.apic.apic_id);
#endif
/* Start the new cpu */
if (!start_cpu(new)) {
/* Record the error in cpu? */
printk_err("CPU %u would not start!\n",
printk(BIOS_ERR, "CPU %u would not start!\n",
new->path.apic.apic_id);
}
}

2
src/cpu/intel/model_1067x/model_1067x_init.c
View File

@@ -210,7 +210,7 @@ static void model_1067x_init(device_t cpu)
/* Print processor name */
fill_processor_name(processor_name);
printk_info("CPU: %s.\n", processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?

4
src/cpu/intel/model_106cx/cache_as_ram_disable.c
View File

@@ -36,12 +36,12 @@ void stage1_main(unsigned long bist)
"movl %%esp, %0\n\t"
: "=a" (v_esp)
);
printk_spew("v_esp=%08x\r\n", v_esp);
printk(BIOS_SPEW, "v_esp=%08x\r\n", v_esp);
}
cpu_reset_x:
printk_spew("cpu_reset = %08x\r\n",cpu_reset);
printk(BIOS_SPEW, "cpu_reset = %08x\r\n",cpu_reset);
if(cpu_reset == 0) {
print_spew("Clearing initial memory region: ");

2
src/cpu/intel/model_106cx/model_106cx_init.c
View File

@@ -171,7 +171,7 @@ static void model_106cx_init(device_t cpu)
/* Print processor name */
fill_processor_name(processor_name);
printk_info("CPU: %s.\n", processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?

8
src/cpu/intel/model_6ex/cache_as_ram_disable.c
View File

@@ -37,13 +37,13 @@ void stage1_main(unsigned long bist)
"movl %%esp, %0\n"
: "=a" (v_esp)
);
printk_spew("v_esp=%08x\n", v_esp);
printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
#endif
cpu_reset_x:
printk_spew("cpu_reset = %08x\n", cpu_reset);
printk_spew("No cache as ram now - ");
printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
printk(BIOS_SPEW, "No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
@@ -83,5 +83,5 @@ cpu_reset_x:
}
/* We will not return */
printk_debug("sorry. parachute did not open.\n");
printk(BIOS_DEBUG, "sorry. parachute did not open.\n");
}

2
src/cpu/intel/model_6ex/model_6ex_init.c
View File

@@ -200,7 +200,7 @@ static void model_6ex_init(device_t cpu)
/* Print processor name */
fill_processor_name(processor_name);
printk_info("CPU: %s.\n", processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?

8
src/cpu/intel/model_6fx/cache_as_ram_disable.c
View File

@@ -38,13 +38,13 @@ void stage1_main(unsigned long bist)
"movl %%esp, %0\n"
: "=a" (v_esp)
);
printk_spew("v_esp=%08x\n", v_esp);
printk(BIOS_SPEW, "v_esp=%08x\n", v_esp);
#endif
cpu_reset_x:
printk_spew("cpu_reset = %08x\n", cpu_reset);
printk_spew("No cache as ram now - ");
printk(BIOS_SPEW, "cpu_reset = %08x\n", cpu_reset);
printk(BIOS_SPEW, "No cache as ram now - ");
/* store cpu_reset to ebx */
__asm__ volatile (
@@ -84,5 +84,5 @@ cpu_reset_x:
}
/* We will not return */
printk_debug("sorry. parachute did not open.\n");
printk(BIOS_DEBUG, "sorry. parachute did not open.\n");
}

2
src/cpu/intel/model_6fx/model_6fx_init.c
View File

@@ -227,7 +227,7 @@ static void model_6fx_init(device_t cpu)
/* Print processor name */
fill_processor_name(processor_name);
printk_info("CPU: %s.\n", processor_name);
printk(BIOS_INFO, "CPU: %s.\n", processor_name);
#if CONFIG_USBDEBUG_DIRECT
// Is this caution really needed?

8
src/cpu/intel/speedstep/acpi.c
View File

@@ -56,7 +56,7 @@ static int get_fsb(void)
case 3: return 166;
case 5: return 100;
}
printk_debug("Warning: No supported FSB frequency. Assuming 200MHz\n");
printk(BIOS_DEBUG, "Warning: No supported FSB frequency. Assuming 200MHz\n");
return 200;
}
@@ -68,7 +68,7 @@ void generate_cpu_entries(void)
int totalcores = determine_total_number_of_cores();
int cores_per_package = (cpuid_ebx(1)>>16) & 0xff;
int numcpus = totalcores/cores_per_package; // this assumes that all CPUs share the same layout
printk_debug("Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
printk(BIOS_DEBUG, "Found %d CPU(s) with %d core(s) each.\n", numcpus, cores_per_package);
for (cpuID=1; cpuID <=numcpus; cpuID++) {
for (coreID=1; coreID<=cores_per_package; coreID++) {
@@ -93,7 +93,7 @@ void generate_cpu_entries(void)
int vid_max=msr.lo & 0x3f;
int clock_max=get_fsb()*busratio_max;
int clock_min=get_fsb()*busratio_min;
printk_debug("clocks between %d and %d MHz.\n", clock_min, clock_max);
printk(BIOS_DEBUG, "clocks between %d and %d MHz.\n", clock_min, clock_max);
#define MEROM_MIN_POWER 16000
#define MEROM_MAX_POWER 35000
int power_max=MEROM_MAX_POWER;
@@ -104,7 +104,7 @@ void generate_cpu_entries(void)
busratio_step <<= 1;
num_states >>= 1;
}
printk_debug("adding %x P-States between busratio %x and %x, incl. P0\n", num_states+1, busratio_min, busratio_max);
printk(BIOS_DEBUG, "adding %x P-States between busratio %x and %x, incl. P0\n", num_states+1, busratio_min, busratio_max);
int vid_step=(vid_max-vid_min)/num_states;
int power_step=(power_max-power_min)/num_states;
int clock_step=(clock_max-clock_min)/num_states;

36
src/cpu/via/model_c7/model_c7_init.c
View File

@@ -68,7 +68,7 @@ static int c7d_speed_translation[] = {
static void set_c7_speed(int model) {
int cnt, current, new, i;
msr_t msr;
printk_debug("Enabling improved C7 clock and voltage.\n");
printk(BIOS_DEBUG, "Enabling improved C7 clock and voltage.\n");
// Enable Speedstep
msr = rdmsr(MSR_IA32_MISC_ENABLE);
@@ -77,16 +77,16 @@ static void set_c7_speed(int model) {
msr = rdmsr(MSR_IA32_PERF_STATUS);
printk_info("Voltage: %dmV (min %dmV; max %dmV)\n",
printk(BIOS_INFO, "Voltage: %dmV (min %dmV; max %dmV)\n",
((int)(msr.lo & 0xff) * 16 + 700),
((int)((msr.hi >> 16) & 0xff) * 16 + 700),
((int)(msr.hi & 0xff) * 16 + 700));
printk_info("CPU multiplier: %dx (min %dx; max %dx)\n",
printk(BIOS_INFO, "CPU multiplier: %dx (min %dx; max %dx)\n",
(int)((msr.lo >> 8) & 0xff),
(int)((msr.hi >> 24) & 0xff), (int)((msr.hi >> 8) & 0xff));
printk_debug(" msr.lo = %x\n", msr.lo);
printk(BIOS_DEBUG, " msr.lo = %x\n", msr.lo);
/* Wait while CPU is busy */
cnt = 0;
@@ -95,7 +95,7 @@ static void set_c7_speed(int model) {
msr = rdmsr(MSR_IA32_PERF_STATUS);
cnt++;
if (cnt > 128) {
printk_warning("Could not update multiplier and voltage.\n");
printk(BIOS_WARNING, "Could not update multiplier and voltage.\n");
return;
}
}
@@ -129,7 +129,7 @@ static void set_c7_speed(int model) {
msr.lo = new;
msr.hi = 0;
printk_debug(" new msr.lo = %x\n", msr.lo);
printk(BIOS_DEBUG, " new msr.lo = %x\n", msr.lo);
wrmsr(MSR_IA32_PERF_CTL, msr);
@@ -140,13 +140,13 @@ static void set_c7_speed(int model) {
msr = rdmsr(MSR_IA32_PERF_STATUS);
cnt++;
if (cnt > 128) {
printk_warning("Error while updating multiplier and voltage\n");
printk(BIOS_WARNING, "Error while updating multiplier and voltage\n");
break;
}
} while (msr.lo & ((1 << 16) | (1 << 17)));
printk_info("Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
printk_info("Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
printk(BIOS_INFO, "Current voltage: %dmV\n", ((int)(msr.lo & 0xff) * 16 + 700));
printk(BIOS_INFO, "Current CPU multiplier: %dx\n", (int)((msr.lo >> 8) & 0xff));
}
static void model_c7_init(device_t dev)
@@ -157,39 +157,39 @@ static void model_c7_init(device_t dev)
get_fms(&c, dev->device);
printk_info("Detected VIA ");
printk(BIOS_INFO, "Detected VIA ");
switch (c.x86_model) {
case 10:
msr = rdmsr(0x1153);
brand = (((msr.lo >> 2) ^ msr.lo) >> 18) & 3;
printk_info("Model A ");
printk(BIOS_INFO, "Model A ");
break;
case 13:
msr = rdmsr(0x1154);
brand = (((msr.lo >> 4) ^ (msr.lo >> 2))) & 0x000000ff;
printk_info("Model D ");
printk(BIOS_INFO, "Model D ");
break;
default:
printk_info("Model Unknown ");
printk(BIOS_INFO, "Model Unknown ");
brand = 0xff;
}
switch (brand) {
case 0:
printk_info("C7-M\n");
printk(BIOS_INFO, "C7-M\n");
break;
case 1:
printk_info("C7\n");
printk(BIOS_INFO, "C7\n");
break;
case 2:
printk_info("Eden\n");
printk(BIOS_INFO, "Eden\n");
break;
case 3:
printk_info("C7-D\n");
printk(BIOS_INFO, "C7-D\n");
break;
default:
printk_info("%02x (please report)\n", brand);
printk(BIOS_INFO, "%02x (please report)\n", brand);
}
/* Gear up */

2
src/cpu/x86/cache/cache.c vendored
View File

@@ -4,7 +4,7 @@
void x86_enable_cache(void)
{
post_code(0x60);
printk_info("Enabling cache\n");
printk(BIOS_INFO, "Enabling cache\n");
enable_cache();
}

8
src/cpu/x86/lapic/lapic.c
View File

@@ -17,7 +17,7 @@ void setup_lapic(void)
/* Only Pentium Pro and later have those MSR stuff */
msr_t msr;
printk_info("Setting up local apic...");
printk(BIOS_INFO, "Setting up local apic...");
/* Enable the local apic */
msr = rdmsr(LAPIC_BASE_MSR);
@@ -55,18 +55,18 @@ void setup_lapic(void)
LAPIC_DELIVERY_MODE_NMI)
);
printk_debug(" apic_id: 0x%02lx ", lapicid());
printk(BIOS_DEBUG, " apic_id: 0x%02lx ", lapicid());
#else /* !NEED_LLAPIC */
/* Only Pentium Pro and later have those MSR stuff */
msr_t msr;
printk_info("Disabling local apic...");
printk(BIOS_INFO, "Disabling local apic...");
msr = rdmsr(LAPIC_BASE_MSR);
msr.lo &= ~LAPIC_BASE_MSR_ENABLE;
wrmsr(LAPIC_BASE_MSR, msr);
#endif /* !NEED_LAPIC */
printk_info("done.\n");
printk(BIOS_INFO, "done.\n");
post_code(0x9b);
}

68
src/cpu/x86/lapic/lapic_cpu_init.c
View File

@@ -66,7 +66,7 @@ static void copy_secondary_start_to_1m_below(void)
/* copy the _secondary_start to the ram below 1M*/
memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
#endif
}
@@ -80,7 +80,7 @@ static int lapic_start_cpu(unsigned long apicid)
* Starting actual IPI sequence...
*/
printk_spew("Asserting INIT.\n");
printk(BIOS_SPEW, "Asserting INIT.\n");
/*
* Turn INIT on target chip
@@ -94,28 +94,28 @@ static int lapic_start_cpu(unsigned long apicid)
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
| LAPIC_DM_INIT);
printk_spew("Waiting for send to finish...\n");
printk(BIOS_SPEW, "Waiting for send to finish...\n");
timeout = 0;
do {
printk_spew("+");
printk(BIOS_SPEW, "+");
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
printk_err("CPU %ld: First apic write timed out. Disabling\n",
printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n",
apicid);
// too bad.
printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) {
printk_err("Try to reset ESR\n");
printk(BIOS_ERR, "Try to reset ESR\n");
lapic_write_around(LAPIC_ESR, 0);
printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
}
return 0;
}
mdelay(10);
printk_spew("Deasserting INIT.\n");
printk(BIOS_SPEW, "Deasserting INIT.\n");
/* Target chip */
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
@@ -123,15 +123,15 @@ static int lapic_start_cpu(unsigned long apicid)
/* Send IPI */
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
printk_spew("Waiting for send to finish...\n");
printk(BIOS_SPEW, "Waiting for send to finish...\n");
timeout = 0;
do {
printk_spew("+");
printk(BIOS_SPEW, "+");
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
printk_err("CPU %ld: Second apic write timed out. Disabling\n",
printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n",
apicid);
// too bad.
return 0;
@@ -148,16 +148,16 @@ static int lapic_start_cpu(unsigned long apicid)
/*
* Run STARTUP IPI loop.
*/
printk_spew("#startup loops: %d.\n", num_starts);
printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts);
maxlvt = 4;
for (j = 1; j <= num_starts; j++) {
printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid);
printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid);
lapic_read_around(LAPIC_SPIV);
lapic_write(LAPIC_ESR, 0);
lapic_read(LAPIC_ESR);
printk_spew("After apic_write.\n");
printk(BIOS_SPEW, "After apic_write.\n");
/*
* STARTUP IPI
@@ -176,12 +176,12 @@ static int lapic_start_cpu(unsigned long apicid)
*/
udelay(300);
printk_spew("Startup point 1.\n");
printk(BIOS_SPEW, "Startup point 1.\n");
printk_spew("Waiting for send to finish...\n");
printk(BIOS_SPEW, "Waiting for send to finish...\n");
timeout = 0;
do {
printk_spew("+");
printk(BIOS_SPEW, "+");
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
@@ -201,11 +201,11 @@ static int lapic_start_cpu(unsigned long apicid)
if (send_status || accept_status)
break;
}
printk_spew("After Startup.\n");
printk(BIOS_SPEW, "After Startup.\n");
if (send_status)
printk_warning("APIC never delivered???\n");
printk(BIOS_WARNING, "APIC never delivered???\n");
if (accept_status)
printk_warning("APIC delivery error (%lx).\n", accept_status);
printk(BIOS_WARNING, "APIC delivery error (%lx).\n", accept_status);
if (send_status || accept_status)
return 0;
return 1;
@@ -294,7 +294,7 @@ void stop_this_cpu(void)
id = lapic_read(LAPIC_ID) >> 24;
printk_debug("CPU %ld going down...\n", id);
printk(BIOS_DEBUG, "CPU %ld going down...\n", id);
/* send an LAPIC INIT to myself */
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
@@ -302,37 +302,37 @@ void stop_this_cpu(void)
/* wait for the ipi send to finish */
#if 0
// When these two printk_spew calls are not removed, the
// When these two printk(BIOS_SPEW, ...) calls are not removed, the
// machine will hang when log level is SPEW. Why?
printk_spew("Waiting for send to finish...\n");
printk(BIOS_SPEW, "Waiting for send to finish...\n");
#endif
timeout = 0;
do {
#if 0
printk_spew("+");
printk(BIOS_SPEW, "+");
#endif
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
printk_err("timed out\n");
printk(BIOS_ERR, "timed out\n");
}
mdelay(10);
printk_spew("Deasserting INIT.\n");
printk(BIOS_SPEW, "Deasserting INIT.\n");
/* Deassert the LAPIC INIT */
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
printk_spew("Waiting for send to finish...\n");
printk(BIOS_SPEW, "Waiting for send to finish...\n");
timeout = 0;
do {
printk_spew("+");
printk(BIOS_SPEW, "+");
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
printk_err("timed out\n");
printk(BIOS_ERR, "timed out\n");
}
while(1) {
@@ -387,7 +387,7 @@ static void start_other_cpus(struct bus *cpu_bus, device_t bsp_cpu)
if (!start_cpu(cpu)) {
/* Record the error in cpu? */
printk_err("CPU 0x%02x would not start!\n",
printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
#if CONFIG_SERIAL_CPU_INIT == 1
@@ -408,7 +408,7 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
active_count = atomic_read(&active_cpus);
while(active_count > 1) {
if (active_count != old_active_count) {
printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1);
old_active_count = active_count;
}
udelay(10);
@@ -419,11 +419,11 @@ static void wait_other_cpus_stop(struct bus *cpu_bus)
continue;
}
if (!cpu->initialized) {
printk_err("CPU 0x%02x did not initialize!\n",
printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
cpu->path.apic.apic_id);
}
}
printk_debug("All AP CPUs stopped\n");
printk(BIOS_DEBUG, "All AP CPUs stopped\n");
}
#else /* CONFIG_SMP */

48
src/cpu/x86/mtrr/mtrr.c
View File

@@ -98,7 +98,7 @@ static void set_var_mtrr(
base.hi = basek >> 22;
base.lo = basek << 10;
printk_spew("ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
printk(BIOS_SPEW, "ADDRESS_MASK_HIGH=%#x\n", address_mask_high);
if (sizek < 4*1024*1024) {
mask.hi = address_mask_high;
@@ -236,12 +236,12 @@ static unsigned int range_to_mtrr(unsigned int reg,
/* If there's no MTRR hole, this function will bail out
* here when called for the hole.
*/
printk_spew("Zero-sized MTRR range @%ldKB\n", range_startk);
printk(BIOS_SPEW, "Zero-sized MTRR range @%ldKB\n", range_startk);
return reg;
}
if (reg >= BIOS_MTRRS) {
printk_err("Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
printk(BIOS_ERR, "Warning: Out of MTRRs for base: %4ldMB, range: %ldMB, type %s\n",
range_startk >>10, range_sizek >> 10,
(type==MTRR_TYPE_UNCACHEABLE)?"UC":
((type==MTRR_TYPE_WRBACK)?"WB":"Other") );
@@ -258,7 +258,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
align = max_align;
}
sizek = 1 << align;
printk_debug("Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
printk(BIOS_DEBUG, "Setting variable MTRR %d, base: %4ldMB, range: %4ldMB, type %s\n",
reg, range_startk >>10, sizek >> 10,
(type==MTRR_TYPE_UNCACHEABLE)?"UC":
((type==MTRR_TYPE_WRBACK)?"WB":"Other")
@@ -267,7 +267,7 @@ static unsigned int range_to_mtrr(unsigned int reg,
range_startk += sizek;
range_sizek -= sizek;
if (reg >= BIOS_MTRRS) {
printk_err("Running out of variable MTRRs!\n");
printk(BIOS_ERR, "Running out of variable MTRRs!\n");
break;
}
}
@@ -295,7 +295,7 @@ static void set_fixed_mtrr_resource(void *gp, struct device *dev, struct resourc
if (start_mtrr >= NUM_FIXED_RANGES) {
return;
}
printk_debug("Setting fixed MTRRs(%d-%d) Type: WB\n",
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: WB\n",
start_mtrr, last_mtrr);
set_fixed_mtrrs(start_mtrr, last_mtrr, MTRR_TYPE_WRBACK);
@@ -357,7 +357,7 @@ void set_var_mtrr_resource(void *gp, struct device *dev, struct resource *res)
#endif
}
/* Allocate an msr */
printk_spew(" Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek);
printk(BIOS_SPEW, " Allocate an msr - basek = %08lx, sizek = %08lx,\n", basek, sizek);
state->range_startk = basek;
state->range_sizek = sizek;
}
@@ -369,9 +369,9 @@ void x86_setup_fixed_mtrrs(void)
* and clear out the mtrrs.
*/
printk_debug("\n");
printk(BIOS_DEBUG, "\n");
/* Initialized the fixed_mtrrs to uncached */
printk_debug("Setting fixed MTRRs(%d-%d) Type: UC\n",
printk(BIOS_DEBUG, "Setting fixed MTRRs(%d-%d) Type: UC\n",
0, NUM_FIXED_RANGES);
set_fixed_mtrrs(0, NUM_FIXED_RANGES, MTRR_TYPE_UNCACHEABLE);
@@ -380,10 +380,10 @@ void x86_setup_fixed_mtrrs(void)
search_global_resources(
IORESOURCE_MEM | IORESOURCE_CACHEABLE, IORESOURCE_MEM | IORESOURCE_CACHEABLE,
set_fixed_mtrr_resource, NULL);
printk_debug("DONE fixed MTRRs\n");
printk(BIOS_DEBUG, "DONE fixed MTRRs\n");
/* enable fixed MTRR */
printk_spew("call enable_fixed_mtrr()\n");
printk(BIOS_SPEW, "call enable_fixed_mtrr()\n");
enable_fixed_mtrr();
}
@@ -421,7 +421,7 @@ void x86_setup_var_mtrrs(unsigned address_bits)
#if (CONFIG_GFXUMA == 1) /* UMA or SP. */
// For now we assume the UMA space is at the end of memory
if (var_state.hole_startk || var_state.hole_sizek) {
printk_debug("Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");
printk(BIOS_DEBUG, "Warning: Can't set up MTRR hole for UMA due to pre-existing MTRR hole.\n");
} else {
// Increase the base range and set up UMA as an UC hole instead
var_state.range_sizek += (uma_memory_size >> 10);
@@ -437,15 +437,15 @@ void x86_setup_var_mtrrs(unsigned address_bits)
var_state.reg = range_to_mtrr(var_state.reg, var_state.hole_startk,
var_state.hole_sizek, 0, MTRR_TYPE_UNCACHEABLE, var_state.address_bits);
#endif
printk_debug("DONE variable MTRRs\n");
printk_debug("Clear out the extra MTRR's\n");
printk(BIOS_DEBUG, "DONE variable MTRRs\n");
printk(BIOS_DEBUG, "Clear out the extra MTRR's\n");
/* Clear out the extra MTRR's */
while(var_state.reg < MTRRS) {
set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
}
printk_spew("call enable_var_mtrr()\n");
printk(BIOS_SPEW, "call enable_var_mtrr()\n");
enable_var_mtrr();
printk_spew("Leave %s\n", __func__);
printk(BIOS_SPEW, "Leave %s\n", __func__);
post_code(0x6A);
}
@@ -460,24 +460,24 @@ int x86_mtrr_check(void)
{
/* Only Pentium Pro and later have MTRR */
msr_t msr;
printk_debug("\nMTRR check\n");
printk(BIOS_DEBUG, "\nMTRR check\n");
msr = rdmsr(0x2ff);
msr.lo >>= 10;
printk_debug("Fixed MTRRs : ");
printk(BIOS_DEBUG, "Fixed MTRRs : ");
if (msr.lo & 0x01)
printk_debug("Enabled\n");
printk(BIOS_DEBUG, "Enabled\n");
else
printk_debug("Disabled\n");
printk(BIOS_DEBUG, "Disabled\n");
printk_debug("Variable MTRRs: ");
printk(BIOS_DEBUG, "Variable MTRRs: ");
if (msr.lo & 0x02)
printk_debug("Enabled\n");
printk(BIOS_DEBUG, "Enabled\n");
else
printk_debug("Disabled\n");
printk(BIOS_DEBUG, "Disabled\n");
printk_debug("\n");
printk(BIOS_DEBUG, "\n");
post_code(0x93);
return ((int) msr.lo);

2
src/cpu/x86/pae/pgtbl.c
View File

@@ -66,7 +66,7 @@ void *map_2M_page(unsigned long page)
#warning "We may need to increase CONFIG_RAMTOP, it need to be more than (0x100000+20480*CONFIG_MAX_CPUS)\n"
#endif
if(x_end > (CONFIG_RAMTOP)) {
printk_debug("map_2M_page: Please increase the CONFIG_RAMTOP more than %dK\n", x_end);
printk(BIOS_DEBUG, "map_2M_page: Please increase the CONFIG_RAMTOP more than %dK\n", x_end);
die("Can not go on");
}
#else

10
src/cpu/x86/smm/smihandler.c
View File

@@ -68,7 +68,7 @@ void io_trap_handler(int smif)
/* If a handler function handled a given IO trap, it
* shall return a non-zero value
*/
printk_debug("SMI function trap 0x%x: ", smif);
printk(BIOS_DEBUG, "SMI function trap 0x%x: ", smif);
if (southbridge_io_trap_handler(smif))
return;
@@ -76,7 +76,7 @@ void io_trap_handler(int smif)
if (mainboard_io_trap_handler(smif))
return;
printk_debug("Unknown function\n");
printk(BIOS_DEBUG, "Unknown function\n");
}
/**
@@ -111,7 +111,7 @@ void smi_handler(u32 smm_revision)
console_init();
printk_spew("\nSMI# #%d\n", node);
printk(BIOS_SPEW, "\nSMI# #%d\n", node);
switch (smm_revision) {
case 0x00030002:
@@ -131,8 +131,8 @@ void smi_handler(u32 smm_revision)
(0xa8000 + 0x7e00 - (node * 0x400));
break;
default:
printk_debug("smm_revision: 0x%08x\n", smm_revision);
printk_debug("SMI# not supported on your CPU\n");
printk(BIOS_DEBUG, "smm_revision: 0x%08x\n", smm_revision);
printk(BIOS_DEBUG, "SMI# not supported on your CPU\n");
/* Don't release lock, so no further SMI will happen,
* if we don't handle it anyways.
*/

12
src/cpu/x86/tsc/delay_tsc.c
View File

@@ -78,7 +78,7 @@ static unsigned long long calibrate_tsc(void)
* 32 bits..
*/
bad_ctc:
printk_err("bad_ctc\n");
printk(BIOS_ERR, "bad_ctc\n");
return 0;
}
@@ -104,7 +104,7 @@ static unsigned long long calibrate_tsc(void)
unsigned long long start, end, delta;
unsigned long result, count;
printk_spew("Calibrating delay loop...\n");
printk(BIOS_SPEW, "Calibrating delay loop...\n");
start = rdtscll();
// no udivdi3 because we don't like libgcc. (only in x86emu)
// so we count to 1<< 20 and then right shift 20
@@ -128,10 +128,10 @@ static unsigned long long calibrate_tsc(void)
delta >>= 20;
// save this for microsecond timing.
result = delta;
printk_spew("end %llx, start %llx\n", end, start);
printk_spew("32-bit delta %ld\n", (unsigned long) delta);
printk(BIOS_SPEW, "end %llx, start %llx\n", end, start);
printk(BIOS_SPEW, "32-bit delta %ld\n", (unsigned long) delta);
printk_spew("%s 32-bit result is %ld\n",
printk(BIOS_SPEW, "%s 32-bit result is %ld\n",
__func__,
result);
return delta;
@@ -144,7 +144,7 @@ void init_timer(void)
{
if (!clocks_per_usec) {
clocks_per_usec = calibrate_tsc();
printk_info("clocks_per_usec: %lu\n", clocks_per_usec);
printk(BIOS_INFO, "clocks_per_usec: %lu\n", clocks_per_usec);
}
}