Kconfig: Drop the C_ENVIRONMENT_BOOTBLOCK symbol

The romcc bootblock will be deprecated soon and most platforms use
C_ENVIRONMENT_BOOTBLOCK already. This patch drops the
CONFIG_C_ENVIRONMENT_BOOTBLOCK symbol and adds CONFIG_ROMCC_BOOTBLOCK
where needed.

Change-Id: I773a76aade623303b7cd95ebe9b0411e5a7ecbaf
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>

src/cpu/intel/car/non-evict/cache_as_ram.S

@@ -29,7 +29,7 @@ _cache_as_ram_setup:
 
 bootblock_pre_c_entry:
 
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(ROMCC_BOOTBLOCK)
 	movl	$cache_as_ram, %esp /* return address */
 	jmp	check_mtrr /* Check if CPU properly reset */
 #endif

src/cpu/intel/car/p3/cache_as_ram.S

@@ -18,7 +18,7 @@
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK)
+#if !CONFIG(ROMCC_BOOTBLOCK)
 #if ((CONFIG_C_ENV_BOOTBLOCK_SIZE & (CONFIG_C_ENV_BOOTBLOCK_SIZE - 1)) != 0)
 #error "CONFIG_C_ENV_BOOTBLOCK_SIZE must be a power of 2!"
 #endif

src/cpu/intel/car/romstage.c

@@ -71,8 +71,8 @@ static void romstage_main(unsigned long bist)
 	/* We do not return here. */
 }
 
-#if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
-/* This wrapper enables easy transition towards C_ENVIRONMENT_BOOTBLOCK,
+#if CONFIG(ROMCC_BOOTBLOCK)
+/* This wrapper enables easy transition away from ROMCC_BOOTBLOCK
  * keeping changes in cache_as_ram.S easy to manage.
  */
 asmlinkage void bootblock_c_entry_bist(uint64_t base_timestamp, uint32_t bist)

src/cpu/intel/microcode/Kconfig

@@ -1,7 +1,7 @@
 config MICROCODE_UPDATE_PRE_RAM
 	bool
 	depends on SUPPORT_CPU_UCODE_IN_CBFS
-	default y if C_ENVIRONMENT_BOOTBLOCK
+	default y if !ROMCC_BOOTBLOCK
 	help
 	  Select this option if you want to update the microcode
 	  during the cache as ram setup.

src/cpu/intel/model_206ax/Kconfig

@@ -21,7 +21,6 @@ config CPU_SPECIFIC_OPTIONS
 	select CPU_INTEL_COMMON_TIMEBASE
 	select PARALLEL_MP
 	select NO_FIXED_XIP_ROM_SIZE
-	select C_ENVIRONMENT_BOOTBLOCK
 
 config SMM_TSEG_SIZE
 	hex

src/cpu/intel/slot_1/Kconfig

@@ -27,6 +27,7 @@ config SLOT_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
 	select UNKNOWN_TSC_RATE
+	select ROMCC_BOOTBLOCK
 
 config DCACHE_RAM_BASE
 	hex

src/cpu/intel/socket_mPGA604/Kconfig

@@ -11,7 +11,6 @@ config SOCKET_SPECIFIC_OPTIONS # dummy
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
 	select SIPI_VECTOR_IN_ROM
-	select C_ENVIRONMENT_BOOTBLOCK
 	select CPU_INTEL_COMMON
 	select CPU_INTEL_COMMON_TIMEBASE
 

src/cpu/qemu-x86/Kconfig

@@ -21,5 +21,4 @@ config CPU_QEMU_X86
 	select UDELAY_TSC
 	select TSC_MONOTONIC_TIMER
 	select UNKNOWN_TSC_RATE
-	select C_ENVIRONMENT_BOOTBLOCK
 	select SMM_ASEG

src/cpu/x86/16bit/entry16.inc

@@ -29,7 +29,7 @@
 
 #include <arch/rom_segs.h>
 
-#if CONFIG(C_ENVIRONMENT_BOOTBLOCK) || \
+#if !CONFIG(ROMCC_BOOTBLOCK) || \
     CONFIG(SIPI_VECTOR_IN_ROM)
 /* Symbol _start16bit must be aligned to 4kB to start AP CPUs with
  * Startup IPI message without RAM.

src/cpu/x86/Kconfig

@@ -77,7 +77,7 @@ config XIP_ROM_SIZE
 
 config SETUP_XIP_CACHE
 	bool
-	depends on C_ENVIRONMENT_BOOTBLOCK
+	depends on !ROMCC_BOOTBLOCK
 	depends on !NO_XIP_EARLY_STAGES
 	help
 	  Select this option to set up an MTRR to cache XIP stages loaded