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updated to new svn repo

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git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2018 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
2005-09-12 13:42:12 +00:00
parent ccf52a92f4
commit c06ca3af71
4 changed files with 782 additions and 34 deletions
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82
src/cpu/amd/sc520/raminit.c
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@ -162,13 +162,50 @@ setupsc520(void){
* with these short pointers, it now reliably comes up after power cycle
* with printk. Ah yi yi.
*/
/* turn off the write buffer*/
/* per the note above, make this a short? Let's try it.
*/
/* turn off the write buffer*/
/* per the note above, make this a short? Let's try it.
*/
sp = (unsigned short *)0xfffef040;
*sp = 0;
*sp = 0;
/* as per the book: */
/* PAR register setup */
/* set up the PAR registers as they are on the MSM586SEG */
par = (unsigned long *) 0xfffef088;
/* NOTE: move this to mainboard.c ASAP */
#if 1
*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
*par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
*par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
*par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
*par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
*par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
*par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
*par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
*par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
*par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
#else
par += 15;
#endif
*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
/* CPCSF register */
sp = (unsigned short *)0xfffefc24;
*sp = 0xfe;
/* ADDDECTL */
sp = (unsigned short *)0xfffefc80;
*sp = 0x10;
/* byte writes in AMD assembly */
/* we do short anyway, since u-boot does ... */
@ -223,16 +260,18 @@ setupsc520(void){
#endif
/*; set the uart baud rate clocks to the normal 1.8432 MHz.*/
/* enable interrupts here? Why not? */
cp = (unsigned char *)0xfffefcc0;
*cp = 4; /* uart 1 clock source */
*cp = 4 | 3; /* uart 1 clock source */
cp = (unsigned char *)0xfffefcc4;
*cp = 4; /* uart 2 clock source */
#if 0
/*; set the interrupt mapping registers.*/
cp = (unsigned char *)0x0fffefd20;
*cp = 0x01;
x cp = (unsigned char *)0x0fffefd28;
cp = (unsigned char *)0x0fffefd28;
*cp = 0x0c;
cp = (unsigned char *)0x0fffefd29;
@ -246,7 +285,7 @@ x cp = (unsigned char *)0x0fffefd28;
cp = (unsigned char *)0x0fffefd51;
*cp = 0x02;
#endif
/*; "enumerate" the PCI. Mainly set the interrupt bits on the PCnetFast. */
outl(0xcf8, 0x08000683c);
outl(0xcfc, 0xc); /* set the interrupt line */
@ -257,32 +296,7 @@ x cp = (unsigned char *)0x0fffefd28;
outl(0x0cf8,0x080000004); /*index the status command register on device 0*/
outl(0xcfc, 0x2); /*set the memory access enable bit*/
OUTC(0x0fffef072, 1); /* enable req bits in SYSARBMENB */
#endif
/* set up the PAR registers as they are on the MSM586SEG */
par = (unsigned long *) 0xfffef088;
#if 0
*par++ = 0x607c00a0; /*PAR0: PCI:Base 0xa0000; size 0x1f000:*/
*par++ = 0x480400d8; /*PAR1: GP BUS MEM:CS2:Base 0xd8, size 0x4:*/
*par++ = 0x340100ea; /*PAR2: GP BUS IO:CS5:Base 0xea, size 0x1:*/
*par++ = 0x380701f0; /*PAR3: GP BUS IO:CS6:Base 0x1f0, size 0x7:*/
*par++ = 0x3c0003f6; /*PAR4: GP BUS IO:CS7:Base 0x3f6, size 0x0:*/
*par++ = 0x35ff0400; /*PAR5: GP BUS IO:CS5:Base 0x400, size 0xff:*/
*par++ = 0x35ff0600; /*PAR6: GP BUS IO:CS5:Base 0x600, size 0xff:*/
*par++ = 0x35ff0800; /*PAR7: GP BUS IO:CS5:Base 0x800, size 0xff:*/
*par++ = 0x35ff0a00; /*PAR8: GP BUS IO:CS5:Base 0xa00, size 0xff:*/
*par++ = 0x35ff0e00; /*PAR9: GP BUS IO:CS5:Base 0xe00, size 0xff:*/
*par++ = 0x34fb0104; /*PAR10: GP BUS IO:CS5:Base 0x104, size 0xfb:*/
*par++ = 0x35af0200; /*PAR11: GP BUS IO:CS5:Base 0x200, size 0xaf:*/
*par++ = 0x341f03e0; /*PAR12: GP BUS IO:CS5:Base 0x3e0, size 0x1f:*/
*par++ = 0xe41c00c0; /*PAR13: SDRAM:code:cache:nowrite:Base 0xc0000, size 0x7000:*/
*par++ = 0x545c00c8; /*PAR14: GP BUS MEM:CS5:Base 0xc8, size 0x5c:*/
#else
par += 15;
#endif
*par++ = 0x8a020200; /*PAR15: BOOTCS:code:nocache:write:Base 0x2000000, size 0x80000:*/
}