ACPI: Use common OperationRegion for PCI_MMCONF
Change-Id: Iadb4c3c77ecda4df8e48415d246e769ede2ce86d Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/50648 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -1,8 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
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OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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/* Byte offsets are computed using the following technique:
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* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
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* The 8 comes from 8 functions per device, and 4096 bytes per function config space
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@@ -29,9 +29,7 @@ Scope(\) {
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}
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Scope(\_SB) {
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/* PCIe Configuration Space for 16 busses */
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OperationRegion(PCFG, SystemMemory, PCBA, 0x01000000) /* Each bus consumes 1MB */
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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/* Byte offsets are computed using the following technique:
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* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
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* The 8 comes from 8 functions per device, and 4096 bytes per function config space
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@@ -1,8 +1,6 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* PCIe Configuration Space for CONFIG_MMCONF_BUS_NUMBER busses */
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OperationRegion(PCFG, SystemMemory, PCBA, PCLN) /* Each bus consumes 1MB */
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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Field(PCFG, ByteAcc, NoLock, Preserve) {
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/* Byte offsets are computed using the following technique:
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* ((bus number + 1) * ((device number * 8) * 4096)) + register offset
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* The 8 comes from 8 functions per device, and 4096 bytes per function config space
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