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security/tpm: Unify the coreboot TPM software stack

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* Remove 2nd software stack in pc80 drivers directory.
* Create TSPI interface for common usage.
* Refactor TSS / TIS code base.
* Add vendor tss (Cr50) directory.
* Change kconfig options for TPM to TPM1.
* Add user / board configuration with:
  * MAINBOARD_HAS_*_TPM # * BUS driver
  * MAINBOARD_HAS_TPM1 or MAINBOARD_HAS_TPM2
  * Add kconfig TPM user selection (e.g. pluggable TPMs)
* Fix existing headers and function calls.
* Fix vboot for interface usage and antirollback mode.

Change-Id: I7ec277e82a3c20c62a0548a1a2b013e6ce8f5b3f
Signed-off-by: Philipp Deppenwiese <zaolin@das-labor.org>
Reviewed-on: https://review.coreboot.org/24903
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Philipp Deppenwiese
2018-02-27 19:40:52 +01:00
committed by Martin Roth
parent 961d31bdb3
commit c07f8fbe6f
112 changed files with 1126 additions and 1396 deletions
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8
src/drivers/spi/tpm/Kconfig
View File

@ -1,6 +1,7 @@
config SPI_TPM
bool "SPI TPM"
depends on TPM2
bool
help
SPI TPM driver is enabled!
config DRIVER_TPM_SPI_BUS
hex "SPI bus TPM chip is connected to"
@ -15,3 +16,6 @@ config DRIVER_TPM_SPI_CHIP
config MAINBOARD_HAS_SPI_TPM_CR50
bool
default n
select SPI_TPM
help
Board has SPI TPM support

7
src/drivers/spi/tpm/Makefile.inc
View File

@ -1,9 +1,4 @@
bootblock-$(CONFIG_SPI_TPM) += tis.c tpm.c
verstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
romstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
ramstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
ifneq ($(CONFIG_CHROMEOS),y)
bootblock-$(CONFIG_SPI_TPM) += tis.c tpm.c
romstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
ramstage-$(CONFIG_SPI_TPM) += tis.c tpm.c
endif