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nb/intel/gm45: Deduplicate PCIEXBAR decoding

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We can use `decode_pcie_bar` instead, if we make it non-static.

Change-Id: I4d005290355e30e6fdaae3e8e092891fddfbe4fc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44118
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons 2020-08-03 13:55:18 +02:00
parent b9bbed2c41
commit c0c951630a
3 changed files with 6 additions and 32 deletions
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35
src/northbridge/intel/gm45/acpi.c
View File

@ -1,6 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <types.h> #include <types.h>
#include <commonlib/helpers.h>
#include <console/console.h> #include <console/console.h>
#include <acpi/acpi.h> #include <acpi/acpi.h>
#include <acpi/acpigen.h> #include <acpi/acpigen.h>
@ -12,40 +13,12 @@
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
{ {
struct device *dev; u32 length, pciexbar;
u32 pciexbar = 0;
u32 pciexbar_reg;
int max_buses;
dev = dev_find_device(0x8086, 0x2a40, 0); if (!decode_pcie_bar(&pciexbar, &length))
if (!dev)
return current; return current;
pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO); const int max_buses = length / MiB;
// MMCFG not supported or not enabled.
if (!(pciexbar_reg & (1 << 0)))
return current;
switch ((pciexbar_reg >> 1) & 3) {
case 0: // 256MB
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
max_buses = 256;
break;
case 1: // 128M
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
max_buses = 128;
break;
case 2: // 64M
pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
max_buses = 64;
break;
default: // RSVD
return current;
}
if (!pciexbar)
return current;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current, current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
pciexbar, 0x0, 0x0, max_buses - 1); pciexbar, 0x0, 0x0, max_buses - 1);

1
src/northbridge/intel/gm45/gm45.h
View File

@ -433,6 +433,7 @@ struct blc_pwm_t {
int get_blc_values(const struct blc_pwm_t **entries); int get_blc_values(const struct blc_pwm_t **entries);
u16 get_blc_pwm_freq_value(const char *edid_ascii_string); u16 get_blc_pwm_freq_value(const char *edid_ascii_string);
int decode_pcie_bar(u32 *const base, u32 *const len);
#include <device/device.h> #include <device/device.h>

2
src/northbridge/intel/gm45/northbridge.c
View File

@ -21,7 +21,7 @@
static const int legacy_hole_base_k = 0xa0000 / 1024; static const int legacy_hole_base_k = 0xa0000 / 1024;
static const int legacy_hole_size_k = 128; static const int legacy_hole_size_k = 128;
static int decode_pcie_bar(u32 *const base, u32 *const len) int decode_pcie_bar(u32 *const base, u32 *const len)
{ {
*base = 0; *base = 0;
*len = 0; *len = 0;