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Add initial support for the Intel 82810 northbridge.

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Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Joseph Smith <joe@smittys.pointclark.net>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2720 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Corey Osgood
2007-06-14 12:02:38 +00:00
committed by Uwe Hermann
parent e99bd105af
commit c0eb5e0830
8 changed files with 801 additions and 0 deletions
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22
src/northbridge/intel/i82810/Config.lb Normal file
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##
## This file is part of the LinuxBIOS project.
##
## Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; either version 2 of the License, or
## (at your option) any later version.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
## You should have received a copy of the GNU General Public License
## along with this program; if not, write to the Free Software
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
##
config chip.h
object northbridge.o

25
src/northbridge/intel/i82810/chip.h Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
struct northbridge_intel_i82810_config
{
};
extern struct chip_operations northbridge_intel_i82810_ops;

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src/northbridge/intel/i82810/debug.c Normal file
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static void dump_spd_registers(const struct mem_controller *ctrl)
{
int i;
print_debug("\r\n");
for(i = 0; i < 4; i++) {
unsigned device;
device = ctrl->channel0[i];
if (device) {
int j;
print_debug("dimm: ");
print_debug_hex8(i);
print_debug(".0: ");
print_debug_hex8(device);
for(j = 0; j < 256; j++) {
int status;
unsigned char byte;
if ((j & 0xf) == 0) {
print_debug("\r\n");
print_debug_hex8(j);
print_debug(": ");
}
status = smbus_read_byte(device, j);
if (status < 0) {
print_debug("bad device\r\n");
break;
}
byte = status & 0xff;
print_debug_hex8(byte);
print_debug_char(' ');
}
print_debug("\r\n");
}
}
}

59
src/northbridge/intel/i82810/i82810.h Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
/*
* Datasheet:
* - Name: Intel 810 Chipset:
* 82810/82810-DC100 Graphics and Memory Controller Hub (GMCH)
* - URL: http://www.intel.com/design/chipsets/datashts/290656.htm
* - PDF: ftp://download.intel.com/design/chipsets/datashts/29065602.pdf
* - Order Number: 290656-002
*/
/*
* PCI Configuration Registers.
*
* Any addresses between 0x00 and 0xff not listed below are reserved and
* should not be touched.
*/
#define VID 0x00 /* Vendor Identification */
#define DID 0x02 /* Device Identification */
#define PCICMD 0x04 /* PCI Command Register */
#define PCISTS 0x06 /* PCI Status Register */
#define RID 0x08 /* Revision Identification */
#define SUBC 0x0a /* Sub-Class Code */
#define BCC 0x0b /* Base Class Code */
#define MLT 0x0d /* Master Latency Timer */
#define HDR 0x0e /* Header Type */
#define SVID 0x2c /* Subsystem Vendor Identification */
#define SID 0x2e /* Subsystem Identification */
#define CAPPTR 0x34 /* Capabilities Pointer */
/* TODO: Descriptions */
#define GMCHCFG 0x50
#define PAM 0x51
#define DRP 0x52
#define DRAMT 0x53
#define FDHC 0x58
#define SMRAM 0x70 /* System Management RAM Control */
#define MISSC 0x72
#define MISSC2 0x80
#define BUFF_SC 0x92

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src/northbridge/intel/i82810/northbridge.c Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
#include <string.h>
#include <bitops.h>
#include "chip.h"
#include "northbridge.h"
#include "i82810.h"
static void northbridge_init(device_t dev)
{
printk_spew("Northbridge init\n");
}
static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = 0,
.ops_pci = 0,
};
static struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_INTEL,
.device = 0x7120,
};
#define BRIDGE_IO_MASK (IORESOURCE_IO | IORESOURCE_MEM)
static void pci_domain_read_resources(device_t dev)
{
struct resource *resource;
unsigned reg;
/* Initialize the system wide io space constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
resource->base = 0x400;
resource->limit = 0xffffUL;
resource->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
/* Initialize the system wide memory resources constraints */
resource = new_resource(dev, IOINDEX_SUBTRACTIVE(1, 0));
resource->limit = 0xffffffffULL;
resource->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE | IORESOURCE_ASSIGNED;
}
static void ram_resource(device_t dev, unsigned long index,
unsigned long basek, unsigned long sizek)
{
struct resource *resource;
if (!sizek) {
return;
}
resource = new_resource(dev, index);
resource->base = ((resource_t)basek) << 10;
resource->size = ((resource_t)sizek) << 10;
resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
}
static void tolm_test(void *gp, struct device *dev, struct resource *new)
{
struct resource **best_p = gp;
struct resource *best;
best = *best_p;
if (!best || (best->base > new->base)) {
best = new;
}
*best_p = best;
}
static uint32_t find_pci_tolm(struct bus *bus)
{
struct resource *min;
uint32_t tolm;
min = 0;
search_bus_resources(bus, IORESOURCE_MEM, IORESOURCE_MEM, tolm_test, &min);
tolm = 0xffffffffUL;
if (min && tolm > min->base) {
tolm = min->base;
}
return tolm;
}
/* Table which returns the RAM size in MB when fed the DRP[7:4] or [3:0] value.
* Note that 2 is a value which the DRP should never be programmed to.
* Some size values appear twice, due to single-sided vs dual-sided banks.
*/
static int translate_i82810_to_mb[] = {
/* DRP 0 1 (2) 3 4 5 6 7 8 9 A B C D E F */
/* MB */0, 8, 0, 16, 16, 24, 32, 32, 48, 64, 64, 96, 128, 128, 192, 256,
};
static void pci_domain_set_resources(device_t dev)
{
device_t mc_dev;
uint32_t pci_tolm;
pci_tolm = find_pci_tolm(&dev->link[0]);
mc_dev = dev->link[0].children;
if (mc_dev) {
/* Figure out which areas are/should be occupied by RAM.
* This is all computed in kilobytes and converted to/from
* the memory controller right at the edges.
* Having different variables in different units is
* too confusing to get right. Kilobytes are good up to
* 4 Terabytes of RAM...
*/
unsigned long tomk, tolmk;
int idx;
int drp_value;
/* First get the value for DIMM 0. */
drp_value = pci_read_config8(mc_dev, DRP);
/* Translate it to MB and add to tomk. */
tomk = (unsigned long)(translate_i82810_to_mb[drp_value & 0xf]);
/* Now do the same for DIMM 1. */
drp_value = drp_value >> 4; // >>= 4; //? mess with later
tomk += (unsigned long)(translate_i82810_to_mb[drp_value]);
printk_debug("Setting RAM size to %d MB\n", tomk);
/* Convert tomk from MB to KB. */
tomk = tomk << 10;
/* Compute the top of Low memory. */
tolmk = pci_tolm >> 10;
if (tolmk >= tomk) {
/* The PCI hole does does not overlap the memory. */
tolmk = tomk;
}
/* Report the memory regions. */
idx = 10;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 1024, tolmk - 1024);
}
assign_resources(&dev->link[0]);
}
static unsigned int pci_domain_scan_bus(device_t dev, unsigned int max)
{
max = pci_scan_bus(&dev->link[0], PCI_DEVFN(0, 0), 0xff, max);
return max;
}
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = enable_childrens_resources,
.init = 0,
.scan_bus = pci_domain_scan_bus,
};
static void cpu_bus_init(device_t dev)
{
initialize_cpus(&dev->link[0]);
}
static void cpu_bus_noop(device_t dev)
{
}
static struct device_operations cpu_bus_ops = {
.read_resources = cpu_bus_noop,
.set_resources = cpu_bus_noop,
.enable_resources = cpu_bus_noop,
.init = cpu_bus_init,
.scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
struct device_path path;
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_PCI_DOMAIN) {
dev->ops = &pci_domain_ops;
pci_set_method(dev);
}
else if (dev->path.type == DEVICE_PATH_APIC_CLUSTER) {
dev->ops = &cpu_bus_ops;
}
}
struct chip_operations northbridge_intel_i82810_ops = {
CHIP_NAME("Intel 82810 Northbridge")
.enable_dev = enable_dev,
};

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src/northbridge/intel/i82810/northbridge.h Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef NORTHBRIDGE_INTEL_I82810_NORTHBRIDGE_H
#define NORTHBRIDGE_INTEL_I82810_NORTHBRIDGE_H
extern unsigned int i82810_scan_root_bus(device_t root, unsigned int max);
#endif /* NORTHBRIDGE_INTEL_I82810_NORTHBRIDGE_H */

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src/northbridge/intel/i82810/raminit.c Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
* Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <spd.h>
#include <sdram_mode.h>
#include <delay.h>
#include "i82810.h"
/*-----------------------------------------------------------------------------
Macros and definitions.
-----------------------------------------------------------------------------*/
/* Uncomment this to enable debugging output. */
// #define DEBUG_RAM_SETUP 1
/* Debugging macros. */
#if defined(DEBUG_RAM_SETUP)
#define PRINT_DEBUG(x) print_debug(x)
#define PRINT_DEBUG_HEX8(x) print_debug_hex8(x)
#define PRINT_DEBUG_HEX16(x) print_debug_hex16(x)
#define PRINT_DEBUG_HEX32(x) print_debug_hex32(x)
#define DUMPNORTH() dump_pci_device(PCI_DEV(0, 0, 0))
#else
#define PRINT_DEBUG(x)
#define PRINT_DEBUG_HEX8(x)
#define PRINT_DEBUG_HEX16(x)
#define PRINT_DEBUG_HEX32(x)
#define DUMPNORTH()
#endif
/* DRAMT[7:5] - SDRAM Mode Select (SMS). */
#define RAM_COMMAND_SELF_REFRESH 0x0 /* IE disable refresh */
#define RAM_COMMAND_NORMAL 0x1 /* Normal refresh, 15.6us/11.7us for 100/133MHz */
#define RAM_COMMAND_NORMAL_FR 0x2 /* Fast refresh, 7.8us/5.85us for 100/133MHz */
#define RAM_COMMAND_NOP 0x4
#define RAM_COMMAND_PRECHARGE 0x5
#define RAM_COMMAND_MRS 0x6
#define RAM_COMMAND_CBR 0x7
/*-----------------------------------------------------------------------------
SDRAM configuration functions.
-----------------------------------------------------------------------------*/
/**
* Send the specified RAM command to all DIMMs.
*
* @param Memory controller
* @param TODO
* @param TODO
*/
static void do_ram_command(const struct mem_controller *ctrl, uint32_t command,
uint32_t addr_offset, uint32_t row_offset)
{
int i;
uint8_t reg;
/* TODO: Support for multiple DIMMs. */
/* Configure the RAM command. */
reg = pci_read_config8(ctrl->d0, DRAMT);
reg &= 0x1f; /* Clear bits 7-5. */
reg |= command << 5;
pci_write_config8(ctrl->d0, DRAMT, reg);
/* RAM_COMMAND_NORMAL affects only the memory controller and
doesn't need to be "sent" to the DIMMs. */
/* if (command == RAM_COMMAND_NORMAL) return; */
PRINT_DEBUG(" Sending RAM command 0x");
PRINT_DEBUG_HEX8(reg);
PRINT_DEBUG(" to 0x");
PRINT_DEBUG_HEX32(0 + addr_offset); // FIXME
PRINT_DEBUG("\r\n");
/* Read from (DIMM start address + addr_offset). */
read32(0 + addr_offset); //first offset is always 0
read32(row_offset + addr_offset);
}
/*-----------------------------------------------------------------------------
DIMM-independant configuration functions.
-----------------------------------------------------------------------------*/
static void spd_set_dram_size(const struct mem_controller *ctrl, uint32_t row_offset)
{
/* The variables drp and dimm_size have to be ints since all the
* SMBus-related functions return ints, and its just easier this way.
*/
int i, drp, dimm_size;
drp = 0x00;
for (i = 0; i < DIMM_SOCKETS; i++)
{
/* First check if a DIMM is actually present. */
if (smbus_read_byte(ctrl->channel0[i], 2) == 4) {
print_debug("Found DIMM in slot ");
print_debug_hex8(i);
print_debug("\r\n");
dimm_size = smbus_read_byte(ctrl->channel0[i], 31);
/* WISHLIST: would be nice to display it as decimal? */
print_debug("DIMM is 0x");
print_debug_hex8(dimm_size * 4);
print_debug("MB\r\n");
/* The i810 can't handle DIMMs larger than 128MB per
* side. This will fail if the DIMM uses a
* non-supported DRAM tech, and can't be used until
* buffers are done dynamically.
* Note: the factory BIOS just dies if it spots
* this :D
*/
if(dimm_size > 32) {
print_err("DIMM row sizes larger than 128MB not"
"supported on i810\r\n");
print_err("Attempting to treat as 128MB DIMM\r\n");
dimm_size = 32;
}
/* Set the row offset, in KBytes (should this be Kbits?) */
/* Note that this offset is the start of the next row. */
row_offset = (dimm_size * 4 * 1024);
/* This is the way I was doing this, it's provided mainly
* as an alternative to the "new" way.
*/
#if 0
/* 8MB */
if(dimm_size == 0x2) dimm_size = 0x1;
/* 16MB */
else if(dimm_size == 0x4) dimm_size = 0x4;
/* 32MB */
else if(dimm_size == 0x8) dimm_size = 0x7;
/* 64 MB */
else if(dimm_size == 0x10) dimm_size = 0xa;
/* 128 MB */
else if(dimm_size == 0x20) dimm_size = 0xd;
else print_debug("Ram Size not supported\r\n");
#endif
/* This array is provided in raminit.h, because it got
* extremely messy. The above way is cleaner, but
* doesn't support any asymetrical/odd configurations.
*/
dimm_size = translate_spd_to_i82810[dimm_size];
print_debug("After translation, dimm_size is 0x");
print_debug_hex8(dimm_size);
print_debug("\r\n");
/* If the DIMM is dual-sided, the DRP value is +2 */
/* TODO: Figure out asymetrical configurations */
if ((smbus_read_byte(ctrl->channel0[i], 127) | 0xf) == 0xff) {
print_debug("DIMM is dual-sided\r\n");
dimm_size += 2;
}
} else {
print_debug("No DIMM found in slot ");
print_debug_hex8(i);
print_debug("\r\n");
/* If there's no DIMM in the slot, set the value to 0. */
dimm_size = 0x00;
}
/* Put in dimm_size to reflect the current DIMM. */
drp |= dimm_size << (i * 4);
}
print_debug("DRP calculated to 0x");
print_debug_hex8(drp);
print_debug("\r\n");
pci_write_config8(ctrl->d0, DRP, drp);
}
static void set_dram_timing(const struct mem_controller *ctrl)
{
/* TODO, for now using default, hopefully safe values. */
// pci_write_config8(ctrl->d0, DRAMT, 0x00);
}
static void set_dram_buffer_strength(const struct mem_controller *ctrl)
{
/* TODO: This needs to be set according to the DRAM tech
* (x8, x16, or x32). Argh, Intel provides no docs on this!
* Currently, it needs to be pulled from the output of
* lspci -xxx Rx92
*/
pci_write_config16(ctrl->d0, BUFF_SC, 0x77da);
}
/*-----------------------------------------------------------------------------
Public interface.
-----------------------------------------------------------------------------*/
/**
* TODO.
*
* @param Memory controller
*/
static void sdram_set_registers(const struct mem_controller *ctrl)
{
unsigned long val;
/* TODO */
pci_write_config8(ctrl->d0, GMCHCFG, 0x60);
/* PAMR: Programmable Attributes Register
* Every pair of bits controls an address range:
* 00 = Disabled, all accesses are forwarded to the ICH
* 01 = Read Only
* 10 = Write Only
* 11 = Read/Write
* Bit Range
* 7:6 000F0000 - 000FFFFF
* 5:4 000E0000 - 000EFFFF
* 3:2 000D0000 - 000DFFFF
* 1:0 000C0000 - 000CFFFF
*/
/* Ideally, this should be R/W for as many ranges as possible. */
pci_write_config8(ctrl->d0, PAM, 0x00);
/* Enable 1MB framebuffer. */
pci_write_config8(ctrl->d0, SMRAM, 0xC0);
val = pci_read_config16(ctrl->d0, MISSC);
/* Preserve reserved bits. */
val &= 0xff06;
/* Set graphics cache window to 32MB, no power throttling. */
val |= 0x0001;
pci_write_config16(ctrl->d0, MISSC, val);
val = pci_read_config8(ctrl->d0, MISSC2);
/* Enable graphics palettes and clock gating (not optional!) */
val |= 0x06;
pci_write_config8(ctrl->d0, MISSC2, val);
}
/**
* TODO.
*
* @param Memory controller
*/
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
/* spd_set_dram_size() moved into sdram_enable() to prevent having
* to pass a variable between here and there.
*/
set_dram_buffer_strength(ctrl);
set_dram_timing(ctrl);
}
/**
* Enable SDRAM.
*
* @param Number of controllers
* @param Memory controller
*/
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
/* Todo: this will currently work with either one dual sided or two
* single sided DIMMs. Needs to work with 2 dual sided DIMMs in the
* long run.
*/
uint32_t row_offset;
spd_set_dram_size(ctrl, row_offset);
/* 1. Apply NOP. */
PRINT_DEBUG("RAM Enable 1: Apply NOP\r\n");
do_ram_command(ctrl, RAM_COMMAND_NOP, 0, row_offset);
udelay(200);
/* 2. Precharge all. Wait tRP. */
PRINT_DEBUG("RAM Enable 2: Precharge all\r\n");
do_ram_command(ctrl, RAM_COMMAND_PRECHARGE, 0, row_offset);
udelay(1);
/* 3. Perform 8 refresh cycles. Wait tRC each time. */
PRINT_DEBUG("RAM Enable 3: CBR\r\n");
do_ram_command(ctrl, RAM_COMMAND_CBR, 0, row_offset);
for (i = 0; i < 8; i++) {
read32(0);
read32(row_offset);
udelay(1);
}
/* 4. Mode register set. Wait two memory cycles. */
PRINT_DEBUG("RAM Enable 4: Mode register set\r\n");
do_ram_command(ctrl, RAM_COMMAND_MRS, 0x1d0, row_offset);
udelay(2);
/* 5. Normal operation (enables refresh) */
PRINT_DEBUG("RAM Enable 5: Normal operation\r\n");
do_ram_command(ctrl, RAM_COMMAND_NORMAL, 0, row_offset);
udelay(1);
PRINT_DEBUG("Northbridge following SDRAM init:\r\n");
DUMPNORTH();
}

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src/northbridge/intel/i82810/raminit.h Normal file
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/*
* This file is part of the LinuxBIOS project.
*
* Copyright (C) 2007 Corey Osgood <corey@slightlyhackish.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#ifndef NORTHBRIDGE_INTEL_I82810_RAMINIT_H
#define NORTHBRIDGE_INTEL_I82810_RAMINIT_H
/* The i810 supports max 2 dual-sided DIMMs. */
#define DIMM_SOCKETS 2
struct mem_controller {
device_t d0;
uint16_t channel0[DIMM_SOCKETS];
};
#endif /* NORTHBRIDGE_INTEL_I82810_RAMINIT_H */
/* The following table has been bumped over to this header to avoid clutter in
* raminit.c. It's used to translate the value read from SPD Byte 31 to a value
* the northbridge can understand in DRP, aka Rx52[7:4], [3:0]. Where most
* northbridges have some sort of simple calculation that can be done for this,
* I haven't yet figured out one for this northbridge. Until someone does,
* this table is necessary.
*/
/* TODO: Find a better way of doing this */
static const uint8_t translate_spd_to_i82810[] = {
/* Note: 4MB sizes are not supported, so dual-sided DIMMs with a 4MB
* side can't be either, at least for now.
*/
/* TODO: For above case, only use the other side if > 4MB, and get some
* of these DIMMs to test it with. Same for unsupported 128/x sizes.
*/
/* SPD Byte 31 Memory Size [Side 1/2] */
0xff, /* 0x01 No memory */
0xff, /* 0x01 4/0 */
0x01, /* 0x02 8/0 */
0xff, /* 0x03 8/4 */
0x04, /* 0x04 16/0 or 16 */
0xff, /* 0x05 16/4 */
0x05, /* 0x06 16/8 */
0xff, /* 0x07 Invalid */
0x07, /* 0x08 32/0 or 32 */
0xff, /* 0x09 32/4 */
0xff, /* 0x0A 32/8 */
0xff, /* 0x0B Invalid */
0x08, /* 0x0C 32/16 */
0xff, 0xff, 0xff, /* 0x0D-0F Invalid */
0x0a, /* 0x10 64/0 or 64 */
0xff, /* 0x11 64/4 */
0xff, /* 0x12 64/8 */
0xff, /* 0x13 Invalid */
0xff, /* 0x14 64/16 */
0xff, 0xff, 0xff, /* 0x15-17 Invalid */
0x0b, /* 0x18 64/32 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x19-1f Invalid */
0x0d, /* 0x20 128/0 or 128 */
/* These configurations are not supported by the i810 */
0xff, /* 0x21 128/4 */
0xff, /* 0x22 128/8 */
0xff, /* 0x23 Invalid */
0xff, /* 0x24 128/16 */
0xff, 0xff, 0xff, /* 0x25-27 Invalid */
0xff, /* 0x28 128/32 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 0x29-2f Invalid */
0x0e, /* 0x30 128/64 */
0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
0xff, 0xff, 0xff, /* 0x31-3f Invalid */
0x0f, /* 0x40 256/0 or 256 */
/* Anything larger is not supported by the i810 */
};