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vc/amd/opensil/genoa_poc/mpio: add IFTYPE_ prefix to mpio_type values

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Add an IFTYPE_ prefix to all elements of the mpio_type enum to have more
specific names.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I229a3402c36941ee5347e3704fcf8d8a1bbc78a6
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81338
Reviewed-by: Martin L Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Held 2024-03-11 22:31:43 +01:00
parent f7aafacb33
commit c12ef5d7b7
3 changed files with 16 additions and 16 deletions
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24
src/mainboard/amd/onyx_poc/devicetree.cb
View File

@ -57,7 +57,7 @@ chip soc/amd/genoa_poc
device ref rcec_0 on end device ref rcec_0 on end
device ref gpp_bridge_0_0_a on device ref gpp_bridge_0_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P2 chip vendorcode/amd/opensil/genoa_poc/mpio # P2
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "48" register "start_lane" = "48"
register "end_lane" = "63" register "end_lane" = "63"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -67,7 +67,7 @@ chip soc/amd/genoa_poc
end end
device ref gpp_bridge_0_0_b on device ref gpp_bridge_0_0_b on
chip vendorcode/amd/opensil/genoa_poc/mpio # G2 chip vendorcode/amd/opensil/genoa_poc/mpio # G2
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "112" register "start_lane" = "112"
register "end_lane" = "127" register "end_lane" = "127"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -78,7 +78,7 @@ chip soc/amd/genoa_poc
end end
device ref gpp_bridge_0_0_c on device ref gpp_bridge_0_0_c on
chip vendorcode/amd/opensil/genoa_poc/mpio chip vendorcode/amd/opensil/genoa_poc/mpio
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "128" register "start_lane" = "128"
register "end_lane" = "131" register "end_lane" = "131"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -101,7 +101,7 @@ chip soc/amd/genoa_poc
device ref rcec_1 on end device ref rcec_1 on end
device ref gpp_bridge_1_0_a on device ref gpp_bridge_1_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P3 chip vendorcode/amd/opensil/genoa_poc/mpio # P3
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "16" register "start_lane" = "16"
register "end_lane" = "31" register "end_lane" = "31"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -111,7 +111,7 @@ chip soc/amd/genoa_poc
end end
device ref gpp_bridge_1_0_b on device ref gpp_bridge_1_0_b on
chip vendorcode/amd/opensil/genoa_poc/mpio # G3 chip vendorcode/amd/opensil/genoa_poc/mpio # G3
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "80" register "start_lane" = "80"
register "end_lane" = "95" register "end_lane" = "95"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -126,7 +126,7 @@ chip soc/amd/genoa_poc
device ref rcec_2 on end device ref rcec_2 on end
device ref gpp_bridge_2_0_a on device ref gpp_bridge_2_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P1 chip vendorcode/amd/opensil/genoa_poc/mpio # P1
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "32" register "start_lane" = "32"
register "end_lane" = "47" register "end_lane" = "47"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -137,7 +137,7 @@ chip soc/amd/genoa_poc
end end
device ref gpp_bridge_2_0_b on device ref gpp_bridge_2_0_b on
chip vendorcode/amd/opensil/genoa_poc/mpio # G1 chip vendorcode/amd/opensil/genoa_poc/mpio # G1
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "64" register "start_lane" = "64"
register "end_lane" = "79" register "end_lane" = "79"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -153,7 +153,7 @@ chip soc/amd/genoa_poc
device ref rcec_3 on end device ref rcec_3 on end
device ref gpp_bridge_3_0_a on device ref gpp_bridge_3_0_a on
chip vendorcode/amd/opensil/genoa_poc/mpio # P0 chip vendorcode/amd/opensil/genoa_poc/mpio # P0
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "0" register "start_lane" = "0"
register "end_lane" = "15" register "end_lane" = "15"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -163,7 +163,7 @@ chip soc/amd/genoa_poc
end end
device ref gpp_bridge_3_0_b on device ref gpp_bridge_3_0_b on
chip vendorcode/amd/opensil/genoa_poc/mpio # G0 chip vendorcode/amd/opensil/genoa_poc/mpio # G0
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "96" register "start_lane" = "96"
register "end_lane" = "111" register "end_lane" = "111"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -173,7 +173,7 @@ chip soc/amd/genoa_poc
end end
device ref gpp_bridge_3_0_c on # WAFL device ref gpp_bridge_3_0_c on # WAFL
chip vendorcode/amd/opensil/genoa_poc/mpio chip vendorcode/amd/opensil/genoa_poc/mpio
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "132" register "start_lane" = "132"
register "end_lane" = "133" register "end_lane" = "133"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -183,7 +183,7 @@ chip soc/amd/genoa_poc
end end
device ref gpp_bridge_3_1_c on # BMC device ref gpp_bridge_3_1_c on # BMC
chip vendorcode/amd/opensil/genoa_poc/mpio chip vendorcode/amd/opensil/genoa_poc/mpio
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "134" register "start_lane" = "134"
register "end_lane" = "134" register "end_lane" = "134"
register "gpio_group" = "1" register "gpio_group" = "1"
@ -194,7 +194,7 @@ chip soc/amd/genoa_poc
end end
device ref gpp_bridge_3_2_c on # BMC device ref gpp_bridge_3_2_c on # BMC
chip vendorcode/amd/opensil/genoa_poc/mpio chip vendorcode/amd/opensil/genoa_poc/mpio
register "type" = "PCIE" register "type" = "IFTYPE_PCIE"
register "start_lane" = "135" register "start_lane" = "135"
register "end_lane" = "135" register "end_lane" = "135"
register "gpio_group" = "1" register "gpio_group" = "1"

4
src/vendorcode/amd/opensil/genoa_poc/mpio/chip.c
View File

@ -141,7 +141,7 @@ static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev
static int mpio_port = 0; static int mpio_port = 0;
MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST }; MPIO_PORT_DESCRIPTOR port = { .Flags = DESCRIPTOR_TERMINATE_LIST };
if (config->type == PCIE) { if (config->type == IFTYPE_PCIE) {
const MPIO_ENGINE_DATA engine_data = const MPIO_ENGINE_DATA engine_data =
MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine, MPIO_ENGINE_DATA_INITIALIZER(MpioPcieEngine,
config->start_lane, config->end_lane, config->start_lane, config->end_lane,
@ -160,7 +160,7 @@ static void per_device_config(MPIOCLASS_INPUT_BLK *mpio_data, struct device *dev
config->aspm_l1_2, config->aspm_l1_2,
config->clock_pm); config->clock_pm);
port.Port = port_data; port.Port = port_data;
} else if (config->type == SATA) { } else if (config->type == IFTYPE_SATA) {
const MPIO_ENGINE_DATA engine_data = const MPIO_ENGINE_DATA engine_data =
MPIO_ENGINE_DATA_INITIALIZER(MpioSATAEngine, MPIO_ENGINE_DATA_INITIALIZER(MpioSATAEngine,
config->start_lane, config->end_lane, config->start_lane, config->end_lane,

4
src/vendorcode/amd/opensil/genoa_poc/mpio/chip.h
View File

@ -17,8 +17,8 @@
*/ */
enum mpio_type { enum mpio_type {
PCIE, IFTYPE_PCIE,
SATA, IFTYPE_SATA,
}; };
/* Sync with PCIE_HOTPLUG_TYPE */ /* Sync with PCIE_HOTPLUG_TYPE */