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rockchip/rk3399: Add a stub implementation of the rk3399 SOC

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Most things still need to be filled in, but this will allow
us to build boards which use this SOC.

BRANCH=none
BUG=chrome-os-partner:51537
TEST=with the rest of the patches applied Kevin board can be booted to
     Linux login propmt.

Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 27dfc39efe95025be2271e2e00e9df93b7907840
Original-Change-Id: I6f2407ff578dcd3d0daed86dd03d8f5f4edcac53
Original-Signed-off-by: huang lin <hl@rock-chips.com>
Original-Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/332385
Reviewed-on: https://review.coreboot.org/13915
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
huang lin
2016-03-02 18:38:40 +08:00
committed by Patrick Georgi
parent 46f8bd70ef
commit c14b54dd17
11 changed files with 403 additions and 0 deletions
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26
src/soc/rockchip/rk3399/Kconfig Normal file
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config SOC_ROCKCHIP_RK3399
bool
default n
select ARCH_BOOTBLOCK_ARMV8_64
select ARCH_RAMSTAGE_ARMV8_64
select ARCH_ROMSTAGE_ARMV8_64
select ARCH_VERSTAGE_ARMV8_64
select ARM64_A53_ERRATUM_843419
select BOOTBLOCK_CONSOLE
select GENERIC_UDELAY
select HAVE_MONOTONIC_TIMER
select HAVE_UART_SPECIAL
select UNCOMPRESSED_RAMSTAGE
if SOC_ROCKCHIP_RK3399
config CHROMEOS
select RETURN_FROM_VERSTAGE
select SEPARATE_VERSTAGE
select VBOOT_STARTS_IN_BOOTBLOCK
config PMIC_BUS
int
default -1
endif

61
src/soc/rockchip/rk3399/Makefile.inc Normal file
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##
## This file is part of the coreboot project.
##
## Copyright 2016 Rockchip Inc.
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
ifeq ($(CONFIG_SOC_ROCKCHIP_RK3399),y)
IDBTOOL = util/rockchip/make_idb.py
bootblock-y += ../common/spi.c
ifeq ($(CONFIG_BOOTBLOCK_CONSOLE),y)
bootblock-$(CONFIG_DRIVERS_UART) += ../common/uart.c
endif
bootblock-y += bootblock.c
bootblock-y += clock.c
bootblock-y += timer.c
verstage-y += ../common/cbmem.c
verstage-y += ../common/spi.c
verstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
verstage-y += clock.c
verstage-y += timer.c
################################################################################
romstage-y += ../common/cbmem.c
romstage-y += ../common/spi.c
romstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
romstage-y += clock.c
romstage-y += timer.c
################################################################################
ramstage-y += ../common/cbmem.c
ramstage-y += ../common/spi.c
ramstage-$(CONFIG_DRIVERS_UART) += ../common/uart.c
ramstage-y += clock.c
ramstage-y += soc.c
ramstage-y += timer.c
################################################################################
CPPFLAGS_common += -Isrc/soc/rockchip/rk3399/include
CPPFLAGS_common += -Isrc/soc/rockchip/common/include
$(objcbfs)/bootblock.bin: $(objcbfs)/bootblock.raw.bin
@printf "Generating: $(subst $(obj)/,,$(@))\n"
@mkdir -p $(dir $@)
@$(IDBTOOL) --from=$< --to=$@ --enable-align --chip=RK33
endif

25
src/soc/rockchip/rk3399/bootblock.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2016 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <arch/io.h>
#include <arch/mmu.h>
#include <bootblock_common.h>
#include <console/console.h>
#include <symbols.h>
void bootblock_soc_init(void)
{
}

21
src/soc/rockchip/rk3399/clock.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2016 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
*/
#include <soc/clock.h>
void rkclk_configure_spi(unsigned int bus, unsigned int hz)
{
}

58
src/soc/rockchip/rk3399/include/soc/addressmap.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2016 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__
#define __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__
#define PMUGRF_BASE 0xff320000
#define PMUSGRF_BASE 0xff330000
#define CRU_BASE 0xff760000
#define GRF_BASE 0xff770000
#define TIMER0_BASE 0xff850000
#define EMMC_BASE 0xfe330000
#define SDMMC_BASE 0xfe320000
#define GPIO0_BASE 0xff720000
#define GPIO1_BASE 0xff730000
#define GPIO2_BASE 0xff780000
#define GPIO3_BASE 0xff788000
#define GPIO4_BASE 0xff790000
#define I2C0_BASE 0xff3c0000
#define I2C1_BASE 0xff110000
#define I2C2_BASE 0xff120000
#define I2C3_BASE 0xff130000
#define I2C4_BASE 0xff3d0000
#define I2C5_BASE 0xff140000
#define I2C6_BASE 0xff150000
#define I2C7_BASE 0xff160000
#define I2C8_BASE 0xff3e0000
#define UART0_BASE 0xff180000
#define UART1_BASE 0xff190000
#define UART2_BASE 0xff1a0000
#define UART3_BASE 0xff1b0000
#define UART4_BASE 0xff370000
#define SPI0_BASE 0xff1c0000
#define SPI1_BASE 0xff1d0000
#define SPI2_BASE 0xff1e0000
#define SPI3_BASE 0xff350000
#define SPI4_BASE 0xff1f0000
#define SPI5_BASE 0xff200000
#define TSADC_BASE 0xff260000
#define SARADC_BASE 0xff100000
#endif /* __SOC_ROCKCHIP_RK3399_ADDRESSMAP_H__ */

21
src/soc/rockchip/rk3399/include/soc/clock.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2016 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_ROCKCHIP_RK3399_CLOCK_H__
#define __SOC_ROCKCHIP_RK3399_CLOCK_H__
void rkclk_configure_spi(unsigned int bus, unsigned int hz);
#endif /* __SOC_ROCKCHIP_RK3399_CLOCK_H__ */

36
src/soc/rockchip/rk3399/include/soc/memlayout.ld Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2016 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <memlayout.h>
#include <arch/header.ld>
SECTIONS
{
DRAM_START(0x00000000)
POSTRAM_CBFS_CACHE(0x00100000, 1M)
RAMSTAGE(0x00300000, 256K)
DMA_COHERENT(0x10000000, 2M)
SRAM_START(0xFF8C0000)
BOOTBLOCK(0xFF8C2004, 32K - 4)
PRERAM_CBFS_CACHE(0xFF8CA000, 4K)
PRERAM_CBMEM_CONSOLE(0xFF8CB000, 4K)
OVERLAP_VERSTAGE_ROMSTAGE(0xFF8CC000, 64K)
VBOOT2_WORK(0XFF8DC000, 12K)
TTB(0xFF8DF000, 32K)
TIMESTAMP(0xFF8E7000, 1K)
STACK(0xFF8E7400, 24K)
SRAM_END(0xFF8F0000)
}

20
src/soc/rockchip/rk3399/include/soc/sdram.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* dummy until the RAM init implementation passed review */
static int sdram_size_mb(void)
{
return 0;
}

39
src/soc/rockchip/rk3399/include/soc/timer.h Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2016 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __SOC_ROCKCHIP_RK3399_TIMER_H__
#define __SOC_ROCKCHIP_RK3399_TIMER_H__
#include <inttypes.h>
#include <soc/addressmap.h>
#include <timer.h>
static const u32 clocks_per_usec = (24 * 1000 * 1000) / USECS_PER_SEC;
struct rk3399_timer {
u32 timer_load_count0;
u32 timer_load_count1;
u32 timer_cur_value0;
u32 timer_cur_value1;
u32 timer_load_count2;
u32 timer_load_count3;
u32 timer_int_status;
u32 timer_ctrl_reg;
};
static struct rk3399_timer * const timer0_ptr = (void *)TIMER0_BASE;
#define TIMER_LOAD_VAL 0xffffffff
#endif /* __SOC_ROCKCHIP_RK3399_TIMER_H__ */

51
src/soc/rockchip/rk3399/soc.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2015 MediaTek Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/cpu.h>
#include <console/console.h>
#include <device/device.h>
#include <stdlib.h>
#include <stddef.h>
#include <string.h>
#include <symbols.h>
static void soc_read_resources(device_t dev)
{
ram_resource(dev, 0, (uintptr_t)_dram / KiB,
CONFIG_DRAM_SIZE_MB * KiB);
}
static void soc_init(device_t dev)
{
/* reserve bl31 image, which define in
* arm-trusted-firmware/plat/rockchip/rk3399/include/platform_def.h
*/
mmio_resource(dev, 1, (0x500000 / KiB), (0x80000 / KiB));
}
static struct device_operations soc_ops = {
.read_resources = soc_read_resources,
.init = soc_init,
};
static void enable_soc_dev(device_t dev)
{
dev->ops = &soc_ops;
}
struct chip_operations soc_rockchip_rk3399_ops = {
CHIP_NAME("SOC Rockchip RK3399\n")
.enable_dev = enable_soc_dev,
};

45
src/soc/rockchip/rk3399/timer.c Normal file
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/*
* This file is part of the coreboot project.
*
* Copyright 2016 Rockchip Inc.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <delay.h>
#include <soc/timer.h>
#include <stdint.h>
#include <timer.h>
static uint64_t timer_raw_value(void)
{
uint64_t value0;
uint64_t value1;
value0 = (uint64_t)read32(&timer0_ptr->timer_cur_value0);
value1 = (uint64_t)read32(&timer0_ptr->timer_cur_value1);
return value0 | value1<<32;
}
void timer_monotonic_get(struct mono_time *mt)
{
mono_time_set_usecs(mt, timer_raw_value() / clocks_per_usec);
}
void init_timer(void)
{
write32(&timer0_ptr->timer_load_count0, TIMER_LOAD_VAL);
write32(&timer0_ptr->timer_load_count1, TIMER_LOAD_VAL);
write32(&timer0_ptr->timer_load_count2, 0);
write32(&timer0_ptr->timer_load_count3, 0);
write32(&timer0_ptr->timer_ctrl_reg, 1);
}