Revert "soc/intel/apollolake: Enable LPC bus interface"
This reverts commit e976bd4469
.
The LPC resource allocation will be completely reworked in subsequent
patches. The most straightforward approach is to start by reverting
the existing code.
Change-Id: I2475542b79817020d4c956f22ed5856f05046b16
Reviewed-on: https://review.coreboot.org/14583
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
committed by
Martin Roth
parent
d5b7c55c46
commit
c1526f0458
@ -20,46 +20,6 @@
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#include <device/pci_ids.h>
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#include <soc/acpi.h>
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#include <soc/pci_ids.h>
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#include <reg_script.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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#include <soc/lpc.h>
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#include "chip.h"
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static const struct reg_script lpc_serirq_enable[] = {
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/* Setup SERIRQ, enable continuous mode */
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REG_PCI_OR8(SERIRQ_CNTL, (1 << 7) | (1 << 6)),
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#if !IS_ENABLED(CONFIG_SERIRQ_CONTINUOUS_MODE)
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REG_PCI_RMW8(SERIRQ_CNTL, ~(1 << 6), 0),
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#endif
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REG_SCRIPT_END
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};
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static void enable_lpc_decode(struct device *lpc)
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{
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const struct soc_intel_apollolake_config *config;
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if (!lpc || !lpc->chip_info)
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return;
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config = lpc->chip_info;
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/* Enable requested fixed IO decode ranges */
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pci_write_config16(lpc, LPC_EN, config->lpc_dec);
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/* Enable generic IO decode ranges */
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pci_write_config32(lpc, LPC_GEN1_DEC, config->gen1_dec);
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pci_write_config32(lpc, LPC_GEN2_DEC, config->gen2_dec);
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pci_write_config32(lpc, LPC_GEN3_DEC, config->gen3_dec);
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pci_write_config32(lpc, LPC_GEN4_DEC, config->gen4_dec);
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}
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static void lpc_init(struct device *dev)
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{
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enable_lpc_decode(dev);
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reg_script_run_on_dev(dev, lpc_serirq_enable);
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}
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static void soc_lpc_add_io_resources(device_t dev)
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{
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@ -87,7 +47,6 @@ static struct device_operations device_ops = {
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.enable_resources = &pci_dev_enable_resources,
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.write_acpi_tables = southbridge_write_acpi_tables,
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.acpi_inject_dsdt_generator = southbridge_inject_dsdt,
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.init = &lpc_init
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};
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static const struct pci_driver soc_lpc __pci_driver = {
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