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src/amd/picasso: Update reset code

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Remove the scratch register indicators.  Per AMD, AGESA no longer
uses these.  Use a new IO register to determine whether a warm
reset should occur.

Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Change-Id: I0ff7935004b3d1ac5204d3ef575cfa98116a57fa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33989
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Marshall Dawson
2019-06-25 16:06:12 -06:00
committed by Martin Roth
parent 48c5d29cde
commit c17cc63e48
3 changed files with 8 additions and 19 deletions
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23
src/soc/amd/picasso/reset.c
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@@ -25,32 +25,18 @@
void set_warm_reset_flag(void)
{
u32 htic;
htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
htic |= HTIC_COLD_RST_DET;
pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
uint8_t ncp = inw(NCP_ERR);
outb(NCP_ERR, ncp | NCP_WARM_BOOT);
}
int is_warm_reset(void)
{
u32 htic;
htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
return !!(htic & HTIC_COLD_RST_DET);
}
/* Clear bits 5, 9 & 10, used to signal the reset type */
static void clear_bios_reset(void)
{
u32 htic;
htic = pci_read_config32(SOC_HT_DEV, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_DETECT;
pci_write_config32(SOC_HT_DEV, HT_INIT_CONTROL, htic);
return !!(inb(NCP_ERR) & NCP_WARM_BOOT);
}
void do_cold_reset(void)
{
clear_bios_reset();
/* De-assert and then assert all PwrGood signals on CF9 reset. */
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) |
TOGGLE_ALL_PWR_GOOD);
@@ -60,7 +46,6 @@ void do_cold_reset(void)
void do_warm_reset(void)
{
set_warm_reset_flag();
clear_bios_reset();
/* Assert reset signals only. */
outb(RST_CMD | SYS_RST, SYS_RESET);