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mb/lenovo/x220: Remove superfluous comments related to PCI devices

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Since all devicetrees from lenovo/x220 are using the reference names for
PCI devices now, remove the equivalent comments documenting their
function.

Change-Id: Ic8bff0516811371e1fbb72765c8d03812a689701
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/79940
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Rudolph <patrick.rudolph@9elements.com>
This commit is contained in:
Felix Singer
2024-01-13 22:30:12 +01:00
committed by Felix Singer
parent 7fc6114f89
commit c1a0e128a0
3 changed files with 33 additions and 33 deletions
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52
src/mainboard/lenovo/x220/devicetree.cb
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@@ -38,9 +38,9 @@ chip northbridge/intel/sandybridge
device domain 0 on device domain 0 on
subsystemid 0x17aa 0x21db inherit subsystemid 0x17aa 0x21db inherit
device ref host_bridge on end # host bridge device ref host_bridge on end
device ref peg10 off end # PCIe Bridge for discrete graphics device ref peg10 off end
device ref igd on end # vga controller device ref igd on end
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
# GPI routing # GPI routing
@@ -68,37 +68,37 @@ chip northbridge/intel/sandybridge
register "spi_uvscc" = "0x2005" register "spi_uvscc" = "0x2005"
register "spi_lvscc" = "0x2005" register "spi_lvscc" = "0x2005"
device ref mei1 on end # Management Engine Interface 1 device ref mei1 on end
device ref mei2 off end # Management Engine Interface 2 device ref mei2 off end
device ref me_ide_r off end # Management Engine IDE-R device ref me_ide_r off end
device ref me_kt off end # Management Engine KT device ref me_kt off end
device ref gbe on device ref gbe on
subsystemid 0x17aa 0x21ce subsystemid 0x17aa 0x21ce
end # Intel Gigabit Ethernet end
device ref ehci2 on end # USB2 EHCI #2 device ref ehci2 on end
device ref hda on end # High Definition Audio device ref hda on end
device ref pcie_rp1 off end # PCIe Port #1 device ref pcie_rp1 off end
device ref pcie_rp2 on # PCIe Port #2 (wlan) device ref pcie_rp2 on
smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthShort" smbios_slot_desc "SlotTypeM2Socket1_SD" "SlotLengthShort"
"WIFI" "SlotDataBusWidth1X" "WIFI" "SlotDataBusWidth1X"
end end
device ref pcie_rp3 off end # PCIe Port #3 device ref pcie_rp3 off end
device ref pcie_rp4 on device ref pcie_rp4 on
smbios_slot_desc "7" "3" "ExpressCard Slot" "8" smbios_slot_desc "7" "3" "ExpressCard Slot" "8"
end # PCIe Port #4 end
device ref pcie_rp5 on device ref pcie_rp5 on
chip drivers/ricoh/rce822 chip drivers/ricoh/rce822
register "sdwppol" = "1" register "sdwppol" = "1"
register "disable_mask" = "0x87" register "disable_mask" = "0x87"
device pci 00.0 on end device pci 00.0 on end
end end
end # PCIe Port #5 (SD) end
device ref pcie_rp6 off end # PCIe Port #6 device ref pcie_rp6 off end
device ref pcie_rp7 on end # PCIe Port #7 Optional XHCI controller device ref pcie_rp7 on end # Optional XHCI controller
device ref pcie_rp8 off end # PCIe Port #8 device ref pcie_rp8 off end
device ref ehci1 on end # USB2 EHCI #1 device ref ehci1 on end
device ref pci_bridge off end # PCI bridge device ref pci_bridge off end
device ref lpc on #LPC bridge device ref lpc on
chip ec/lenovo/pmh7 chip ec/lenovo/pmh7
device pnp ff.1 on end # dummy device pnp ff.1 on end # dummy
register "backlight_enable" = "true" register "backlight_enable" = "true"
@@ -149,8 +149,8 @@ chip northbridge/intel/sandybridge
register "wwan_gpio_num" = "70" register "wwan_gpio_num" = "70"
register "wwan_gpio_lvl" = "0" register "wwan_gpio_lvl" = "0"
end end
end # LPC bridge end
device ref sata1 on end # SATA Controller 1 device ref sata1 on end
device ref smbus on device ref smbus on
# eeprom, 8 virtual devices, same chip # eeprom, 8 virtual devices, same chip
chip drivers/i2c/at24rf08c chip drivers/i2c/at24rf08c
@@ -163,9 +163,9 @@ chip northbridge/intel/sandybridge
device i2c 5e on end device i2c 5e on end
device i2c 5f on end device i2c 5f on end
end end
end # SMBus end
device ref sata2 off end # SATA Controller 2 device ref sata2 off end
device ref thermal on end # Thermal device ref thermal on end
end end
end end
end end

10
src/mainboard/lenovo/x220/variants/x1/overridetree.cb
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@@ -21,10 +21,10 @@ chip northbridge/intel/sandybridge
# X1 does not have ExpressCard slot # X1 does not have ExpressCard slot
register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }" register "pcie_hotplug_map" = "{ 0, 0, 0, 0, 0, 0, 0, 0 }"
device ref pcie_rp1 off end # PCIe Port #1 device ref pcie_rp1 off end
device ref pcie_rp3 off end # PCIe Port #3 device ref pcie_rp3 off end
device ref pcie_rp4 off end # PCIe Port #4 device ref pcie_rp4 off end
device ref lpc on #LPC bridge device ref lpc on
chip ec/lenovo/h8 chip ec/lenovo/h8
device pnp ff.2 on end # dummy device pnp ff.2 on end # dummy
register "config2" = "0xe0" register "config2" = "0xe0"
@@ -36,7 +36,7 @@ chip northbridge/intel/sandybridge
register "event5_enable" = "0x3c" register "event5_enable" = "0x3c"
register "evente_enable" = "0x3d" register "evente_enable" = "0x3d"
end end
end # LPC bridge end
end end
end end
end end

4
src/mainboard/lenovo/x220/variants/x220/overridetree.cb
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@@ -1,13 +1,13 @@
chip northbridge/intel/sandybridge chip northbridge/intel/sandybridge
device domain 0 on device domain 0 on
chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH chip southbridge/intel/bd82x6x # Intel Series 6 Cougar Point PCH
device ref lpc on #LPC bridge device ref lpc on
chip ec/lenovo/h8 chip ec/lenovo/h8
device pnp ff.2 on end # dummy device pnp ff.2 on end # dummy
register "eventa_enable" = "0x01" register "eventa_enable" = "0x01"
register "eventb_enable" = "0xf0" register "eventb_enable" = "0xf0"
end end
end # LPC bridge end
end end
end end
end end