Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
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Documentation/Intel/Board/board.html
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Documentation/Intel/Board/board.html
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<!DOCTYPE html>
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<html>
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<head>
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<title>Board</title>
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</head>
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<body>
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<h1>x86 Board Development</h1>
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<p>
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Board development requires System-on-a-Chip (SoC) support.
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The combined steps are listed
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<a target="_blank" href="../x86Development.html">here</a>.
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The development steps for the board are listed below:
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</p>
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<ol>
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<li><a href="#RequiredFiles">Required Files</a></li>
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</ol>
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<hr>
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<h1><a name="RequiredFiles">Required Files</a></h1>
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<p>
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Create the board directory as src/mainboard/<Vendor>/<Board>.
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</p>
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<p>
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The following files are required to build a new board:
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</p>
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<ol>
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<li>Kconfig.name - Defines the Kconfig value for the board</li>
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<li>Kconfig
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<ol type="A">
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<li>Selects the SoC for the board and specifies the SPI flash size
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<ol type="I">
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<li>BOARD_ROMSIZE_KB_<Size></li>
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<li>SOC_<Vendor>_<Chip Family></li>
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</ol>
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</li>
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<li>Declare the Kconfig values for:
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<ol type="I">
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<li>MAINBOARD_DIR</li>
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<li>MAINBOARD_PART_NUMBER</li>
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<li>MAINBOARD_VENDOR</li>
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</ol>
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</li>
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</ol>
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</li>
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<li>devicetree.cb - Enable root bridge and serial port
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<ol type="A">
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<li>The first line must be "chip soc/Intel/<soc family>";
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this path is used by the generated static.c to include the chip.h
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header file
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</li>
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</ol>
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</li>
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<li>romstage.c
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<ol type="A">
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<li>Add routine mainboard_romstage_entry which calls romstage_common</li>
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</ol>
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</li>
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<li>Configure coreboot build:
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<ol type="A">
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<li>Set LOCALVERSION</li>
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<li>FLASHMAP_OFFSET = 0x00700000</li>
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<li>Select vendor for the board</li>
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<li>Select the board</li>
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<li>CBFS_SIZE = 0x00100000</li>
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<li>Set the CPU_MICROCODE_CBFS_LEN</li>
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<li>Set the CPU_MICROCODE_CBFS_LOC</li>
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<li>Set the FSP_IMAGE_ID_STRING</li>
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<li>Set the FSP_LOC</li>
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<li>Disable GOP_SUPPORT</li>
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<li>No payload</li>
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<li>Choose the default value for all other options</li>
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</ol>
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</li>
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</ol>
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<hr>
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<p>Modified: 31 January 2016</p>
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</body>
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</html>
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100
Documentation/Intel/Board/galileo.html
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Documentation/Intel/Board/galileo.html
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<!DOCTYPE html>
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<html>
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<head>
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<title>Galileo Gen 2</title>
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</head>
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<body>
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<h1>Intel® Galileo Gen 2 Development Board</h1>
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<table>
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<tr>
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<td><a target="_blank" href="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg"><img alt="Galileo Gen 2" src="http://www.mouser.com/images/microsites/Intel_Galileo2_lrg.jpg" width=500></a></td>
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<td>
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<table>
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<tr bgcolor="#ffc0c0">
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<td>
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Warning: Use of the Intel® Galileo Gen 2 mainboard code requires modification of the
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util/xcompile/xcompile file to change the machine architecture from i686 to i586 because
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the Quark™ processor does not support the instructions introduced with the
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Pentium™ 6 architecture.
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<ol>
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<li>Edit the file util/xcompile/xcompile</li>
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<li>Search for
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xcompile;hb=HEAD#l185">-march</a></li>
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<li>Replace i686 with i586</li>
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<li>Save the result</li>
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</ol>
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Without this change the Quark™ processor will halt when it executes one of the
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instructions introduced with the Pentium™ 6 architecture.
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</td>
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</tr>
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</table>
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<p>
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The Intel® Galileo Gen 2 mainboard code was developed along with the Intel®
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<a target="_blank" href="../SoC/quark.html">Quark™</a> SoC:
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</p>
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<ul>
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<li><a target="_blank" href="../x86Development.html">Overall</a> development</li>
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<li><a target="_blank" href="../SoC/soc.html">SoC</a> support</li>
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<li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li>
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<li><a target="_blank" href="board.html">Board</a> support</li>
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</ul>
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</td>
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</tr>
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</table>
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<hr>
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<h1>Galileo Gen 2 Board Documentation</h1>
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<ul>
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<li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_blockdiagram.jpg">Block Diagram</a></li>
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<li><a target="_blank" href="https://software.intel.com/en-us/iot/library/galileo-getting-started">Getting Started</a></li>
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<li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/galileo/galileo-overview.html">Overview</a></li>
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<li><a target="_blank" href="http://files.linuxgizmos.com/intel_galileo_gen2_ports.jpg">Port Diagram</a></li>
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<li><a target="_blank" href="http://download.intel.com/support/galileo/sb/intelgalileogen2prodbrief_330736_003.pdf">Product Brief</a></li>
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<li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/galileo-g2-schematic.pdf">Schematic</a></li>
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<li><a target="_blank" href="http://download.intel.com/support/galileo/sb/galileo_boarduserguide_330237_001.pdf">User Guide</a></li>
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<li>Components
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<ul>
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<li>A/D: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/adc108s102.pdf">ADC108S102</a></li>
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<li>Analog Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/ts5a23159.pdf">TS5A23159</a></li>
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<li>Ethernet (10/100 MB/S): Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/dp83848-ep.pdf">DP83848</a></li>
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<li>Load Switch: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps22920.pdf">TPS22920x</a></li>
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<li>Memory (256 MiB): Micron <a target="_blank" href="https://www.micron.com/~/media/Documents/Products/Data%20Sheet/DRAM/DDR3/1Gb_1_35V_DDR3L.pdf">MT41K128M8</a></li>
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<li>SoC: Intel® Quark™ <a target="_blank" href="../SoC/quark.html">X-1000</a></li>
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<li>Serial EEPROM (1 KiB): ON Semiconductor® <a target="_blank" href="http://www.onsemi.com/pub_link/Collateral/CAT24C01-D.PDF">CAT24C08</a></li>
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<li>SPI Flash (8 MiB): Winbond™ <a target="_blank" href="http://www.winbond-usa.com/resource-files/w25q64fv_revl1_100713.pdf">W25Q64FV</a></li>
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<li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/slvsag7c/slvsag7c.pdf">TPS62130</a></li>
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<li>Step Down Converter: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ug/slvu570/slvu570.pdf">TPS652510</a></li>
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<li>Termination Regulator: Texas Instruments <a target="_blank" href="http://www.ti.com/lit/ds/symlink/tps51200.pdf">TPS51200</a></li>
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</ul>
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</li>
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</ul>
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<hr>
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<h1>Debug Tools</h1>
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<ul>
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<li>Flash Programmer:
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<ul>
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<li>Dediprog <a target="_blank" href="http://www.dediprog.com/pd/spi-flash-solution/SF100">SF100</a> ISP IC Programmer</li>
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</ul>
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</li>
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<li>JTAG Connector: <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-JTAG-20-10">Olimex ARM-JTAG-20-10</a></li>
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<li>JTAG Debugger:
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<ul>
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<li>Olimex LTD <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=Olimex+ARM-USB-OCD-H">ARM-USB-OCD-H</a></li>
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<li>Tincan Tools <a target="_blank" href="https://www.tincantools.com/wiki/Flyswatter2">Flyswatter2</a></li>
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</ul>
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</li>
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<li><a target="_blank" href="http://download.intel.com/support/processors/quark/sb/sourcedebugusingopenocd_quark_appnote_330015_003.pdf">Hardware Setup and Software Installation</a></li>
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<li>USB Serial cable: FTDI <a target="_blank" href="https://www.google.com/webhp?sourceid=chrome-instant&ion=1&espv=2&ie=UTF-8#q=FTDI+TTL-232R-3V3">TTL-232R-3V3</a></li>
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</ul>
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<hr>
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<p>Modified: 30 January 2016</p>
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</body>
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</html>
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