Documentation: Add x86 documentation for required files
Document the required files to perform a minimal coreboot/FSP build for x86. TEST=None Change-Id: I65b2947114634fce982ce82fb7c577fd5f47ed10 Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com> Reviewed-on: https://review.coreboot.org/13438 Tested-by: build bot (Jenkins) Reviewed-by: Martin Roth <martinroth@google.com>
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Lee Leahy
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Documentation/Intel/SoC/quark.html
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Documentation/Intel/SoC/quark.html
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<!DOCTYPE html>
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<html>
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<head>
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<title>Quark™ SoC</title>
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</head>
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<body>
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<h1>Intel® Quark™ SoC</h1>
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<table>
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<tr>
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<td><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png"><img alt="Quark Block Diagram" src="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png" width=500></a></td>
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<td>
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<table>
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<tr bgcolor="#ffc0c0">
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<td>
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Warning: Use of the Intel® Quark™ SoC code requires modification of the util/xcompile/xcompile file to change the machine
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architecture from i686 to i586 because the Quark™ processor does not support the instructions
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introduced with the Pentium™ 6 architecture.
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<ol>
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<li>Edit the file util/xcompile/xcompile</li>
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<li>Search for
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=util/xcompile/xcompile;hb=HEAD#l185">-march</a></li>
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<li>Replace i686 with i586</li>
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<li>Save the result</li>
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</ol>
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Without this change the Quark™ processor will halt when it executes one of the
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instructions introduced with the Pentium™ 6 architecture.
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</td>
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</tr>
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</table>
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<p>
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The Quark™ SoC code was developed using the
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<a target="_blank" href="../Board/galileo.html">Galileo Gen 2</a>
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board:
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</p>
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<ul>
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<li><a target="_blank" href="../x86Development.html">Overall</a> development</li>
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<li><a target="_blank" href="soc.html">SoC</a> support</li>
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<li><a target="_blank" href="../fsp1_1.html">FSP 1.1</a> integration</li>
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<li><a target="_blank" href="../Board/board.html">Board</a> support</li>
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</ul>
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</td>
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</tr>
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</table>
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<hr>
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<h1>Quark™ Documentation</h1>
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<ul>
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<li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/images/embedded/16x9/edc-quark-block-diagram-16x9.png">Block Diagram</a></li>
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<li>Intel® 64 and IA-32 Architectures <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-manual-325462.pdf">Software Developer Manual</a></li>
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<li><a target="_blank" href="http://www.intel.com/content/www/us/en/embedded/products/quark/specifications.html">Specifications</a>:
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<ul>
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<li><a target="_blank" href="http://ark.intel.com/products/79084/Intel-Quark-SoC-X1000-16K-Cache-400-MHz">X1000</a>
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- <a target="_blank" href="http://www.intel.com/content/www/us/en/search.html?keyword=X1000">Documentation</a>:
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<ul>
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<li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/quark-x1000-datasheet.pdf">Datasheet</a></li>
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<li><a target="_blank" href="http://www.intel.com/content/dam/support/us/en/documents/processors/quark/sb/intelquarkcore_devman_001.pdf">Developer's Manual</a></li>
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<li><a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/intel-quark-product-brief-v3.pdf">Product Brief</a></li>
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</ul>
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</li>
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</ul>
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</li>
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</ul>
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<hr>
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<h1>Quark™ FSP</h1>
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<ul>
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<li>Intel® Firmware Support Package External Architecture Specification <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/technical-specifications/fsp-architecture-spec-v1-1.pdf">V1.1</a></li>
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<li>Intel® Quark™ SoC X1000 <a target="_blank" href="http://www.intel.com/content/dam/www/public/us/en/documents/guides/quark-x1000-uefi-firmware-writers-guide.pdf">UEFI Firmware Writer's Guide</a></li>
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<li>EDK2 Sources:
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<ul>
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<li>EDK2: git clone <a target="_blank" href="https://github.com/tianocore/edk2.git">https://github.com/tianocore/edk2.git</a></li>
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<li>EDK2-FatPkg: git clone <a target="_blank" href="https://github.com/tianocore/edk2-FatPkg.git">https://github.com/tianocore/edk2-FatPkg.git</a> FatPkg</li>
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<li>EDK2-non-osi: git clone <a target="_blank" href="https://github.com/tianocore/edk2-non-osi.git">https://github.com/tianocore/edk2-non-osi.git</a></li>
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<li>Win32 BaseTools: git clone <a target="_blank" href="https://github.com/tianocore/edk2-BaseTools-win32.git">https://github.com/tianocore/edk2-BaseTools-win32.git</a></li>
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</ul>
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</li>
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<li>Win32 Build Instructions:
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<pre><code>set WORKSPACE=%CD%
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set PACKAGES_PATH=%WORKSPACE%\edk2;%WORKSPACE%\FatPkg;%WORKSPACE%\edk2-non-osi
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set EDK_TOOLS_BIN=%WORKSPACE%\edk2-BaseTools-win32
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cd edk2
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edksetup.bat
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build -p QuarkPlatformPkg/Quark.dsc -a IA32 -t VS2012x86 -b DEBUG -DDEBUG_PROPERTY_MASK=0x27 -DDEBUG_PRINT_ERROR_LEVEL=0x80000042
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</code></pre>
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</li>
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</ul>
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<hr>
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<p>Modified: 30 January 2016</p>
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</body>
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</html>
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105
Documentation/Intel/SoC/soc.html
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Documentation/Intel/SoC/soc.html
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<!DOCTYPE html>
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<html>
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<head>
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<title>SoC</title>
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</head>
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<body>
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<h1>x86 System on a Chip (SoC) Development</h1>
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<p>
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SoC development is best done in parallel with development for a specific
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board. The combined steps are listed
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<a target="_blank" href="../x86Development.html">here</a>.
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The development steps for the SoC are listed below:
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</p>
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<ol>
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<li><a target="_blank" href="../fsp1_1.html#RequiredFiles">FSP 1.1</a> required files</li>
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<li>SoC <a href="#RequiredFiles">Required Files</a></li>
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<li><a href="#Descriptor">Start Booting</a></li>
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<li><a href="#EarlyDebug">Early Debug</a></li>
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</ol>
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<hr>
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<h1><a name="RequiredFiles">Required Files</a></h1>
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<p>
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Create the directory as src/soc/<Vendor>/<Chip Family>.
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</p>
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<p>
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The following files are required to build a new SoC:
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</p>
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<ul>
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<li>Include files
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<ul>
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<li>include/soc/pei_data.h</li>
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<li>include/soc/pm.h</li>
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</ul>
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</li>
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<li>Kconfig - Defines the Kconfig value for the SoC and selects the tool
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chains for the various stages:
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<ul>
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<li>select ARCH_BOOTBLOCK_<Tool Chain></li>
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<li>select ARCH_RAMSTAGE_<Tool Chain></li>
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<li>select ARCH_ROMSTAGE_<Tool Chain></li>
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<li>select ARCH_VERSTAGE_<Tool Chain></li>
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</ul>
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</li>
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<li>Makefile.inc - Specify the include paths</li>
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<li>memmap.c - Top of usable RAM</li>
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</ul>
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<hr>
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<h1><a name="Descriptor">Start Booting</a></h1>
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<p>
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Some SoC parts require additional firmware components in the flash.
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This section describes how to add those pieces.
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</p>
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<h2>Intel Firmware Descriptor</h2>
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<p>
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The Intel Firmware Descriptor (IFD) is located at the base of the flash part.
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The following command overwrites the base of the flash image with the Intel
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Firmware Descriptor:
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</p>
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<pre><code>dd if=descriptor.bin of=build/coreboot.rom conv=notrunc >/dev/null 2>&1</code></pre>
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<h2><a name="MEB">Management Engine Binary</a></h2>
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<p>
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Some SoC parts contain and require that the Management Engine (ME) be running
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before it is possible to bring the x86 processor out of reset. A binary file
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containing the management engine code must be added to the firmware using the
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ifdtool. The following commands add this binary blob:
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</p>
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<pre><code>util/ifdtool/ifdtool -i ME:me.bin build/coreboot.rom
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mv build/coreboot.rom.new build/coreboot.rom
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</code></pre>
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<h2><a name="EarlyDebug">Early Debug</a></h2>
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<p>
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Early debugging between the reset vector and the time the serial port is enabled
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is most easily done by writing values to port 0x80.
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</p>
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<h2>Success</h2>
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<p>
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When the reset vector is successfully invoked, port 0x80 will output the following value:
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</p>
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<ul>
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<li>0x01: <a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/include/console/post_codes.h;hb=HEAD#l45">POST_RESET_VECTOR_CORRECT</a>
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- Bootblock successfully executed the
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/reset16.inc;hb=HEAD#l4">reset vector</a>
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and entered the 16-bit code at
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<a target="_blank" href="http://review.coreboot.org/gitweb?p=coreboot.git;a=blob;f=src/cpu/x86/16bit/entry16.inc;hb=HEAD#l35">_start</a>
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</li>
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</ul>
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<hr>
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<p>Modified: 31 January 2016</p>
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</body>
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</html>
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