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mb/google/myst: Add eMMC/NVMe config support

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Add FW_CONFIG item for eMMC/NVMe support and address the init
of the lanes based on said config.

BUG=b:278877257
TEST=builds

Change-Id: Id6452f497cf78549b7d6126f1b55cd6d45b403c3
Signed-off-by: Jon Murphy <jpmurphy@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74957
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Van Patten <timvp@google.com>
Reviewed-by: Mark Hasemeyer <markhas@google.com>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
Jon Murphy 2023-05-03 20:48:26 -06:00 committed by Felix Held
parent 33c666587a
commit c20afb801a
3 changed files with 49 additions and 15 deletions
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54
src/mainboard/google/myst/port_descriptors.c
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@ -1,12 +1,14 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <baseboard/variants.h> #include <baseboard/variants.h>
#include <console/console.h>
#include <fw_config.h>
#include <gpio.h> #include <gpio.h>
#include <soc/platform_descriptors.h> #include <soc/platform_descriptors.h>
#include <types.h> #include <types.h>
static const fsp_dxio_descriptor myst_dxio_descriptors[] = { static fsp_dxio_descriptor myst_dxio_descriptors[] = {
{ /* WWAN */ [DXIO_WWAN] = {
.engine_type = UNUSED_ENGINE, .engine_type = UNUSED_ENGINE,
.port_present = true, .port_present = true,
.start_logical_lane = 13, .start_logical_lane = 13,
@ -17,7 +19,7 @@ static const fsp_dxio_descriptor myst_dxio_descriptors[] = {
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ2, .clk_req = CLK_REQ2,
}, },
{ /* WLAN */ [DXIO_WLAN] = {
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.port_present = true, .port_present = true,
.start_logical_lane = 14, .start_logical_lane = 14,
@ -28,7 +30,7 @@ static const fsp_dxio_descriptor myst_dxio_descriptors[] = {
.turn_off_unused_lanes = true, .turn_off_unused_lanes = true,
.clk_req = CLK_REQ0, .clk_req = CLK_REQ0,
}, },
{ /* SD */ [DXIO_SD] = {
.engine_type = PCIE_ENGINE, .engine_type = PCIE_ENGINE,
.port_present = true, .port_present = true,
.start_logical_lane = 15, .start_logical_lane = 15,
@ -40,17 +42,31 @@ static const fsp_dxio_descriptor myst_dxio_descriptors[] = {
.link_hotplug = 3, .link_hotplug = 3,
.clk_req = CLK_REQ1, .clk_req = CLK_REQ1,
}, },
{ /* SSD */ [DXIO_STORAGE] = { 0 },
.engine_type = PCIE_ENGINE, };
.port_present = true,
.start_logical_lane = 16, static const fsp_dxio_descriptor emmc_descriptor = {
.end_logical_lane = 19, .engine_type = PCIE_ENGINE,
.device_number = PCI_SLOT(NVME_DEVFN), .port_present = true,
.function_number = PCI_FUNC(NVME_DEVFN), .start_logical_lane = 16,
.link_speed_capability = GEN_MAX, .end_logical_lane = 16,
.turn_off_unused_lanes = true, .device_number = PCI_SLOT(NVME_DEVFN),
.clk_req = CLK_REQ3, .function_number = PCI_FUNC(NVME_DEVFN),
}, .link_speed_capability = GEN_MAX,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ3,
};
static const fsp_dxio_descriptor nvme_descriptor = {
.engine_type = PCIE_ENGINE,
.port_present = true,
.start_logical_lane = 16,
.end_logical_lane = 19,
.device_number = PCI_SLOT(NVME_DEVFN),
.function_number = PCI_FUNC(NVME_DEVFN),
.link_speed_capability = GEN_MAX,
.turn_off_unused_lanes = true,
.clk_req = CLK_REQ3,
}; };
static const fsp_ddi_descriptor myst_ddi_descriptors[] = { static const fsp_ddi_descriptor myst_ddi_descriptors[] = {
@ -85,6 +101,14 @@ void mainboard_get_dxio_ddi_descriptors(
const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num, const fsp_dxio_descriptor **dxio_descs, size_t *dxio_num,
const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num) const fsp_ddi_descriptor **ddi_descs, size_t *ddi_num)
{ {
if (fw_config_is_provisioned() && fw_config_probe(FW_CONFIG(STORAGE, NVME))) {
printk(BIOS_DEBUG, "Enabling NVMe.\n");
myst_dxio_descriptors[DXIO_STORAGE] = nvme_descriptor;
} else {
printk(BIOS_DEBUG, "Enabling eMMC.\n");
myst_dxio_descriptors[DXIO_STORAGE] = emmc_descriptor;
}
*dxio_descs = myst_dxio_descriptors; *dxio_descs = myst_dxio_descriptors;
*dxio_num = ARRAY_SIZE(myst_dxio_descriptors); *dxio_num = ARRAY_SIZE(myst_dxio_descriptors);
*ddi_descs = myst_ddi_descriptors; *ddi_descs = myst_ddi_descriptors;

6
src/mainboard/google/myst/variants/baseboard/include/baseboard/variants.h
View File

@ -12,6 +12,12 @@
#define SD_DEVFN PCIE_GPP_2_3_DEVFN #define SD_DEVFN PCIE_GPP_2_3_DEVFN
#define NVME_DEVFN PCIE_GPP_2_4_DEVFN #define NVME_DEVFN PCIE_GPP_2_4_DEVFN
enum dxio_port_id {
DXIO_WWAN,
DXIO_WLAN,
DXIO_SD,
DXIO_STORAGE
};
/* This function provides base GPIO configuration table. */ /* This function provides base GPIO configuration table. */
void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size); void baseboard_gpio_table(const struct soc_amd_gpio **gpio, size_t *size);

4
src/mainboard/google/myst/variants/myst/overridetree.cb
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@ -26,6 +26,10 @@ fw_config
option DISABLED 0 option DISABLED 0
option ENABLED 1 option ENABLED 1
end end
field STORAGE 11
option EMMC 0
option NVME 1
end
end end
chip soc/amd/phoenix chip soc/amd/phoenix