From c2310a16adaca7ac32f21c083258ceb27d12ab89 Mon Sep 17 00:00:00 2001 From: Karthikeyan Ramasubramanian Date: Tue, 31 Aug 2021 12:39:47 -0600 Subject: [PATCH] soc/amd/cezanne: Increase the FSP_M_SIZE configuration On mainboards with Cezanne SOC, serial enabled FSP_M binary size is greater than the size allocated in DRAM. Increase the allocated size for FSP_M binary in DRAM to handle both debug and release FSP_M binaries. Also adjust the verstage load address accordingly. BUG=None TEST=Build and boot to OS in guybrush with both debug and release FSP_M. Perform warm, cold reboot and suspend/resume cycling for 10 iterations. Change-Id: Ic6f90041e258039e691cbdb3a978cfe1f782642a Signed-off-by: Karthikeyan Ramasubramanian Reviewed-on: https://review.coreboot.org/c/coreboot/+/57293 Reviewed-by: Furquan Shaikh Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/cezanne/Kconfig | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/amd/cezanne/Kconfig b/src/soc/amd/cezanne/Kconfig index 81597d075c..46e60173c6 100644 --- a/src/soc/amd/cezanne/Kconfig +++ b/src/soc/amd/cezanne/Kconfig @@ -166,7 +166,7 @@ config FSP_M_ADDR config FSP_M_SIZE hex - default 0x80000 + default 0xC0000 help Sets the size of DRAM allocation for FSP-M in linker script. @@ -179,7 +179,7 @@ config FSP_TEMP_RAM_SIZE config VERSTAGE_ADDR hex depends on VBOOT_SEPARATE_VERSTAGE - default 0x2140000 + default 0x2180000 help Sets the address in DRAM where verstage should be loaded if running as a separate stage on x86.