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src: Update bare access to BOOL CONFIG_ vals to CONFIG()

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BOOL type Kconfig values should be used through the CONFIG() macro.
These instances were not, so update them.

Signed-off-by: Martin Roth <martin@coreboot.org>
Change-Id: Ie4706d82c12c487607bbf5ad8059922e0e586858
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43825
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Martin Roth
2020-07-24 12:26:21 -06:00
committed by Patrick Georgi
parent f48acbda7b
commit c25c1ebd9e
8 changed files with 15 additions and 15 deletions
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6
src/soc/intel/tigerlake/fsp_params.c
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@ -109,7 +109,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->CpuMpPpi = (uintptr_t) mp_fill_ppi_services_data();
params->SkipMpInit = 0;
} else {
params->SkipMpInit = !CONFIG_USE_INTEL_FSP_MP_INIT;
params->SkipMpInit = !CONFIG(USE_INTEL_FSP_MP_INIT);
}
/* D3Hot and D3Cold for TCSS */
@ -277,8 +277,8 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
params->ThcPort1Assignment = dev->enabled ? THC_1 : THC_NONE;
/* Legacy 8254 timer support */
params->Enable8254ClockGating = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGatingOnS3 = !CONFIG_USE_LEGACY_8254_TIMER;
params->Enable8254ClockGating = !CONFIG(USE_LEGACY_8254_TIMER);
params->Enable8254ClockGatingOnS3 = !CONFIG(USE_LEGACY_8254_TIMER);
/* Enable Hybrid storage auto detection */
if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && cse_is_hfs3_fw_sku_lite()