arch/x86/ioapic: Select IOAPIC with SMP

For coreboot proper, I/O APIC programming is not really required,
except for the APIC ID field. We generally do not guard the related
set_ioapic_id() or setup_ioapic() calls with CONFIG(IOAPIC).
In practice it's something one cannot leave unselected, but maintain
the Kconfig for the time being.

Change-Id: I6e83efafcf6e81d1dfd433fab1e89024d984cc1f
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55291
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Raul Rangel <rrangel@chromium.org>
This commit is contained in:
Kyösti Mälkki
2021-06-06 08:28:16 +03:00
committed by Felix Held
parent 4bab5691cc
commit c25ecb5443
27 changed files with 1 additions and 26 deletions

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@@ -10,7 +10,6 @@ if SOUTHBRIDGE_AMD_AGESA_HUDSON || SOUTHBRIDGE_AMD_AGESA_YANGTZE
config SOUTHBRIDGE_SPECIFIC_OPTIONS
def_bool y
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_CF9_RESET
select HAVE_CF9_RESET_PREPARE

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@@ -3,7 +3,6 @@
config SOUTHBRIDGE_AMD_CIMX_SB800
bool
default n
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select AMD_SB_CIMX
select HAVE_CF9_RESET

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@@ -10,7 +10,6 @@ if SOUTHBRIDGE_AMD_PI_AVALON || SOUTHBRIDGE_AMD_PI_KERN
config SOUTHBRIDGE_SPECIFIC_OPTIONS
def_bool y
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_CF9_RESET
select HAVE_CF9_RESET_PREPARE

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@@ -23,7 +23,6 @@ config SOUTH_BRIDGE_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select IOAPIC
select HAVE_USBDEBUG_OPTIONS
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT

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@@ -3,7 +3,6 @@
config SOUTHBRIDGE_INTEL_I82801DX
bool
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select IOAPIC
select HAVE_SMI_HANDLER
select SOUTHBRIDGE_INTEL_COMMON_SMBUS
select SOUTHBRIDGE_INTEL_COMMON_EARLY_SMBUS

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@@ -5,7 +5,6 @@ config SOUTHBRIDGE_INTEL_I82801GX
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select ACPI_SOC_NVS
select AZALIA_PLUGIN_SUPPORT
select IOAPIC
select USE_WATCHDOG_ON_BOOT
select HAVE_SMI_HANDLER
select SOUTHBRIDGE_INTEL_COMMON_GPIO

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@@ -8,7 +8,6 @@ config SOUTHBRIDGE_INTEL_I82801IX
select HAVE_SMI_HANDLER if !NO_SMM
select HAVE_USBDEBUG_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select IOAPIC
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB

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@@ -9,7 +9,6 @@ config SOUTHBRIDGE_INTEL_I82801JX
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
select INTEL_DESCRIPTOR_MODE_CAPABLE
select IOAPIC
select SOUTHBRIDGE_INTEL_COMMON_GPIO
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select SOUTHBRIDGE_INTEL_COMMON_PMCLIB

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@@ -9,7 +9,6 @@ config SOUTH_BRIDGE_OPTIONS
def_bool y
select ACPI_INTEL_HARDWARE_SLEEP_VALUES
select AZALIA_PLUGIN_SUPPORT
select IOAPIC
select HAVE_SMI_HANDLER
select USE_WATCHDOG_ON_BOOT
select PCIEXP_ASPM

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@@ -19,7 +19,6 @@ config SOUTH_BRIDGE_OPTIONS
select SOUTHBRIDGE_INTEL_COMMON_PMBASE
select SOUTHBRIDGE_INTEL_COMMON_RTC
select SOUTHBRIDGE_INTEL_COMMON_RESET
select IOAPIC
select HAVE_SMI_HANDLER
select HAVE_USBDEBUG_OPTIONS
select USE_WATCHDOG_ON_BOOT