This patch adds (initial) support for the Kontron KT690 mainboard.
It's an embedded AMD 690/SB600 mainboard with a Mobile Sempron CPU. Issues with this port: - hangs early during "Starting Windows" with Windows 7, after loading all the drivers - sound is untested and probably not working - powernow seems to be not working Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4764 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Stefan Reinauer
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Stefan Reinauer
Stefan Reinauer
parent
45cbc35abb
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c270e896f0
257
src/mainboard/kontron/kt690/mainboard.c
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257
src/mainboard/kontron/kt690/mainboard.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2008 Advanced Micro Devices, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <console/console.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <arch/io.h>
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#include <boot/coreboot_tables.h>
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#include <cpu/x86/msr.h>
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#include <cpu/amd/mtrr.h>
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#include <device/pci_def.h>
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#include <../southbridge/amd/sb600/sb600.h>
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#include "chip.h"
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#define ADT7461_ADDRESS 0x4C
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#define ARA_ADDRESS 0x0C /* Alert Response Address */
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#define SMBUS_IO_BASE 0x1000
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extern int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address);
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extern int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address,
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u8 val);
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extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
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uint64_t start, uint64_t size);
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#define ADT7461_read_byte(address) \
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do_smbus_read_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address)
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#define ARA_read_byte(address) \
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do_smbus_read_byte(SMBUS_IO_BASE, ARA_ADDRESS, address)
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#define ADT7461_write_byte(address, val) \
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do_smbus_write_byte(SMBUS_IO_BASE, ADT7461_ADDRESS, address, val)
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uint64_t uma_memory_base, uma_memory_size;
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/********************************************************
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* dbm690t uses a BCM5789 as on-board NIC.
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* It has a pin named LOW_POWER to enable it into LOW POWER state.
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* In order to run NIC, we should let it out of Low power state. This pin is
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* controlled by sb600 GPM3.
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* RRG4.2.3 GPM as GPIO
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* GPM pins can be used as GPIO. The GPM I/O functions is controlled by three registers:
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* I/O C50, C51, C52, PM I/O94, 95, 96.
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* RRG4.2.3.1 GPM pins as Input
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* RRG4.2.3.2 GPM pins as Output
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********************************************************/
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static void enable_onboard_nic()
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{
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u8 byte;
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printk_info("%s.\n", __func__);
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/* set index register 0C50h to 13h (miscellaneous control) */
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outb(0x13, 0xC50); /* CMIndex */
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/* set CM data register 0C51h bits [7:6] to 01b to set Input/Out control */
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byte = inb(0xC51);
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byte &= 0x3F;
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byte |= 0x40;
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outb(byte, 0xC51);
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/* set GPM port 0C52h bit 3 to 0 to enable output for GPM3 */
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byte = inb(0xC52);
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byte &= ~0x8;
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outb(byte, 0xC52);
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/* set CM data register 0C51h bits [7:6] to 10b to set Output state control */
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byte = inb(0xC51);
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byte &= 0x3F;
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byte |= 0x80; /* 7:6=10 */
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outb(byte, 0xC51);
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/* set GPM port 0C52h bit 3 to 0 to output 0 on GPM3 */
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byte = inb(0xC52);
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byte &= ~0x8;
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outb(byte, 0xC52);
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}
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/********************************************************
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* dbm690t uses SB600 GPIO9 to detect IDE_DMA66.
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* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
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* get the cable type, 40 pin or 80 pin?
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********************************************************/
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static void get_ide_dma66()
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{
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u8 byte;
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struct device *sm_dev;
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struct device *ide_dev;
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printk_info("%s.\n", __func__);
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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byte = pci_read_config8(sm_dev, 0xA9);
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byte |= (1 << 5); /* Set Gpio9 as input */
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pci_write_config8(sm_dev, 0xA9, byte);
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ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
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byte = pci_read_config8(ide_dev, 0x56);
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byte &= ~(7 << 0);
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if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
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byte |= 2 << 0; /* mode 2 */
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else
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byte |= 5 << 0; /* mode 5 */
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pci_write_config8(ide_dev, 0x56, byte);
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}
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/*
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* set thermal config
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*/
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static void set_thermal_config()
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{
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u8 byte;
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u16 word;
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device_t sm_dev;
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/* set ADT 7461 */
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ADT7461_write_byte(0x0B, 0x50); /* Local Temperature Hight limit */
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ADT7461_write_byte(0x0C, 0x00); /* Local Temperature Low limit */
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ADT7461_write_byte(0x0D, 0x50); /* External Temperature Hight limit High Byte */
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ADT7461_write_byte(0x0E, 0x00); /* External Temperature Low limit High Byte */
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ADT7461_write_byte(0x19, 0x55); /* External THERM limit */
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ADT7461_write_byte(0x20, 0x55); /* Local THERM limit */
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byte = ADT7461_read_byte(0x02); /* read status register to clear it */
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ARA_read_byte(0x05); /* A hardware alert can only be cleared by the master sending an ARA as a read command */
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printk_info("Init adt7461 end , status 0x02 %02x\n", byte);
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/* sb600 settings for thermal config */
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/* set SB600 GPIO 64 to GPIO with pull-up */
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byte = pm2_ioread(0x42);
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byte &= 0x3f;
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pm2_iowrite(0x42, byte);
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/* set GPIO 64 to input */
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sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
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word = pci_read_config16(sm_dev, 0x56);
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word |= 1 << 7;
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pci_write_config16(sm_dev, 0x56, word);
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/* set GPIO 64 internal pull-up */
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byte = pm2_ioread(0xf0);
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byte &= 0xee;
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pm2_iowrite(0xf0, byte);
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/* set Talert to be active low */
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byte = pm_ioread(0x67);
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byte &= ~(1 << 5);
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pm_iowrite(0x67, byte);
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/* set Talert to generate ACPI event */
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byte = pm_ioread(0x3c);
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byte &= 0xf3;
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pm_iowrite(0x3c, byte);
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/* THERMTRIP pin */
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/* byte = pm_ioread(0x68);
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* byte |= 1 << 3;
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* pm_iowrite(0x68, byte);
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*
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* byte = pm_ioread(0x55);
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* byte |= 1 << 0;
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* pm_iowrite(0x55, byte);
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*
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* byte = pm_ioread(0x67);
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* byte &= ~( 1 << 6);
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* pm_iowrite(0x67, byte);
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*/
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}
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/*************************************************
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* enable the dedicated function in dbm690t board.
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* This function called early than rs690_enable.
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*************************************************/
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void kt690_enable(device_t dev)
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{
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struct mainboard_config *mainboard =
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(struct mainboard_config *)dev->chip_info;
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printk_info("Mainboard KT690 Enable. dev=0x%p\n", dev);
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#if (CONFIG_GFXUMA == 1)
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msr_t msr, msr2;
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/* TOP_MEM: the top of DRAM below 4G */
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msr = rdmsr(TOP_MEM);
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printk_info("%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
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__func__, msr.lo, msr.hi);
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/* TOP_MEM2: the top of DRAM above 4G */
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msr2 = rdmsr(TOP_MEM2);
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printk_info("%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
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__func__, msr2.lo, msr2.hi);
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switch (msr.lo) {
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case 0x10000000: /* 256M system memory */
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uma_memory_size = 0x2000000; /* 32M recommended UMA */
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break;
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case 0x18000000: /* 384M system memory */
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uma_memory_size = 0x4000000; /* 64M recommended UMA */
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break;
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case 0x20000000: /* 512M system memory */
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uma_memory_size = 0x4000000; /* 64M recommended UMA */
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break;
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default: /* 1GB and above system memory */
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uma_memory_size = 0x8000000; /* 128M recommended UMA */
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break;
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}
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uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
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printk_info("%s: uma size 0x%08llx, memory start 0x%08llx\n",
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__func__, uma_memory_size, uma_memory_base);
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/* TODO: TOP_MEM2 */
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#else
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uma_memory_size = 0x8000000; /* 128M recommended UMA */
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uma_memory_base = 0x38000000; /* 1GB system memory supposed */
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#endif
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enable_onboard_nic();
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get_ide_dma66();
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set_thermal_config();
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}
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int add_mainboard_resources(struct lb_memory *mem)
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{
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/* UMA is removed from system memory in the northbridge code, but
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* in some circumstances we want the memory mentioned as reserved.
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*/
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#if (CONFIG_GFXUMA == 1)
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printk_info("uma_memory_base=0x%llx, uma_memory_size=0x%llx \n",
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uma_memory_base, uma_memory_size);
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lb_add_memory_range(mem, LB_MEM_RESERVED,
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uma_memory_base, uma_memory_size);
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#endif
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}
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struct chip_operations mainboard_ops = {
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CHIP_NAME("Kontron KT690/mITX Mainboard")
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.enable_dev = kt690_enable,
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};
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